357
32072H–AVR32–10/2012
AT32UC3A3
19.12.5
Control Register for Channel x High
Name: CTLxH
Access Type: Read/Write
Offset:
0x01C + [x * 0x58]
Reset Value:
0x00000002
• DONE: Done Bit
Software can poll this bit to see when a block transfer is complete
• BLOCK_TS: Block Transfer Size
When the DMACA is flow controller, this field is written by the user before the channel is enabled to indicate the block size.
The number programmed into BLOCK_TS indicates the total number of single transactions to perform for every block
transfer, unless the transfer is already in progress, in which case the value of BLOCK_TS indicates the number of single
transactions that have been performed so far.
The width of the single transaction is determined by CTLx.SRC_TR_WIDTH.
31
30
29
28
27
26
25
24
-
-
-
-
-
-
-
-
23
22
21
20
19
18
17
16
-
-
-
-
-
-
-
-
15
14
13
12
11
10
9
8
-
-
-
DONE
BLOCK_TS[11:8]
7
6
5
4
3
2
1
0
BLOCK_TS[7:0]
Summary of Contents for AT32UC3A3128
Page 61: ...61 32072H AVR32 10 2012 AT32UC3A3 PLLEN PLL Enable 0 PLL is disabled 1 PLL is enabled...
Page 592: ...592 32072H AVR32 10 2012 AT32UC3A3 Manchester Configuration Register on page 614...
Page 989: ...989 32072H AVR32 10 2012 AT32UC3A3 37 2 Package Drawings Figure 37 1 TFBGA 144 package drawing...
Page 991: ...991 32072H AVR32 10 2012 AT32UC3A3 Figure 37 3 VFBGA 100 package drawing...
