Atmel AT32UC3A3128, Manual

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32072H–AVR32–10/2012
AT32UC3A3
19.5 Functional Description
19.5.1 Basic Definitions
Source peripheral: Device on a System Bus layer from where the DMACA reads data, which is
then stored in the channel FIFO. The source peripheral teams up with a destination peripheral to
form a channel.
Destination peripheral: Device to which the DMACA writes the stored data from the FIFO (pre-
viously read from the source peripheral).
Memory: Source or destination that is always “ready” for a DMA transfer and does not require a
handshaking interface to interact with the DMACA. A peripheral should be assigned as memory
only if it does not insert more than 16 wait states. If more than 16 wait states are required, then
the peripheral should use a handshaking interface (the default if the peripheral is not pro-
grammed to be memory) in order to signal when it is ready to accept or supply data.
Channel: Read/write datapath between a source peripheral on one configured System Bus
layer and a destination peripheral on the same or different System Bus layer that occurs through
the channel FIFO. If the source peripheral is not memory, then a source handshaking interface
is assigned to the channel. If the destination peripheral is not memory, then a destination hand-
shaking interface is assigned to the channel. Source and destination handshaking interfaces can
be assigned dynamically by programming the channel registers.
Master interface: DMACA is a master on the HSB bus reading data from the source and writing
it to the destination over the HSB bus.
Slave interface: The HSB interface over which the DMACA is programmed. The slave interface
in practice could be on the same layer as any of the master interfaces or on a separate layer.
Handshaking interface: A set of signal registers that conform to a protocol and handshake
between the DMACA and source or destination peripheral to control the transfer of a single or
burst transaction between them. This interface is used to request, acknowledge, and control a
DMACA transaction. A channel can receive a request through one of three types of handshaking
interface: hardware, software, or peripheral interrupt.
Hardware handshaking interface: Uses hardware signals to control the transfer of a single or
burst transaction between the DMACA and the source or destination peripheral.
Software handshaking interface: Uses software registers to control the transfer of a single or
burst transaction between the DMACA and the source or destination peripheral. No special
DMACA handshaking signals are needed on the I/O of the peripheral. This mode is useful for
interfacing an existing peripheral to the DMACA without modifying it.
Peripheral interrupt handshaking interface: A simple use of the hardware handshaking inter-
face. In this mode, the interrupt line from the peripheral is tied to the dma_req input of the
hardware handshaking interface. Other interface signals are ignored.
Flow controller: The device (either the DMACA or source/destination peripheral) that deter-
mines the length of and terminates a DMA block transfer. If the length of a block is known before
enabling the channel, then the DMACA should be programmed as the flow controller. If the
length of a block is not known prior to enabling the channel, the source or destination peripheral
needs to terminate a block transfer. In this mode, the peripheral is the flow controller.
Flow control mode (CFGx.FCMODE): Special mode that only applies when the destination
peripheral is the flow controller. It controls the pre-fetching of data from the source peripheral.