Atmel AT32UC3A3128, Manual

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734
32072H–AVR32–10/2012
AT32UC3A3
This bit is cleared when the NAKEDIC bit written to one.
• PERRI: Pipe Error Interrupt
This bit is set when an error occurs on the current bank of the pipe. This triggers an interrupt if the PERRE bit is set. Refers to
the UPERRn register to determine the source of the error.
This bit is cleared when the error source bit is cleared.
• TXSTPI: Transmitted SETUP Interrupt
This bit is set, for Control endpoints, when the current SETUP bank is free and can be filled. This triggers an interrupt if the
TXSTPE bit is one.
This bit is cleared when the TXSTPIC bit is written to one.
• UNDERFI: Underflow Interrupt
This bit is set, for isochronous and Interrupt IN/OUT pipe, when an error flow occurs. This triggers an interrupt if the UNDERFIE
bit is one.
This bit is set, for Isochronous or interrupt OUT pipe, when a transaction underflow occurs in the current pipe. (the pipe can’t
send the OUT data packet in time because the current bank is not ready). A zero-length-packet (ZLP) will be sent instead of.
This bit is set, for Isochronous or interrupt IN pipe, when a transaction flow error occurs in the current pipe. i.e, the current bank
of the pipe is not free whereas a new IN USB packet is received. This packet is not stored in the bank. For Interrupt pipe, the
overflowed packet is ACKed to respect the USB standard.
This bit is cleared when the UNDERFIEC bit is written to one.
• TXOUTI: Transmitted OUT Data Interrupt
This bit is set when the current OUT bank is free and can be filled. This triggers an interrupt if the TXOUTE bit is one.
This bit is cleared when the TXOUTIC bit is written to one.
• RXINI: Received IN Data Interrupt
This bit is set when a new USB message is stored in the current bank of the pipe. This triggers an interrupt if the RXINE bit is
one.
This bit is cleared when the RXINIC bit is written to one.