Atmel AT32UC3A3128, Manual

Page: 209 / 1021

209
32072H–AVR32–10/2012
AT32UC3A3
Figure 15-32. Recommended Procedure to Switch from Slow Clock Mode to Normal Mode or from Normal Mode to Slow
Clock Mode
15.6.9 Asynchronous Page Mode
The SMC supports asynchronous burst reads in page mode, providing that the Page Mode
Enabled bit is written to one in the MODE register (MODE.PMEN). The page size must be con-
figured in the Page Size field in the MODE register (MODE.PS) to 4, 8, 16, or 32 bytes.
The page defines a set of consecutive bytes into memory. A 4-byte page (resp. 8-, 16-, 32-byte
page) is always aligned to 4-byte boundaries (resp. 8-, 16-, 32-byte boundaries) of memory. The
MSB of data address defines the address of the page in memory, the LSB of address define the
address of the data in the page as detailed in
Table 15-6 on page 209 .
With page mode memory devices, the first access to one page (t
pa
) takes longer than the subse-
quent accesses to the page (t
sa
) as shown in Figure 15-33 on page 210 . When in page mode,
the SMC enables the user to define different read timings for the first access within one page,
and next accesses within the page.
Notes: 1. A denotes the address bus of the memory device
2. For 16-bit devices, the bit 0 of address is ignored.
15.6.9.1 Protocol and timings in page mode
Figure 15-33 on page 210 shows the NRD and NCS timings in page mode access.
CLK_SMC
Slow Clock Mode
Internal signal from PM
A[AD_MSB:2]
NBS0, NBS1,
A0, A1
NWE
NCS
1 1
SLOW CLOCK MODE WRITE
2 3 2
IDLE STATE
Reload Configuration
Wait State
NORMAL MODE WRITE
1
Table 15-6. Page Address and Data Address within a Page
Page Size Page Address
(1)
Data Address in the Page
(2)
4 bytes A[23:2] A[1:0]
8 bytes A[23:3] A[2:0]
16 bytes A[23:4] A[3:0]
32 bytes A[23:5] A[4:0]