364
32072H–AVR32–10/2012
AT32UC3A3
19.12.10 Interrupt Registers
The following sections describe the registers pertaining to interrupts, their status, and how to clear them. For each channel,
there are five types of interrupt sources:
• IntTfr: DMA Transfer Complete Interrupt
This interrupt is generated on DMA transfer completion to the destination peripheral.
• IntBlock: Block Transfer Complete Interrupt
This interrupt is generated on DMA block transfer completion to the destination peripheral.
• IntSrcTran: Source Transaction Complete Interrupt
This interrupt is generated after completion of the last System Bus transfer of the requested single/burst transaction from
the handshaking interface on the source side.
If the source for a channel is memory, then that channel never generates a IntSrcTran interrupt and hence the correspond-
ing bit in this field is not set.
• IntDstTran: Destination Transaction Complete Interrupt
This interrupt is generated after completion of the last System Bus transfer of the requested single/burst transaction from
the handshaking interface on the destination side.
If the destination for a channel is memory, then that channel never generates the IntDstTran interrupt and hence the corre-
sponding bit in this field is not set.
• IntErr: Error Interrupt
This interrupt is generated when an ERROR response is received from an HSB slave on the HRESP bus during a DMA
transfer. In addition, the DMA transfer is cancelled and the channel is disabled.
Summary of Contents for AT32UC3A3128
Page 61: ...61 32072H AVR32 10 2012 AT32UC3A3 PLLEN PLL Enable 0 PLL is disabled 1 PLL is enabled...
Page 592: ...592 32072H AVR32 10 2012 AT32UC3A3 Manchester Configuration Register on page 614...
Page 989: ...989 32072H AVR32 10 2012 AT32UC3A3 37 2 Package Drawings Figure 37 1 TFBGA 144 package drawing...
Page 991: ...991 32072H AVR32 10 2012 AT32UC3A3 Figure 37 3 VFBGA 100 package drawing...
