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32072H–AVR32–10/2012
AT32UC3A3
23.8
Functional Description
23.8.1
Transfer Format
The data put on the TWD line must be 8 bits long. Data is transferred MSB first; each byte must
be followed by an acknowledgement. The number of bytes per transfer is unlimited (see
).
Each transfer begins with a START condition and terminates with a STOP condition (see
).
• A high-to-low transition on the TWD line while TWCK is high defines the START condition.
• A low-to-high transition on the TWD line while TWCK is high defines a STOP condition.
Figure 23-3. START and STOP Conditions
Figure 23-4. Transfer Format
23.8.2
Operation
The TWIM has two modes of operation:
• Master transmitter mode
• Master receiver mode
The master is the device which starts and stops a transfer and generates the TWCK clock.
These modes are described in the following chapters.
TWD
TWCK
Start
Stop
TWD
TWCK
Start
Address
R/W
Ack
Data
Ack
Data
Ack
Stop
Summary of Contents for AT32UC3A3128
Page 61: ...61 32072H AVR32 10 2012 AT32UC3A3 PLLEN PLL Enable 0 PLL is disabled 1 PLL is enabled...
Page 592: ...592 32072H AVR32 10 2012 AT32UC3A3 Manchester Configuration Register on page 614...
Page 989: ...989 32072H AVR32 10 2012 AT32UC3A3 37 2 Package Drawings Figure 37 1 TFBGA 144 package drawing...
Page 991: ...991 32072H AVR32 10 2012 AT32UC3A3 Figure 37 3 VFBGA 100 package drawing...
