221
32072H–AVR32–10/2012
AT32UC3A3
16.5
Application Example
16.5.1
Hardware Interface
shows an example of SDRAM device connection using a 16-bit data
bus width. It is important to note that this example is given for a direct connection of the devices
to the SDRAMC, without External Bus Interface or I/O Controller multiplexing.
Figure 16-2. SDRAM Controller Connections to SDRAM Devices: 16-bit Data Bus Width
16.5.2
Software Interface
The SDRAM address space is organized into banks, rows, and columns. The SDRAMC allows
mapping different memory types according to the values set in the SDRAMC Configuration Reg-
ister (CR).
The SDRAMC’s function is to make the SDRAM device access protocol transparent to the user.
illustrate the SDRAM device memory map-
ping seen by the user in correlation with the device structure. Various configurations are
illustrated.
DQM[1:0]
Data Mask Enable Signals
Output
High
SDRAMC_A[12:0]
Address Bus
Output
D[15:0]
Data Bus
Input/Output
Table 16-1.
I/O Lines Description
Name
Description
Type
Active Level
2Mx8
SDRAM
D0-D7
CS
DQM
CLK
CKE
WE
RAS
CAS
A0-A9 A11
BA0
A10
BA1
SDRAMC_A10
BA0
BA1
2Mx8
SDRAM
D0-D7
CS
DQM
CLK
CKE
WE
RAS
CAS
A0-A9 A11
BA0
A10
BA1
SDRAMC_A10
BA0
BA1
SDCS
BA1
BA0
SDRAMC_A[0-12]
SDRAM
Controller
DQM[0-1]
SDWE
SDCKE
SDCK
CAS
RAS
D0-D31
DQM0
D0-D7
D8-D15
DQM1
Summary of Contents for AT32UC3A3128
Page 61: ...61 32072H AVR32 10 2012 AT32UC3A3 PLLEN PLL Enable 0 PLL is disabled 1 PLL is enabled...
Page 592: ...592 32072H AVR32 10 2012 AT32UC3A3 Manchester Configuration Register on page 614...
Page 989: ...989 32072H AVR32 10 2012 AT32UC3A3 37 2 Package Drawings Figure 37 1 TFBGA 144 package drawing...
Page 991: ...991 32072H AVR32 10 2012 AT32UC3A3 Figure 37 3 VFBGA 100 package drawing...
