796
32072H–AVR32–10/2012
AT32UC3A3
29.6.7
ADC Timings
Each ADC has its own minimal startup time that is defined through the Start Up Time field in the
Mode Register (MR.STARTUP). This startup time is given in the Electrical Characteristics
chapter.
In the same way, a minimal sample and hold time is necessary for the ADC to guarantee the
best converted final value between two channels selection. This time has to be defined through
the Sample and Hold Time field in the Mode Register (MR.SHTIM). This time depends on the
input impedance of the analog input, but also on the output impedance of the driver providing the
signal to the analog input, as there is no input buffer amplifier.
29.6.8
Conversion Performances
For performance and electrical characteristics of the ADC, see the Electrical Characteristics
chapter.
Summary of Contents for AT32UC3A3128
Page 61: ...61 32072H AVR32 10 2012 AT32UC3A3 PLLEN PLL Enable 0 PLL is disabled 1 PLL is enabled...
Page 592: ...592 32072H AVR32 10 2012 AT32UC3A3 Manchester Configuration Register on page 614...
Page 989: ...989 32072H AVR32 10 2012 AT32UC3A3 37 2 Package Drawings Figure 37 1 TFBGA 144 package drawing...
Page 991: ...991 32072H AVR32 10 2012 AT32UC3A3 Figure 37 3 VFBGA 100 package drawing...
