10
32072H–AVR32–10/2012
AT32UC3A3
C7
14
A4
PA30
30
VDDIO
x1
MCI - DATA[1]
USART3 - CLK
DMACA - DMAACK[0]
MSI - DATA[1]
B3
29
C2
PA31
31
VDDIO
x1
MCI - DATA[2]
USART2 - RXD
DMACA - DMARQ[0]
MSI - DATA[2]
A2
30
B1
PB00
32
VDDIO
x1
MCI - DATA[3]
USART2 - TXD
ADC - TRIGGER
MSI - DATA[3]
C4
27
B2
PB01
33
VDDIO
x1
MCI - DATA[4]
ABDAC - DATA[1]
EIC - SCAN[0]
MSI - INS
B4
25
B3
PB02
34
VDDIO
x1
MCI - DATA[5]
ABDAC - DATAN[1]
EIC - SCAN[1]
A5
24
C4
PB03
35
VDDIO
x1
MCI - DATA[6]
USART2 - CLK
EIC - SCAN[2]
B6
22
A3
PB04
36
VDDIO
x1
MCI - DATA[7]
USART3 - RXD
EIC - SCAN[3]
H12
121
F7
PB05
37
VDDIO
x3
USB - ID
TC0 - A0
EIC - SCAN[4]
D12
134
D7
PB06
38
VDDIO
x1
USB - VBOF
TC0 - B0
EIC - SCAN[5]
D11
135
D6
PB07
39
VDDIO
x3
SPI1 - SPCK
SSC - TX_CLOCK
EIC - SCAN[6]
C8
11
C6
PB08
40
VDDIO
x2
SPI1 - MISO
SSC - TX_DATA
EIC - SCAN[7]
E7
17
C5
PB09
41
VDDIO
x2
SPI1 - NPCS[0]
SSC - RX_DATA
EBI - NCS[4]
D7
16
D5
PB10
42
VDDIO
x2
SPI1 - MOSI
SSC - RX_FRAME_SYNC
EBI - NCS[5]
B2
31
C1
PB11
43
VDDIO
x1
USART1 - RXD
SSC - TX_FRAME_SYNC
PM - GCLK[1]
K5
98
K5
PC00
45
VDDIO
x1
H6
99
K6
PC01
46
VDDIO
x1
A7
18
A5
PC02
47
VDDIO
x1
B7
19
A6
PC03
48
VDDIO
x1
A8
13
B7
PC04
49
VDDIO
x1
A9
12
A7
PC05
50
VDDIO
x1
G1
55
G4
PX00
51
VDDIO
x2
EBI - DATA[10]
USART0 - RXD
USART1 - RI
H1
59
G2
PX01
52
VDDIO
x2
EBI - DATA[9]
USART0 - TXD
USART1 - DTR
J2
62
G3
PX02
53
VDDIO
x2
EBI - DATA[8]
USART0 - CTS
PM - GCLK[0]
K1
63
J1
PX03
54
VDDIO
x2
EBI - DATA[7]
USART0 - RTS
J1
60
H1
PX04
55
VDDIO
x2
EBI - DATA[6]
USART1 - RXD
G2
58
G1
PX05
56
VDDIO
x2
EBI - DATA[5]
USART1 - TXD
F3
53
F3
PX06
57
VDDIO
x2
EBI - DATA[4]
USART1 - CTS
F2
54
F4
PX07
58
VDDIO
x2
EBI - DATA[3]
USART1 - RTS
D1
50
E3
PX08
59
VDDIO
x2
EBI - DATA[2]
USART3 - RXD
C1
49
E4
PX09
60
VDDIO
x2
EBI - DATA[1]
USART3 - TXD
B1
37
D2
PX10
61
VDDIO
x2
EBI - DATA[0]
USART2 - RXD
L1
67
K7
PX11
62
VDDIO
x2
EBI - NWE1
USART2 - TXD
D6
34
D1
PX12
63
VDDIO
x2
EBI - NWE0
USART2 - CTS
MCI - CLK
C6
33
D3
PX13
64
VDDIO
x2
EBI - NRD
USART2 - RTS
MCI - CLK
M4
68
K5
PX14
65
VDDIO
x2
EBI - NCS[1]
TC0 - A0
E6
40
K4
PX15
66
VDDIO
x2
EBI - ADDR[19]
USART3 - RTS
TC0 - B0
C5
32
D4
PX16
67
VDDIO
x2
EBI - ADDR[18]
USART3 - CTS
TC0 - A1
K6
83
J10
PX17
68
VDDIO
x2
EBI - ADDR[17]
DMACA - DMARQ[1]
TC0 - B1
Table 3-1.
GPIO Controller Function Multiplexing
BGA
144
QFP
144
BGA
100
PIN
G
P
I
O
Supply
PIN
Type
(2)
GPIO function
A
B
C
D
Summary of Contents for AT32UC3A3128
Page 61: ...61 32072H AVR32 10 2012 AT32UC3A3 PLLEN PLL Enable 0 PLL is disabled 1 PLL is enabled...
Page 592: ...592 32072H AVR32 10 2012 AT32UC3A3 Manchester Configuration Register on page 614...
Page 989: ...989 32072H AVR32 10 2012 AT32UC3A3 37 2 Package Drawings Figure 37 1 TFBGA 144 package drawing...
Page 991: ...991 32072H AVR32 10 2012 AT32UC3A3 Figure 37 3 VFBGA 100 package drawing...