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32072H–AVR32–10/2012
AT32UC3A3
Figure 25-45. Preamble Patterns, Default Polarity Assumed
The Start Frame Delimiter Selector bit (MR.ONEBIT) configures the Manchester start bit pattern
following the preamble. If MR.ONEBIT is one, a Manchester encoded zero is transmitted to indi-
cate that a new character is about to be sent. If MR.ONEBIT is zero, a synchronization pattern is
sent for the duration of three bit periods to inaugurate the new character. The sync pattern wave-
form by itself is an invalid Manchester encoding, since the transition only occurs at the middle of
the second bit period.
The Manchester Synchronization Mode bit (MR.MODSYNC) selects sync pattern, and this also
defines if the character is data (MODSYNC=0) with a zero to one transition, or a command
(MODSYNC=1) with a one to zero transition. When direct memory access is used, the sync pat-
tern can be updated on-the-fly with a modified character located in memory. To enable this
mode the Variable Synchronization of Command/Data Sync Start Frame Delimiter bit
(MR.VAR_SYNC) must be written to one. In this case, MODSYNC is bypassed and
THR.TXSYNH selects the sync type to be included.
illustrates supported patterns.
Manchester
encoded
data
Txd
SFD
DATA
8 bit width "ALL_ONE" Preamble
Manchester
encoded
data
Txd
SFD
DATA
8 bit width "ALL_ZERO" Preamble
Manchester
encoded
data
Txd
SFD
DATA
8 bit width "ZERO_ONE" Preamble
Manchester
encoded
data
Txd
SFD
DATA
8 bit width "ONE_ZERO" Preamble
Summary of Contents for AT32UC3A3128
Page 61: ...61 32072H AVR32 10 2012 AT32UC3A3 PLLEN PLL Enable 0 PLL is disabled 1 PLL is enabled...
Page 592: ...592 32072H AVR32 10 2012 AT32UC3A3 Manchester Configuration Register on page 614...
Page 989: ...989 32072H AVR32 10 2012 AT32UC3A3 37 2 Package Drawings Figure 37 1 TFBGA 144 package drawing...
Page 991: ...991 32072H AVR32 10 2012 AT32UC3A3 Figure 37 3 VFBGA 100 package drawing...
