446
32072H–AVR32–10/2012
AT32UC3A3
22.5
Application Block Diagram
Figure 22-2. Application Block Diagram
22.6
I/O Lines Description
22.7
Product Dependencies
In order to use this module, other parts of the system must be configured correctly, as described
below.
22.7.1
I/O Lines
TWDand TWCK are bidirectional lines, connected to a positive supply voltage via a current
source or pull-up resistor (see
). When the bus is free, both lines are
high. The output stages of devices connected to the bus must have an open-drain or open-col-
lector to perform the wired-AND function.
TWALM is used to implement the optional SMBus SMBALERT signal.
TWALM, TWD, and TWCK pins may be multiplexed with I/O Controller lines. To enable the
TWIS, the user must perform the following steps:
• Program the I/O Controller to:
– Dedicate TWD, TWCK, and optionally TWALM as peripheral lines.
– Define TWD, TWCK, and optionally TWALM as open-drain.
Host with
TWI
Interface
TWD
TWCK
Atmel TWI
serial EEPROM
I²C RTC
I²C LCD
controller
Slave 1
Slave 2
Slave 3
VDD
I²C temp.
sensor
Slave 4
Rp: Pull up value as given by the I²C Standard
Rp
Rp
Table 22-4.
I/O Lines Description
Pin Name
Pin Description
Type
TWD
Two-wire Serial Data
Input/Output
TWCK
Two-wire Serial Clock
Input/Output
TWALM
SMBus SMBALERT
Input/Output
Summary of Contents for AT32UC3A3128
Page 61: ...61 32072H AVR32 10 2012 AT32UC3A3 PLLEN PLL Enable 0 PLL is disabled 1 PLL is enabled...
Page 592: ...592 32072H AVR32 10 2012 AT32UC3A3 Manchester Configuration Register on page 614...
Page 989: ...989 32072H AVR32 10 2012 AT32UC3A3 37 2 Package Drawings Figure 37 1 TFBGA 144 package drawing...
Page 991: ...991 32072H AVR32 10 2012 AT32UC3A3 Figure 37 3 VFBGA 100 package drawing...
