853
32072H–AVR32–10/2012
AT32UC3A3
31.7.8
Completion Signal Time-out Register
Name: CSTOR
Access Type: Read-write
Offset: 0x01C
Reset Value:
0x00000000
These two fields determines the maximum number of CLK_MCI cycles that the MCI waits between two data block transfers. Its
value is calculated by (CSTOCYC x Multiplier).
These two fields also determine the maximum number of CLK_MCI cycles that the MCI waits between the end of the data
transfer and the assertion of the completion signal. The data transfer comprises data phase and the optional busy phase. If a
non-DATA ATA command is issued, the MCI starts waiting immediately after the end of the response until the completion signal.
If the data time-out defined by CSTOCYC and CSTOMUL has been exceeded, the Completion Signal Time-out Error bit in the
SR register (SR.CSTOE) is set.
• CSTOMUL: Completion Signal Time-out Multiplier
Multiplier is defined by CSTOMUL as shown in the following table:
• CSTOCYC: Completion Signal Time-out Cycle Number
31
30
29
28
27
26
25
24
-
-
-
-
-
-
-
-
23
22
21
20
19
18
17
16
-
-
-
-
-
-
-
-
15
14
13
12
11
10
9
8
-
-
-
-
-
-
-
-
7
6
5
4
3
2
1
0
-
CSTOMUL
CSTOCYC
CSTOMUL
Multiplier
0
1
1
16
2
128
3
256
4
1024
5
4096
6
65536
7
1048576
Summary of Contents for AT32UC3A3128
Page 61: ...61 32072H AVR32 10 2012 AT32UC3A3 PLLEN PLL Enable 0 PLL is disabled 1 PLL is enabled...
Page 592: ...592 32072H AVR32 10 2012 AT32UC3A3 Manchester Configuration Register on page 614...
Page 989: ...989 32072H AVR32 10 2012 AT32UC3A3 37 2 Package Drawings Figure 37 1 TFBGA 144 package drawing...
Page 991: ...991 32072H AVR32 10 2012 AT32UC3A3 Figure 37 3 VFBGA 100 package drawing...
