910
32072H–AVR32–10/2012
AT32UC3A3
33.5.10
Initialization Vector n Register
Name: IVnR
Access Type: Write-only
Offset:
0x60 + (n-1)*0x04
Reset Value:
0x00000000
• IVn[31:0]: Initialization Vector n
The four 32-bit Initialization Vector registers set the 128-bit Initialization Vector data block that is used by some modes of
operation as an additional initial input:
IV1 corresponds to the first word of the Initialization Vector, IV4 to the last one.
This field is always read as zero to prevent the Initialization Vector from being read by another application.
31
30
29
28
27
26
25
24
IVn[31:24]
23
22
21
20
19
18
17
16
IVn[23:16]
15
14
13
12
11
10
9
8
IVn[15:8]
7
6
5
4
3
2
1
0
IVn[7:0]
MODE(OPMODE.
Description
CBC,OFB, CFB
initialization vector
CTR
counter value
ECB
not used, must not be written
Summary of Contents for AT32UC3A3128
Page 61: ...61 32072H AVR32 10 2012 AT32UC3A3 PLLEN PLL Enable 0 PLL is disabled 1 PLL is enabled...
Page 592: ...592 32072H AVR32 10 2012 AT32UC3A3 Manchester Configuration Register on page 614...
Page 989: ...989 32072H AVR32 10 2012 AT32UC3A3 37 2 Package Drawings Figure 37 1 TFBGA 144 package drawing...
Page 991: ...991 32072H AVR32 10 2012 AT32UC3A3 Figure 37 3 VFBGA 100 package drawing...
