Atmel AT32UC3A3128, Manual

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546
32072H–AVR32–10/2012
AT32UC3A3
25. Universal Synchronous Asynchronous Receiver Transmitter (USART)
Rev: 4.2.0.6
25.1 Features
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Configurable baud rate generator
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5- to 9-bit full-duplex, synchronous and asynchronous, serial communication
– 1, 1.5, or 2 stop bits in asynchronous mode, and 1 or 2 in synchronous mode
– Parity generation and error detection
– Framing- and overrun error detection
– MSB- or LSB-first
– Optional break generation and detection
– Receiver frequency oversampling by 8 or 16 times
– Optional RTS-CTS hardware handshaking
– Optional DTR-DSR-DCD-RI modem signal management
– Receiver Time-out and transmitter Timeguard
– Optional Multidrop mode with address generation and detection
•
RS485 with line driver control
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ISO7816, T=0 and T=1 protocols for Interfacing with smart cards
– , NACK handling, and customizable error counter
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IrDA modulation and demodulation
– Communication at up to 115.2Kbit/s
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SPI Mode
– Master or slave
– Configurable serial clock phase and polarity
– CLK SPI serial clock frequency up to a quarter of the CLK_USART internal clock frequency
•
LIN Mode
– Compliant with LIN 1.3 and LIN 2.0 specifications
– Master or slave
– Processing of Frames with up to 256 data bytes
– Configurable response data length, optionally defined automatically by the Identifier
– Self synchronization in slave node configuration
– Automatic processing and verification of the “Break Field” and “Sync Field”
– The “Break Field” is detected even if it is partially superimposed with a data byte
– Optional, automatic identifier parity management
– Optional, automatic checksum management
– Supports both “Classic” and “Enhanced” checksum types
– Full LIN error checking and reporting
– Frame Slot Mode: the master allocates slots to scheduled frames automatically.
– Wakeup signal generation
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Test Modes
– Automatic echo, remote- and local loopback
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Supports two Peripheral DMA Controller channels
– Buffer transfers without processor intervention
25.2 Overview
The Universal Synchronous Asynchronous Receiver Transmitter (USART) provides a full
duplex, universal, synchronous/asynchronous serial link. Data frame format is widely configu-
rable, including basic length, parity, and stop bit settings, maximizing standards support. The
receiver implements parity-, framing-, and overrun error detection, and can handle un-fixed