47
32072H–AVR32–10/2012
AT32UC3A3
7.5.5.2
Selecting synchronous clock division ratio
The main clock feeds an 8-bit prescaler, which can be used to generate the synchronous clocks.
By default, the synchronous clocks run on the undivided main clock. The user can select a pres-
caler division for the CPU clock by writing CKSEL.CPUDIV to 1 and CPUSEL to the prescaling
value, resulting in a CPU clock frequency:
Similarly, the clock for the PBA, and PBB can be divided by writing their respective fields. To
ensure correct operation, frequencies must be selected so that f
CPU
≥
f
PBA,B
. Also, frequencies
must never exceed the specified maximum frequency for each clock domain.
CKSEL can be written without halting or disabling peripheral modules. Writing CKSEL allows a
new clock setting to be written to all synchronous clocks at the same time. It is possible to keep
one or more clocks unchanged by writing the same value a before to the xxxDIV and xxxSEL
fields. This way, it is possible to e.g. scale CPU and HSB speed according to the required perfor-
mance, while keeping the PBA and PBB frequency constant.
For modules connected to the HSB bus, the PB clock frequency must be set to the same fre-
quency than the CPU clock.
7.5.5.3
Clock ready flag
There is a slight delay from CKSEL is written and the new clock setting becomes effective. Dur-
ing this interval, the Clock Ready (CKRDY) flag in ISR will read as 0. If IER.CKRDY is written to
one, the Power Manager interrupt can be triggered when the new clock setting is effective.
CKSEL must not be re-written while CKRDY is zero, or the system may become unstable or
hang.
7.5.6
Peripheral Clock Masking
By default, the clock for all modules are enabled, regardless of which modules are actually being
used. It is possible to disable the clock for a module in the CPU, HSB, PBA, or PBB clock
domain by writing the corresponding bit in the Clock Mask register (CPU/HSB/PBA/PBB) to 0.
When a module is not clocked, it will cease operation, and its registers cannot be read or written.
The module can be re-enabled later by writing the corresponding mask bit to 1.
A module may be connected to several clock domains, in which case it will have several mask
bits.
contains the list of implemented maskable clocks.
7.5.6.1
Cautionary note
The OCD clock must never be switched off if the user wishes to debug the device with a JTAG
debugger.
Note that clocks should only be switched off if it is certain that the module will not be used.
Switching off the clock for the internal RAM will cause a problem if the stack is mapped there.
Switching off the clock to the Power Manager (PM), which contains the mask registers, or the
corresponding PBx bridge, will make it impossible to write the mask registers again. In this case,
they can only be re-enabled by a system reset.
f
CPU
f
main
2
CPUSEL
1
+
(
)
⁄
=
Summary of Contents for AT32UC3A3128
Page 61: ...61 32072H AVR32 10 2012 AT32UC3A3 PLLEN PLL Enable 0 PLL is disabled 1 PLL is enabled...
Page 592: ...592 32072H AVR32 10 2012 AT32UC3A3 Manchester Configuration Register on page 614...
Page 989: ...989 32072H AVR32 10 2012 AT32UC3A3 37 2 Package Drawings Figure 37 1 TFBGA 144 package drawing...
Page 991: ...991 32072H AVR32 10 2012 AT32UC3A3 Figure 37 3 VFBGA 100 package drawing...
