Atmel AT32UC3A3128, Manual

Page: 646 / 1021

646
32072H–AVR32–10/2012
AT32UC3A3
Figure 27-17. Example of an IN Endpoint with 2 Data Banks
•Detailed description
The data is written, following the next flow:
• When the bank is empty, TXINI and FIFOCON are set, what triggers an EPnINT interrupt if
TXINE is one.
• The user acknowledges the interrupt by clearing TXINI.
• The user writes the data into the current bank by using the USB Pipe/Endpoint nFIFO Data
virtual segment (see ”USB Pipe/Endpoint n FIFO Data Register (USBFIFOnDATA)” on page
747 ), until all the data frame is written or the bank is full (in which case RWALL is cleared and
the Byte Count (BYCT) field in UESTAn reaches the endpoint size).
• The user allows the controller to send the bank and switches to the next bank (if any) by
clearing FIFOCON.
If the endpoint uses several banks, the current one can be written while the previous one is
being read by the host. Then, when the user clears FIFOCON, the following bank may already
be free and TXINI is set immediately.
An “Abort” stage can be produced when a zero-length OUT packet is received during an IN
stage of a control or isochronous IN transaction. The Kill IN Bank (KILLBK) bit in UECONn is
used to kill the last written bank. The best way to manage this abort is to apply the algorithm rep-
resented on
Figure 27-18 on page 647 . See ”Endpoint n Control Register” on page 706 to have
more details about the KILLBK bit.
IN
DATA
(bank 0)
ACK
TXINI
FIFOCON
write data to CPU
BANK 0
SW
SW SW
SW
IN
DATA
(bank 1)
ACK
write data to CPU
BANK 1
SW
HW
write data to CPU
BANK0