Atmel AT32UC3A3128, Manual

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178
32072H–AVR32–10/2012
AT32UC3A3
15. Static Memory Controller (SMC)
Rev. 1.0.6.5
15.1 Features
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6 chip selects available
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16-Mbytes address space per chip select
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8- or 16-bit data bus
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Word, halfword, byte transfers
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Byte write or byte select lines
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Programmable setup, pulse and hold time for read signals per chip select
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Programmable setup, pulse and hold time for write signals per chip select
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Programmable data float time per chip select
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Compliant with LCD module
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External wait request
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Automatic switch to slow clock mode
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Asynchronous read in page mode supported: page size ranges from 4 to 32 bytes
15.2 Overview
The Static Memory Controller (SMC) generates the signals that control the access to the exter-
nal memory devices or peripheral devices. It has 6 chip selects and a 24-bit address bus. The
16-bit data bus can be configured to interface with 8-16-bit external devices. Separate read and
write control signals allow for direct memory and peripheral interfacing. Read and write signal
waveforms are fully parametrizable.
The SMC can manage wait requests from external devices to extend the current access. The
SMC is provided with an automatic slow clock mode. In slow clock mode, it switches from user-
programmed waveforms to slow-rate specific waveforms on read and write signals. The SMC
supports asynchronous burst read in page mode access for page size up to 32 bytes.