200
32072H–AVR32–10/2012
AT32UC3A3
• read access followed by a write access on the same chip select.
with no TDF optimization.
Figure 15-22. TDF Optimization Disabled (MODE.TDFMODE = 0). TDF Wait States between Two Read Accesses on Dif-
ferent Chip Selects.
Figure 15-23. TDF Optimization Disabled (MODE.TDFMODE= 0). TDF Wait States between a Read and a Write Access
on Different Chip Selects.
CLK_SMC
A[AD_MSB:2]
NBS0, NBS1,
A0, A1
Read1 controlling
signal(NRD)
Read2 controlling
signal(NRD)
D[15:0]
Read1 hold = 1
Read1 cycle
TDFCYCLES = 6
Chip Select Wait State
5 TDF WAIT STATES
TDFCYCLES = 6
Read2 setup = 1
Read 2 cycle
TDFMODE=0
(optimization disabled)
CLK_SMC
A[AD_MSB:2]
NBS0, NBS1,
A0, A1
Read1 controlling
signal(NRD)
Write2 controlling
signal(NWE)
D[15:0]
Read1 cycle
TDFCYCLES = 4
Chip Select
Wait State
Read1 hold = 1
TDFCYCLES = 4
Read to Write
Wait State
2 TDF WAIT STATES
Write2 setup = 1
Write 2 cycle
TDFMODE=0
(optimization disabled)
Summary of Contents for AT32UC3A3128
Page 61: ...61 32072H AVR32 10 2012 AT32UC3A3 PLLEN PLL Enable 0 PLL is disabled 1 PLL is enabled...
Page 592: ...592 32072H AVR32 10 2012 AT32UC3A3 Manchester Configuration Register on page 614...
Page 989: ...989 32072H AVR32 10 2012 AT32UC3A3 37 2 Package Drawings Figure 37 1 TFBGA 144 package drawing...
Page 991: ...991 32072H AVR32 10 2012 AT32UC3A3 Figure 37 3 VFBGA 100 package drawing...
