Atmel AT32UC3A3128, Manual

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521
32072H–AVR32–10/2012
AT32UC3A3
Figure 24-15. Receive Frame Format in Continuous Mode
Note: STTDLY is written to zero.
24.7.8 Loop Mode
The receiver can be programmed to receive transmissions from the transmitter. This is done by
writing a one to the Loop Mode bit in RFMR register (RFMR.LOOP). In this case, RX_DATA is
connected to TX_DATA, RX_FRAME_SYNC is connected to TX_FRAME_SYNC and
RX_CLOCK is connected to TX_CLOCK.
24.7.9 Interrupt
Most bits in the SR register have a corresponding bit in interrupt management registers.
The SSC can be programmed to generate an interrupt when it detects an event. The interrupt is
controlled by writing to the Interrupt Enable Register (IER) and Interrupt Disable Register (IDR).
These registers enable and disable, respectively, the corresponding interrupt by setting and
clearing the corresponding bit in the Interrupt Mask Register (IMR), which controls the genera-
tion of interrupts by asserting the SSC interrupt line connected to the interrupt controller.
Figure 24-16. Interrupt Block Diagram
Data Data
To RHR To RHR
DATLEN DATLEN
RX_DATA
Start = Enable Receiver
IM R
IE R ID R
C le a r
S e t
In te rru p t
C o n tro l
S S C In te rru p t
T X R D Y
T X E M P T Y
T X S Y N C
T ra n s m itte r
R e c e iv e r
R X R D Y
O V R U N
R X S Y N C