689
32072H–AVR32–10/2012
AT32UC3A3
27.8.2.2
Device Global Interrupt Register
Register Name:
UDINT
Access Type:
Read-Only
Offset:
0x0004
Reset Value:
0x00000000
• DMAnINT: DMA Channel n Interrupt
This bit is set when an interrupt is triggered by the DMA channel n. This triggers a USB interrupt if DMAnINTE is one.
This bit is cleared when the UDDMAnSTATUS interrupt source is cleared.
• EPnINT: Endpoint n Interrupt
This bit is set when an interrupt is triggered by the endpoint n (UESTAn, UECONn). This triggers a USB interrupt if EPnINTE is
one.
This bit is cleared when the interrupt source is serviced.
• UPRSM: Upstream Resume Interrupt
This bit is set when the USBB sends a resume signal called “Upstream Resume”. This triggers a USB interrupt if UPRSME is
one.
This bit is cleared when the UDINTCLR.UPRSMC bit is written to one to acknowledge the interrupt (USB clock inputs must be
enabled before).
• EORSM: End of Resume Interrupt
This bit is set when the USBB detects a valid “End of Resume” signal initiated by the host. This triggers a USB interrupt if
EORSME is one.
This bit is cleared when the UDINTCLR.EORSMC bit is written to one to acknowledge the interrupt.
• WAKEUP: Wake-Up Interrupt
This bit is set when the USBB is reactivated by a filtered non-idle signal from the lines (not by an upstream resume). This
triggers an interrupt if WAKEUPE is one.
This bit is cleared when the UDINTCLR.WAKEUPC bit is written to one to acknowledge the interrupt (USB clock inputs must be
enabled before).
This bit is cleared when the Suspend (SUSP) interrupt bit is set.
This interrupt is generated even if the clock is frozen by the FRZCLK bit.
• EORST: End of Reset Interrupt
This bit is set when a USB “End of Reset” has been detected. This triggers a USB interrupt if EORSTE is one.
This bit is cleared when the UDINTCLR.EORSTC bit is written to one to acknowledge the interrupt.
31
30
29
28
27
26
25
24
DMA7INT
DMA6INT
DMA5INT
DMA4INT
DMA3INT
DMA2INT
DMA1INT
-
23
22
21
20
19
18
17
16
-
-
-
-
EP7INT
EP6INT
EP5INT
EP4INT
15
14
13
12
11
10
9
8
EP3INT
EP2INT
EP1INT
EP0INT
-
-
-
-
7
6
5
4
3
2
1
0
-
UPRSM
EORSM
WAKEUP
EORST
SOF
MSOF
SUSP
Summary of Contents for AT32UC3A3128
Page 61: ...61 32072H AVR32 10 2012 AT32UC3A3 PLLEN PLL Enable 0 PLL is disabled 1 PLL is enabled...
Page 592: ...592 32072H AVR32 10 2012 AT32UC3A3 Manchester Configuration Register on page 614...
Page 989: ...989 32072H AVR32 10 2012 AT32UC3A3 37 2 Package Drawings Figure 37 1 TFBGA 144 package drawing...
Page 991: ...991 32072H AVR32 10 2012 AT32UC3A3 Figure 37 3 VFBGA 100 package drawing...