409
32072H–AVR32–10/2012
AT32UC3A3
In master mode, if the received data is not read fast enough compared to the transfer rhythm
imposed by the write accesses in the TDR, some overrun errors may occur, even if the FIFO is
enabled. To insure a perfect data integrity of received data (especially at high data rate), the
mode Wait Data Read Before Transfer can be enabled in the MR register (MR.WDRBT). When
this mode is activated, no transfer starts while received data remains unread in the RDR. When
data is written to the TDR and if unread received data is stored in the RDR, the transfer is
paused until the RDR is read. In this mode no overrun error can occur. Please note that if this
mode is enabled, it is useless to activate the FIFO in reception.
shows a block diagram of the SPI when operating in master mode.
shows a flow chart describing how transfers are handled.
21.7.3.1
Master mode block diagram
Figure 21-5. Master Mode Block Diagram
Baud Rate Generator
RXFIFOEN
4 – Character FIFO
Shift Register
TDRE
RXFIFOEN
4 – Character FIFO
PS
PCSDEC
Current
Peripheral
MODF
MODFDIS
MSTR
SCBR
CSR0..3
CSR0..3
CPOL
NCPHA
BITS
RDR
RD
RDRF
OVRES
TD
TDR
RDR
CSAAT
CSNAAT
CSR0..3
PCS
MR
PCS
TDR
SPCK
CLK_SPI
MISO
MOSI
MSB
LSB
NPCS1
NPCS2
NPCS3
NPCS0
SPI
Clock
0
1
0
1
0
1
NPCS0
Summary of Contents for AT32UC3A3128
Page 61: ...61 32072H AVR32 10 2012 AT32UC3A3 PLLEN PLL Enable 0 PLL is disabled 1 PLL is enabled...
Page 592: ...592 32072H AVR32 10 2012 AT32UC3A3 Manchester Configuration Register on page 614...
Page 989: ...989 32072H AVR32 10 2012 AT32UC3A3 37 2 Package Drawings Figure 37 1 TFBGA 144 package drawing...
Page 991: ...991 32072H AVR32 10 2012 AT32UC3A3 Figure 37 3 VFBGA 100 package drawing...