Atmel AT32UC3A3128, Manual

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32072H–AVR32–10/2012
AT32UC3A3
6. Boot Sequence
This chapter summarizes the boot sequence of the AT32UC3A3/A4. The behavior after power-
up is controlled by the Power Manager. For specific details, refer to
Section 7. ”Power Manager
(PM)” on page 41 .
6.1 Starting of Clocks
After power-up, the device will be held in a reset state by the Power-On Reset circuitry, until the
power has stabilized throughout the device. Once the power has stabilized, the device will use
the internal RC Oscillator as clock source.
On system start-up, the PLLs are disabled. All clocks to all modules are running. No clocks have
a divided frequency, all parts of the system receives a clock with the same frequency as the
internal RC Oscillator.
6.2 Fetching of Initial Instructions
After reset has been released, the AVR32 UC CPU starts fetching instructions from the reset
address, which is 0x8000_0000. This address points to the first address in the internal Flash.
The internal Flash uses VDDIO voltage during read and write operations. BOD33 monitors this
voltage and maintains the device under reset until VDDIO reaches the minimum voltage, pre-
venting any spurious execution from flash.
The code read from the internal Flash is free to configure the system to use for example the
PLLs, to divide the frequency of the clock routed to some of the peripherals, and to gate the
clocks to unused peripherals.
When powering up the device, there may be a delay before the voltage has stabilized, depend-
ing on the rise time of the supply used. The CPU can start executing code as soon as the supply
is above the POR threshold, and before the supply is stable. Before switching to a high-speed
clock source, the user should use the BOD to make sure the VDDCORE is above the minimum-
level (1.62V).