644
32072H–AVR32–10/2012
AT32UC3A3
Figure 27-14. Control Write
•Control read
shows a control read transaction. The USBB has to manage the
simultaneous write requests from the CPU and the USB host.
Figure 27-15. Control Read
A NAK handshake is always generated on the first status stage command.
When the controller detects the status stage, all the data written by the CPU are lost and clear-
ing TXINI has no effect.
The user checks if the transmission or the reception is complete.
The OUT retry is always ACKed. This reception sets RXOUTI and TXINI. Handle this with the
following software algorithm:
set TXINI
wait for RXOUTI OR TXINI
if RXOUTI, then clear bit and return
if TXINI, then continue
Once the OUT status stage has been received, the USBB waits for a SETUP request. The
SETUP request has priority over any other request and has to be ACKed. This means that any
other bit should be cleared and the FIFO reset when a SETUP is received.
The user has to take care of the fact that the byte counter is reset when a zero-length OUT
packet is received.
SETUP
RXSTPI
RXOUTI
TXINI
USB Bus
HW
SW
OUT
HW
SW
OUT
HW
SW
IN
IN
NAK
SW
DATA
SETUP
STATUS
SETUP
RXSTPI
RXOUTI
TXINI
USB Bus
HW
SW
IN
HW
SW
IN
OUT
OUT
NAK
SW
SW
HW
Wr Enable
HOST
Wr Enable
CPU
DATA
SETUP
STATUS
Summary of Contents for AT32UC3A3128
Page 61: ...61 32072H AVR32 10 2012 AT32UC3A3 PLLEN PLL Enable 0 PLL is disabled 1 PLL is enabled...
Page 592: ...592 32072H AVR32 10 2012 AT32UC3A3 Manchester Configuration Register on page 614...
Page 989: ...989 32072H AVR32 10 2012 AT32UC3A3 37 2 Package Drawings Figure 37 1 TFBGA 144 package drawing...
Page 991: ...991 32072H AVR32 10 2012 AT32UC3A3 Figure 37 3 VFBGA 100 package drawing...
