532
32072H–AVR32–10/2012
AT32UC3A3
• CKG: Transmit Clock Gating Selection
• CKI: Transmit Clock Inversion
CKI affects only the Transmit Clock and not the output clock signal.
1: The data outputs (Data and Frame Sync signals) are shifted out on transmit clock rising edge. The Frame sync signal input is
sampled on transmit clock falling edge.
0: The data outputs (Data and Frame Sync signals) are shifted out on transmit clock falling edge. The Frame sync signal input is
sampled on transmit clock rising edge.
• CKO: Transmit Clock Output Mode Selection
• CKS: Transmit Clock Selection
CKG
Transmit Clock Gating
0
None, continuous clock
1
Transmit Clock enabled only if TX_FRAME_SYNC is low
2
Transmit Clock enabled only if TX_FRAME_SYNC is high
3
Reserved
CKO
Transmit Clock Output Mode
TX_CLOCK pin
0
None
Input-only
1
Continuous transmit clock
Output
2
Transmit clock only during data transfers
Output
Others
Reserved
CKS
Selected Transmit Clock
0
Divided Clock
1
RX_CLOCK clock signal
2
TX_CLOCK Pin
3
Reserved
Summary of Contents for AT32UC3A3128
Page 61: ...61 32072H AVR32 10 2012 AT32UC3A3 PLLEN PLL Enable 0 PLL is disabled 1 PLL is enabled...
Page 592: ...592 32072H AVR32 10 2012 AT32UC3A3 Manchester Configuration Register on page 614...
Page 989: ...989 32072H AVR32 10 2012 AT32UC3A3 37 2 Package Drawings Figure 37 1 TFBGA 144 package drawing...
Page 991: ...991 32072H AVR32 10 2012 AT32UC3A3 Figure 37 3 VFBGA 100 package drawing...
