571
32072H–AVR32–10/2012
AT32UC3A3
• The theoretical slave node clock frequency; nominal clock frequency (F
Nom
)
• The baud rate
• The oversampling mode (OVER=0 => 16x, or OVER=1 => 8x)
The following formula is used to calculate synchronization deviation, where F
SLAVE
is the real
slave node clock frequency, and F
TOL_UNSYNC
is the difference between F
Nom
and F
SLAVE
. Accord-
ing to the LIN specification, F
TOL_UNSYNCH
may not exceed ±15%, and the bit rates between two
nodes must be within ±2% of each other, resulting in a maximal BaudRate_deviation of ±1%.
Minimum nominal clock frequency with a fractional part:
Examples:
• Baud rate = 20 kbit/s, OVER=0 (Oversampling 16x) => F
Nom
(min) = 2.64 MHz
• Baud rate = 20 kbit/s, OVER=1 (Oversampling 8x) => F
Nom
(min) = 1.47 MHz
• Baud rate = 1 kbit/s, OVER=0 (Oversampling 16x) => F
Nom
(min) = 132 kHz
• Baud rate = 1 kbit/s, OVER=1 (Oversampling 8x) => F
Nom
(min) = 74 kHz
If the fractional part is not used, the synchronization accuracy is much lower. The 16 most signif-
icant bits, added with the first least significant bit, becomes the new clock divider (CD). The
equation of the baud rate deviation is the same as above, but the constants are:
Minimum nominal clock frequency without a fractional part:
Examples:
• Baud rate = 20 kbit/s, OVER=0 (Oversampling 16x) => F
Nom
(min) = 19.12 MHz
• Baud rate = 20 kbit/s, OVER=1 (Oversampling 8x) => F
Nom
(min) = 9.71 MHz
• Baud rate = 1 kbit/s, OVER=0 (Oversampling 16x) => F
Nom
(min) = 956 kHz
• Baud rate = 1 kbit/s, OVER=1 (Oversampling 8x) => F
Nom
(min) = 485 kHz
25.6.10.8
Identifier Parity
An identifier field consists of two sub-fields; the identifier and its parity. Bits 0 to 5 are assigned
to the identifier, while bits 6 and 7 are assigned to parity. Automatic parity management is
BaudRate_deviation
100
α
[
8
2
OVER
–
(
) β
+
]
BaudRate
×
×
×
8
F
SLAVE
×
---------------------------------------------------------------------------------------------------
×
⎝
⎠
⎛
⎞
%
=
BaudRate_deviation
100
α
[
8
2
OVER
–
(
) β
+
]
BaudRate
×
×
×
8
F
TOL_UNSYNC
100
------------------------------------
⎝
⎠
⎛
⎞
xF
Nom
×
---------------------------------------------------------------------------------------------------
×
⎝
⎠
⎜
⎟
⎜
⎟
⎜
⎟
⎛
⎞
%
=
0,5
–
α
+0,5 -1
β
+1
< <
≤ ≤
F
Nom
min
(
)
100
0,5
8
2
OVER
–
(
)
×
×
1
+
[
]
BaudRate
×
8
15
–
100
----------
1
+
⎝
⎠
⎛
⎞
×
1%
×
-------------------------------------------------------------------------------------------------------
×
⎝
⎠
⎜
⎟
⎜
⎟
⎜
⎟
⎛
⎞
Hz
=
4
–
α
+4 -1
β
+1
< <
≤ ≤
F
Nom
min
(
)
100
4
8
2
OVER
–
(
)
×
×
1
+
[
]
Baudrate
×
8
15
–
100
----------
1
+
⎝
⎠
⎛
⎞
×
1%
×
-----------------------------------------------------------------------------------------------
×
⎝
⎠
⎜
⎟
⎜
⎟
⎜
⎟
⎛
⎞
Hz
=
Summary of Contents for AT32UC3A3128
Page 61: ...61 32072H AVR32 10 2012 AT32UC3A3 PLLEN PLL Enable 0 PLL is disabled 1 PLL is enabled...
Page 592: ...592 32072H AVR32 10 2012 AT32UC3A3 Manchester Configuration Register on page 614...
Page 989: ...989 32072H AVR32 10 2012 AT32UC3A3 37 2 Package Drawings Figure 37 1 TFBGA 144 package drawing...
Page 991: ...991 32072H AVR32 10 2012 AT32UC3A3 Figure 37 3 VFBGA 100 package drawing...