751
32072H–AVR32–10/2012
AT32UC3A3
28.5.2
Power Management
If the CPU enters a sleep mode that disables clocks used by the TC, the TC will stop functioning
and resume operation after the system wakes up from sleep mode.
28.5.3
Clocks
The clock for the TC bus interface (CLK_TC) is generated by the Power Manager. This clock is
enabled at reset, and can be disabled in the Power Manager. It is recommended to disable the
TC before disabling the clock, to avoid freezing the TC in an undefined state.
28.5.4
Interrupts
The TC interrupt request line is connected to the interrupt controller. Using the TC interrupt
requires the interrupt controller to be programmed first.
28.5.5
Debug Operation
The Timer Counter clocks are frozen during debug operation, unless the OCD system keeps
peripherals running in debug operation.
28.6
Functional Description
28.6.1
TC Description
The three channels of the Timer Counter are independent and identical in operation. The regis-
ters for channel programming are listed in
.
28.6.1.1
Channel I/O Signals
As described in
, each Channel has the following I/O signals.
28.6.1.2
16-bit counter
Each channel is organized around a 16-bit counter. The value of the counter is incremented at
each positive edge of the selected clock. When the counter has reached the value 0xFFFF and
passes to 0x0000, an overflow occurs and the Counter Overflow Status bit in the Channel n Sta-
tus Register (SRn.COVFS) is set.
The current value of the counter is accessible in real time by reading the Channel n Counter
Value Register (CVn). The counter can be reset by a trigger. In this case, the counter value
passes to 0x0000 on the next valid edge of the selected clock.
Table 28-2.
Channel I/O Signals Description
Block/Channel Signal Name
Description
Channel Signal
XC0, XC1, XC2
External Clock Inputs
TIOA
Capture mode: Timer Counter Input
Waveform mode: Timer Counter Output
TIOB
Capture mode: Timer Counter Input
Waveform mode: Timer Counter Input/Output
INT
Interrupt Signal Output
SYNC
Synchronization Input Signal
Summary of Contents for AT32UC3A3128
Page 61: ...61 32072H AVR32 10 2012 AT32UC3A3 PLLEN PLL Enable 0 PLL is disabled 1 PLL is enabled...
Page 592: ...592 32072H AVR32 10 2012 AT32UC3A3 Manchester Configuration Register on page 614...
Page 989: ...989 32072H AVR32 10 2012 AT32UC3A3 37 2 Package Drawings Figure 37 1 TFBGA 144 package drawing...
Page 991: ...991 32072H AVR32 10 2012 AT32UC3A3 Figure 37 3 VFBGA 100 package drawing...
