500
32072H–AVR32–10/2012
AT32UC3A3
• IDLE: Master Interface is Idle
This bit is one when no command is in progress, and no command waiting to be issued.
Otherwise, this bit is cleared.
• CCOMP: Command Complete
This bit is one when the current command has completed successfully.
This bit is zero if the command failed due to conditions such as a NAK receved from slave.
This bit is cleared by writing 1 to the corresponding bit in the Status Clear Register (SCR).
• CRDY: Ready for More Commands
This bit is one when CMDR and/or NCMDR is ready to receive one or more commands.
This bit is cleared when this is no longer true.
• TXRDY: THR Data Ready
This bit is one when THR is ready for one or more data bytes.
This bit is cleared when this is no longer true (i.e. THR is full or transmission has stopped).
• RXRDY: RHR Data Ready
This bit is one when RX data are ready to be read from RHR.
This bit is cleared when this is no longer true.
Summary of Contents for AT32UC3A3128
Page 61: ...61 32072H AVR32 10 2012 AT32UC3A3 PLLEN PLL Enable 0 PLL is disabled 1 PLL is enabled...
Page 592: ...592 32072H AVR32 10 2012 AT32UC3A3 Manchester Configuration Register on page 614...
Page 989: ...989 32072H AVR32 10 2012 AT32UC3A3 37 2 Package Drawings Figure 37 1 TFBGA 144 package drawing...
Page 991: ...991 32072H AVR32 10 2012 AT32UC3A3 Figure 37 3 VFBGA 100 package drawing...
