830
32072H–AVR32–10/2012
AT32UC3A3
Consequent to MMC Specification 3.1, two types of multiple block read (or write) transactions
are defined (the host can use either one at any time):
• Open-ended/Infinite Multiple block read (or write):
The number of blocks for the read (or write) multiple block operation is not defined. The card
will continuously transfer (or program) data blocks until a stop transmission command is
received.
• Multiple block read (or write) with pre-defined block count (since version 3.1 and higher):
The card will transfer (or program) the requested number of data blocks and terminate the trans-
action. The stop command is not required at the end of this type of multiple block read (or write),
unless terminated with an error. In order to start a multiple block read (or write) with pre-defined
block count, the host must correctly set the BLKR register. Otherwise the card will start an open-
ended multiple block read. The
MMC/SDIO Block Count - SDIO Byte Count field in the BLKR register
(BLKR.BCNT)
defines the number of blocks to transfer (from 1 to 65535 blocks). Writing zero to
this field corresponds to an infinite block transfer.
31.6.4
Read/Write Operation
The following flowchart shows how to read a single block with or without use of DMA Controller
facilities. In this example (see
), a polling method is used to wait for the
end of read. Similarly, the user can configure the IER register to trigger an interrupt at the end of
read.
Summary of Contents for AT32UC3A3128
Page 61: ...61 32072H AVR32 10 2012 AT32UC3A3 PLLEN PLL Enable 0 PLL is disabled 1 PLL is enabled...
Page 592: ...592 32072H AVR32 10 2012 AT32UC3A3 Manchester Configuration Register on page 614...
Page 989: ...989 32072H AVR32 10 2012 AT32UC3A3 37 2 Package Drawings Figure 37 1 TFBGA 144 package drawing...
Page 991: ...991 32072H AVR32 10 2012 AT32UC3A3 Figure 37 3 VFBGA 100 package drawing...
