880
32072H–AVR32–10/2012
AT32UC3A3
32.7.3
Status register
Name :
SR
Access Type :
Read Only
Offset :
0x08
Reset Value :
0x00001020
•
ISTA : Insertion Status. It reflects the Memory Stick card presence. This is the inverse of INS pin.
0 : No card.
1 : Card is inserted.
•
RDY : Ready. RDY goes to 1 when the protocol ends. This bit bit is cleared to 0 by write to the command register.
0 : Command receive disabled due to communication with the Memory Stick.
1 : Command received or protocol ended.
•
EMP : FIFO Empty. This bit is set to 1 by writing system register bit FCLR=1.
0 : FIFO contains data.
1 : FIFO is empty.
•
FUL : FIFO Full. This bit is cleared to 0 by writing system register bit FCLR=1.
0 : FIFO has empty space.
1 : FIFO is full.
•
CED : MS Command End.
In parallel mode, this bit reflects the CED bit in the status register of a Memory Stick (INT). Indicates the end of a
command executed with SET_CMD TPC. In serial mode, this bit is always 0. It is cleared to 0 by writing to the command
register (CMD).
•
ERR : Memory Stick Error.
In parallel mode, this bit reflects the ERR bit in the status register of a Memory Stick (INT). It indicates the occurence
of an error. In serial mode, this bit is always 0. It is cleared to 0 by writing to the command register (CMD).
31
30
29
28
27
26
25
24
-
-
-
-
-
-
-
-
23
22
21
20
19
18
17
16
-
-
-
-
-
-
-
ISTA
15
14
13
12
11
10
9
8
-
-
-
RDY
-
-
-
-
7
6
5
4
3
2
1
0
-
-
EMP
FUL
CED
ERR
BRQ
CNK
Summary of Contents for AT32UC3A3128
Page 61: ...61 32072H AVR32 10 2012 AT32UC3A3 PLLEN PLL Enable 0 PLL is disabled 1 PLL is enabled...
Page 592: ...592 32072H AVR32 10 2012 AT32UC3A3 Manchester Configuration Register on page 614...
Page 989: ...989 32072H AVR32 10 2012 AT32UC3A3 37 2 Package Drawings Figure 37 1 TFBGA 144 package drawing...
Page 991: ...991 32072H AVR32 10 2012 AT32UC3A3 Figure 37 3 VFBGA 100 package drawing...