179
32072H–AVR32–10/2012
AT32UC3A3
15.3
Block Diagram
Figure 15-1. SMC Block Diagram (AD_MSB=23)
15.4
I/O Lines Description
15.5
Product Dependencies
In order to use this module, other parts of the system must be configured correctly, as described
below.
SMC
Chip Select
HMatrix
Power
Manager
CLK_SMC
SMC
I/O
Controller
NCS[5:0]
NRD
NWE0
ADDR[0]
NWE1
ADDR[1]
ADDR[AD_MSB:2]
DATA[15:0]
NWAIT
User Interface
Peripheral Bus
NCS[5:0]
NRD
NWR0/NWE
A0/NBS0
NWR1/NBS1
A1/NWR2/NBS2
A[AD_MSB:2]
D[15:0]
NWAIT
EBI
Mux Logic
Table 15-1.
I/O Lines Description
Pin Name
Pin Description
Type
Active Level
NCS[5:0]
Chip Select Lines
Output
Low
NRD
Read Signal
Output
Low
NWR0/NWE
Write 0/Write Enable Signal
Output
Low
A0/NBS0
Address Bit 0/Byte 0 Select Signal
Output
Low
NWR1/NBS1
Write 1/Byte 1 Select Signal
Output
Low
A[23:2]
Address Bus
Output
D[15:0] Data
Bus
Input/Output
NWAIT
External Wait Signal
Input
Low
Summary of Contents for AT32UC3A3128
Page 61: ...61 32072H AVR32 10 2012 AT32UC3A3 PLLEN PLL Enable 0 PLL is disabled 1 PLL is enabled...
Page 592: ...592 32072H AVR32 10 2012 AT32UC3A3 Manchester Configuration Register on page 614...
Page 989: ...989 32072H AVR32 10 2012 AT32UC3A3 37 2 Package Drawings Figure 37 1 TFBGA 144 package drawing...
Page 991: ...991 32072H AVR32 10 2012 AT32UC3A3 Figure 37 3 VFBGA 100 package drawing...
