937
32072H–AVR32–10/2012
AT32UC3A3
35.4.5.1
Power Management
When an instruction that accesses the SAB is loaded in the instruction register, before entering
a sleep mode, the system clocks are not switched off to allow debugging in sleep modes. This
can lead to a program behaving differently when debugging.
35.4.5.2
Clocks
The JTAG Interface uses the external TCK pin as clock source. This clock must be provided by
the JTAG master.
Instructions that use the SAB bus requires the internal main clock to be running.
35.4.6
JTAG Interface
The JTAG Interface is accessed through the dedicated JTAG pins shown in
. The TMS control line navigates the TAP controller, as shown in
The TAP controller manages the serial access to the JTAG Instruction and Data registers. Data
is scanned into the selected instruction or data register on TDI, and out of the register on TDO,
in the Shift-IR and Shift-DR states, respectively. The LSB is shifted in and out first. TDO is high-
Z in other states than Shift-IR and Shift-DR.
The device implements a 5-bit Instruction Register (IR). A number of public JTAG instructions
defined by the JTAG standard are supported, as described in
, as well as a num-
ber of 32-bit AVR-specific private JTAG instructions described in
. Each
instruction selects a specific data register for the Shift-DR path, as described for each
instruction.
Summary of Contents for AT32UC3A3128
Page 61: ...61 32072H AVR32 10 2012 AT32UC3A3 PLLEN PLL Enable 0 PLL is disabled 1 PLL is enabled...
Page 592: ...592 32072H AVR32 10 2012 AT32UC3A3 Manchester Configuration Register on page 614...
Page 989: ...989 32072H AVR32 10 2012 AT32UC3A3 37 2 Package Drawings Figure 37 1 TFBGA 144 package drawing...
Page 991: ...991 32072H AVR32 10 2012 AT32UC3A3 Figure 37 3 VFBGA 100 package drawing...
