674
32072H–AVR32–10/2012
AT32UC3A3
This bit can be written even if FRZCLK is one.
• FRZCLK: Freeze USB Clock
1: The clock input are disabled (the resume detection is still active).This reduces power consumption. Unless explicitly stated, all
registers then become read-only.
0: The clock inputs are enabled.
This bit can be written even if USBE is zero. Disabling the USBB (by writing a zero to the USBE bit) does not reset this bit, but
this freezes the clock inputs whatever its value.
• VBUSPO: VBus Polarity
1: The USB_VBOF output signal is inverted (active low).
0: The USB_VBOF output signal is in its default mode (active high).
To be generic. May be useful to control an external VBus power module.
This bit can be written even if USBE is zero or FRZCLK is one. Disabling the USBB (by writing a zero to the USBE bit) does not
reset this bit.
• OTGPADE: OTG Pad Enable
1: The OTG pad is enabled.
0: The OTG pad is disabled.
This bit can be written even if USBE is zero or FRZCLK is one. Disabling the USBB (by writing a zero to the USBE bit) does not
reset this bit.
• VBUSHWC: VBus Hardware Control
1: The hardware control over the USB_VBOF output pin is disabled.
0: The hardware control over the USB_VBOF output pin is enabled. The USBB resets the USB_VBOF output pin when a VBUS
problem occurs.
• STOE: Suspend Time-Out Interrupt Enable
1: The Suspend Time-Out Interrupt (STOI) is enabled.
0: The Suspend Time-Out Interrupt (STOI) is disabled.
• ROLEEXE: Role Exchange Interrupt Enable
1: The Role Exchange Interrupt (ROLEEXI) is enabled.
0: The Role Exchange Interrupt (ROLEEXI) is disabled.
• BCERRE: B-Connection Error Interrupt Enable
1: The B-Connection Error Interrupt (BCERRI) is enabled.
0: The B-Connection Error Interrupt (BCERRI) is disabled.
• VBERRE: VBus Error Interrupt Enable
1: The VBus Error Interrupt (VBERRI) is enabled.
0: The VBus Error Interrupt (VBERRI) is disabled.
• VBUSTE: VBus Transition Interrupt Enable
1: The VBus Transition Interrupt (VBUSTI) is enabled.
0: The VBus Transition Interrupt (VBUSTI) is disabled.
• IDTE: ID Transition Interrupt Enable
1: The ID Transition interrupt (IDTI) is enabled.
0: The ID Transition interrupt (IDTI) is disabled.
Summary of Contents for AT32UC3A3128
Page 61: ...61 32072H AVR32 10 2012 AT32UC3A3 PLLEN PLL Enable 0 PLL is disabled 1 PLL is enabled...
Page 592: ...592 32072H AVR32 10 2012 AT32UC3A3 Manchester Configuration Register on page 614...
Page 989: ...989 32072H AVR32 10 2012 AT32UC3A3 37 2 Package Drawings Figure 37 1 TFBGA 144 package drawing...
Page 991: ...991 32072H AVR32 10 2012 AT32UC3A3 Figure 37 3 VFBGA 100 package drawing...
