15
32072H–AVR32–10/2012
AT32UC3A3
RESET_N
Reset Pin
Input
Low
DMA Controller - DMACA (optional)
DMAACK[1:0]
DMA Acknowledge
Output
DMARQ[1:0]
DMA Requests
Input
External Interrupt Controller - EIC
EXTINT[7:0]
External Interrupt Pins
Input
SCAN[7:0]
Keypad Scan Pins
Output
NMI
Non-Maskable Interrupt Pin
Input
Low
General Purpose Input/Output pin - GPIOA, GPIOB, GPIOC, GPIOX
PA[31:0]
Parallel I/O Controller GPIO port A
I/O
PB[11:0]
Parallel I/O Controller GPIO port B
I/O
PC[5:0]
Parallel I/O Controller GPIO port C
I/O
PX[59:0]
Parallel I/O Controller GPIO port X
I/O
External Bus Interface - EBI
ADDR[23:0]
Address Bus
Output
CAS
Column Signal
Output
Low
CFCE1
Compact Flash 1 Chip Enable
Output
Low
CFCE2
Compact Flash 2 Chip Enable
Output
Low
CFRNW
Compact Flash Read Not Write
Output
DATA[15:0]
Data Bus
I/O
NANDOE
NAND Flash Output Enable
Output
Low
NANDWE
NAND Flash Write Enable
Output
Low
NCS[5:0]
Chip Select
Output
Low
NRD
Read Signal
Output
Low
NWAIT
External Wait Signal
Input
Low
NWE0
Write Enable 0
Output
Low
NWE1
Write Enable 1
Output
Low
RAS
Row Signal
Output
Low
Table 3-6.
Signal Description List
Signal Name
Function
Type
Active
Level
Comments
Summary of Contents for AT32UC3A3128
Page 61: ...61 32072H AVR32 10 2012 AT32UC3A3 PLLEN PLL Enable 0 PLL is disabled 1 PLL is enabled...
Page 592: ...592 32072H AVR32 10 2012 AT32UC3A3 Manchester Configuration Register on page 614...
Page 989: ...989 32072H AVR32 10 2012 AT32UC3A3 37 2 Package Drawings Figure 37 1 TFBGA 144 package drawing...
Page 991: ...991 32072H AVR32 10 2012 AT32UC3A3 Figure 37 3 VFBGA 100 package drawing...