766
32072H–AVR32–10/2012
AT32UC3A3
28.7
User Interface
Table 28-3.
TC Register Memory Map
Offset
Register
Register Name
Access
Reset
0x00
Channel 0 Control Register
CCR0
Write-only
0x00000000
0x04
Channel 0 Mode Register
CMR0
Read/Write
0x00000000
0x10
Channel 0 Counter Value
CV0
Read-only
0x00000000
0x14
Channel 0 Register A
RA0
Read/Write
(1)
0x00000000
0x18
Channel 0 Register B
RB0
Read/Write
(1)
0x00000000
0x1C
Channel 0 Register C
RC0
Read/Write
0x00000000
0x20
Channel 0 Status Register
SR0
Read-only
0x00000000
0x24
Interrupt Enable Register
IER0
Write-only
0x00000000
0x28
Channel 0 Interrupt Disable Register
IDR0
Write-only
0x00000000
0x2C
Channel 0 Interrupt Mask Register
IMR0
Read-only
0x00000000
0x40
Channel 1 Control Register
CCR1
Write-only
0x00000000
0x44
Channel 1 Mode Register
CMR1
Read/Write
0x00000000
0x50
Channel 1 Counter Value
CV1
Read-only
0x00000000
0x54
Channel 1 Register A
RA1
Read/Write
(1)
0x00000000
0x58
Channel 1 Register B
RB1
Read/Write
(1)
0x00000000
0x5C
Channel 1 Register C
RC1
Read/Write
0x00000000
0x60
Channel 1 Status Register
SR1
Read-only
0x00000000
0x64
Channel 1 Interrupt Enable Register
IER1
Write-only
0x00000000
0x68
Channel 1 Interrupt Disable Register
IDR1
Write-only
0x00000000
0x6C
Channel 1 Interrupt Mask Register
IMR1
Read-only
0x00000000
0x80
Channel 2 Control Register
CCR2
Write-only
0x00000000
0x84
Channel 2 Mode Register
CMR2
Read/Write
0x00000000
0x90
Channel 2 Counter Value
CV2
Read-only
0x00000000
0x94
Channel 2 Register A
RA2
Read/Write
(1)
0x00000000
0x98
Channel 2 Register B
RB2
Read/Write
(1)
0x00000000
0x9C
Channel 2 Register C
RC2
Read/Write
0x00000000
0xA0
Channel 2 Status Register
SR2
Read-only
0x00000000
0xA4
Channel 2 Interrupt Enable Register
IER2
Write-only
0x00000000
0xA8
Channel 2 Interrupt Disable Register
IDR2
Write-only
0x00000000
0xAC
Channel 2 Interrupt Mask Register
IMR2
Read-only
0x00000000
0xC0
Block Control Register
BCR
Write-only
0x00000000
0xC4
Block Mode Register
BMR
Read/Write
0x00000000
0xF8
Features Register
FEATURES
Read-only
-
(2)
0xFC
Version Register
VERSION
Read-only
-
(2)
Summary of Contents for AT32UC3A3128
Page 61: ...61 32072H AVR32 10 2012 AT32UC3A3 PLLEN PLL Enable 0 PLL is disabled 1 PLL is enabled...
Page 592: ...592 32072H AVR32 10 2012 AT32UC3A3 Manchester Configuration Register on page 614...
Page 989: ...989 32072H AVR32 10 2012 AT32UC3A3 37 2 Package Drawings Figure 37 1 TFBGA 144 package drawing...
Page 991: ...991 32072H AVR32 10 2012 AT32UC3A3 Figure 37 3 VFBGA 100 package drawing...