875
32072H–AVR32–10/2012
AT32UC3A3
Figure 32-6. Interface mode switching sequence
32.6.4
Data transfer requests
After the communication protocol with the Memory Stick starts, a data transfer request is
asserted to the CPU (DRQ bit in ISR) and to DMACA (internal signals), until data transfer of the
amount indicated by DSZ (CMD) is finished. However, the data transfer request stops when the
internal FIFO becomes either empty or full.
Like CPU, DMACA uses Peripheral Bus to access FIFO so it is not recommended to access MSI
registers during transfer. It is also not recommended to enable DRQ interrupt because ISR.DRQ
bit is automatically cleared when FIFO is accessed.
DMACA channel should be configured first and the data size should be a multiple of 64 bits
(FIFO size is 4 * 64bits).
32.6.5
Interrupts
The interrupt sources of MSI are :
•
PEND : protocol command ended without error.
•
DRQ : data request, FIFO is full or empty.
•
MSINT : interrupt received from Memory Stick.
•
CRC : protocol ended with CRC error.
•
TOE : protocol ended with time out error.
•
CD : card detected (inserted or removed).
Each interrupt source can be enabled in Interrupt Enable register (IER) and disabled in Interrupt
Disable register (IDR). The enable status is read in Interrupt Mask register (IMR). The status of
WRITE_REG TPC
system parameter
(PAM bit)
SET_R/W_REG_ADRS TPC
Set Parallel Interface Mode
(
MSSYS.SRAC=0, MSSYS.REI=0)
Serial Interface Mode
(
MSSYS.SRAC=1, MSSYS.REI=1)
Error
OK
Change SCLK
(
MSSYS.CLKDIV[7:0]=X)
Summary of Contents for AT32UC3A3128
Page 61: ...61 32072H AVR32 10 2012 AT32UC3A3 PLLEN PLL Enable 0 PLL is disabled 1 PLL is enabled...
Page 592: ...592 32072H AVR32 10 2012 AT32UC3A3 Manchester Configuration Register on page 614...
Page 989: ...989 32072H AVR32 10 2012 AT32UC3A3 37 2 Package Drawings Figure 37 1 TFBGA 144 package drawing...
Page 991: ...991 32072H AVR32 10 2012 AT32UC3A3 Figure 37 3 VFBGA 100 package drawing...
