280
32072H–AVR32–10/2012
AT32UC3A3
17.7
Module Configuration
The specific configuration for the ECCHRS instance is listed in the following tables.The module
bus clocks listed here are connected to the system bus clocks according to the table in the
Power Manager section.
Table 17-2.
Module clock name
Module name
Clock name
ECCHRS
CLK_ECCHRS
Table 17-3.
Register Reset Values
Register
Reset Value
VERSION
0x00000100
Summary of Contents for AT32UC3A3128
Page 61: ...61 32072H AVR32 10 2012 AT32UC3A3 PLLEN PLL Enable 0 PLL is disabled 1 PLL is enabled...
Page 592: ...592 32072H AVR32 10 2012 AT32UC3A3 Manchester Configuration Register on page 614...
Page 989: ...989 32072H AVR32 10 2012 AT32UC3A3 37 2 Package Drawings Figure 37 1 TFBGA 144 package drawing...
Page 991: ...991 32072H AVR32 10 2012 AT32UC3A3 Figure 37 3 VFBGA 100 package drawing...
