206
32072H–AVR32–10/2012
AT32UC3A3
15.6.7.4
NWAIT latency and read/write timings
There may be a latency between the assertion of the read/write controlling signal and the asser-
tion of the NWAIT signal by the device. The programmed pulse length of the read/write
controlling signal must be at least equal to this latency plus the two cycles of resynchronization
plus one cycle. Otherwise, the SMC may enter the hold state of the access without detecting the
NWAIT signal assertion. This is true in frozen mode as well as in ready mode. This is illustrated
on
When the MODE.EXNWMODE field is enabled (ready or frozen), the user must program a pulse
length of the read and write controlling signal of at least:
Figure 15-29. NWAIT Latency
minimal pulse length
NWAIT latency
2 synchronization cycles
1 cycle
+
+
=
Wait STATE
0
1
2
3
4
CLK_SMC
A[AD_MSB:2]
NBS0, NBS1,
A0, A1
NRD
NWAIT
nternally synchronized
NWAIT signal
Minimal pulse length
0
0
NWAIT latency 2 cycle resynchronization
Read cycle
EXNWMODE = 2 or 3
READMODE = 1 (NRD controlled)
NRDPULSE = 5
Summary of Contents for AT32UC3A3128
Page 61: ...61 32072H AVR32 10 2012 AT32UC3A3 PLLEN PLL Enable 0 PLL is disabled 1 PLL is enabled...
Page 592: ...592 32072H AVR32 10 2012 AT32UC3A3 Manchester Configuration Register on page 614...
Page 989: ...989 32072H AVR32 10 2012 AT32UC3A3 37 2 Package Drawings Figure 37 1 TFBGA 144 package drawing...
Page 991: ...991 32072H AVR32 10 2012 AT32UC3A3 Figure 37 3 VFBGA 100 package drawing...
