Atmel AT32UC3A3128 Manual Download Page 701

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701

32072H–AVR32–10/2012

AT32UC3A3

• CURRBK: Current Bank

This bit is set for non-control endpoints, to indicate the current bank:

This field may be updated one clock cycle after the RWALL bit changes, so the user should not poll this field as an interrupt bit.

• NBUSYBK: Number of Busy Banks

This field is set to indicate the number of busy banks:

For IN endpoints, it indicates the number of banks filled by the user and ready for IN transfer. When all banks are free, this

triggers an EPnINT interrupt if NBUSYBKE is one.

For OUT endpoints, it indicates the number of banks filled by OUT transactions from the host. When all banks are busy, this

triggers an EPnINT interrupt if NBUSYBKE is one.

When the FIFOCON bit is cleared (by writing a one to the FIFOCONC bit) to validate a new bank, this field is updated two or

three clock cycles later to calculate the address of the next bank.

An EPnINT interrupt is triggered if:

- for IN endpoint, NBUSYBKE is one and all the banks are free.

- for OUT endpoint, NBUSYBKE is one and all the banks are busy.

• ERRORTRANS: High-bandwidth isochronous OUT endpoint transaction error Interrupt

This bit is set when a transaction error occurs during the current micro-frame (the data toggle sequencing does not respect the

usb 2.0 standard). This triggers an EPnINT interrupt if ERRORTRANSE is one.

This bit is set as long as the current bank (CURRBK) belongs to the bad n-transactions (n=1,2 or 3) transferred during the

micro-frame. Shall be cleared by software by clearing (at least once) the FIFOCON bit to switch to the bank that belongs to the

next n-transactions (next micro-frame).

Look at the UFEATURES register to know if the high-bandwidth isochronous feature is supported by the device.

• DTSEQ: Data Toggle Sequence

This field is set to indicate the PID of the current bank:

For IN transfers, it indicates the data toggle sequence that will be used for the next packet to be sent. This is not relative to the

current bank.

CURRBK

Current Bank

Bank0

Bank1

Bank2 if supported

(see

Table 27-1 on page 624

Reserved

NBUSYBK

Number of Busy Banks

0 (all banks free)

3 if supported

(see

Table 27-1 on page 624

DTSEQ

Data Toggle Sequence

Data0

Data1

Data2 (for high-bandwidth isochronous endpoint)

MData (for high-bandwidth isochronous endpoint)

Summary of Contents for AT32UC3A3128

Page 1: ...Programmable Priority System Functions Power and Clock Manager Including Internal RC Clock and One 32KHz Oscillator Two Multipurpose Oscillators and Two Phase Lock Loop PLL Watchdog Timer Real Time Cl...

Page 2: ...Interface TWI 400kbit s I2C compatible 16 bit Stereo Audio Bitstream Sample Rate Up to 50 KHz QTouch Library Support Capacitive Touch Buttons Sliders and Wheels QTouch and QMatrix Acquisition On Chip...

Page 3: ...imer Counter TC channels Each chan nel can be independently programmed to perform frequency measurement event counting interval measurement pulse generation delay timing and pulse width modulation 16...

Page 4: ...z RCSYS OSC0 PLL0 USART3 SERIAL PERIPHERAL INTERFACE 0 1 TWO WIRE INTERFACE 0 1 DMA DMA DMA RXD TXD CLK MISO MOSI NPCS 3 1 TWCK TWD USART1 DMA RXD TXD CLK RTS CTS DSR DTR DCD RI USART0 USART2 DMA RXD...

Page 5: ...terrupts 8 TWI 2 USART 4 Peripheral DMA Channels 8 Generic DMA Channels 4 SPI 2 MCI slots 2 MMC SD slots 1 MMC SD slot 1 SD slot High Speed USB 1 AES S option 1 SSC 1 Audio Bitstream DAC 1 Timer Count...

Page 6: ...5 GNDIO PX37 PX36 PB01 PX16 PX47 PX19 PB08 PA30 PX13 PA02 PB10 PX12 PA10 PA08 GNDCORE DPFS PB06 PB07 PA11 PA26 VDDIN PA12 VDDCORE PA07 PA25 PA06 PA16 PA13 PA05 PA04 PX53 VDDIO PB09 PX15 PX49 PX48 GNDI...

Page 7: ...4 60 PX34 61 PX02 62 PX03 63 VDDIO 64 GNDIO 65 PX44 66 PX11 67 PX14 68 PX42 69 PX45 70 PX41 71 PX22 72 TDI 108 TCK 107 RESET_N 106 TDO 105 TMS 104 VDDIO 103 GNDIO 102 PA15 101 PA14 100 PC01 99 PC00 98...

Page 8: ...00 PB11 PA31 GNDIO PX10 PX13 PB03 PB09 PX16 PX53 1 PB10 GNDIO USB_VBIAS PB08 PA09 PB06 PB07 PA10 PA11 VDDIN VDDIN PA06 PA13 1 VDDCORE PA04 PA08 GNDCORE PA03 PX09 VDDIO PA16 GNDIO PX07 GNDIO PA26 PB05...

Page 9: ...EXTINT 6 TC1 A1 C12 138 C10 PA10 10 VDDIO x2 SPI0 MOSI USB VBOF TC1 B0 D10 136 C9 PA11 11 VDDIO x2 SPI0 MISO USB ID TC1 A2 E12 132 G7 1 PA12 12 VDDIO x1 USART1 CTS SPI0 NPCS 2 TC1 A0 F11 129 E8 1 PA13...

Page 10: ...O x1 A7 18 A5 PC02 47 VDDIO x1 B7 19 A6 PC03 48 VDDIO x1 A8 13 B7 PC04 49 VDDIO x1 A9 12 A7 PC05 50 VDDIO x1 G1 55 G4 PX00 51 VDDIO x2 EBI DATA 10 USART0 RXD USART1 RI H1 59 G2 PX01 52 VDDIO x2 EBI DA...

Page 11: ...PI1 MISO PM GCLK 0 C2 38 PX35 86 VDDIO x2 EBI DATA 15 SPI1 MOSI PM GCLK 1 D3 44 PX36 87 VDDIO x2 EBI DATA 14 SPI1 SPCK PM GCLK 2 D2 45 PX37 88 VDDIO x2 EBI DATA 13 SPI1 NPCS 0 PM GCLK 3 E1 51 PX38 89...

Page 12: ...ore information about this Note 1 This ball is physically connected to 2 GPIOs Software must managed carrefully the GPIO con figuration to avoid electrical conflict J4 78 PX56 107 VDDIO x2 EBI ADDR 21...

Page 13: ...the OCD AXS register For details see the AVR32 UC Tech nical Reference Manual Table 3 4 JTAG Pinout TFBGA144 QFP144 VFBGA100 Pin name JTAG pin K12 107 K9 TCK TCK L12 108 K8 TDI TDI J11 105 J8 TDO TDO...

Page 14: ...gital Supply Power Output 1 65 to 1 95 V GNDANA Analog Ground Ground GNDIO I O Ground Ground GNDCORE Digital Ground Ground GNDPLL PLL Ground Ground Clocks Oscillators and PLL s XIN0 XIN1 XIN32 Crystal...

Page 15: ...l I O Controller GPIO port C I O PX 59 0 Parallel I O Controller GPIO port X I O External Bus Interface EBI ADDR 23 0 Address Bus Output CAS Column Signal Output Low CFCE1 Compact Flash 1 Chip Enable...

Page 16: ...dia Card Data I O Serial Peripheral Interface SPI0 SPI1 MISO Master In Slave Out I O MOSI Master Out Slave In I O NPCS 3 0 SPI Peripheral Chip Select I O Low SPCK Clock Output Synchronous Serial Contr...

Page 17: ...2 USART3 CLK Clock I O CTS Clear To Send Input DCD Data Carrier Detect Only USART1 DSR Data Set Ready Only USART1 DTR Data Terminal Ready Only USART1 RI Ring Indicator Only USART1 RTS Request To Send...

Page 18: ...ground through a 6810 ohms 1 resistor in parallel with a 10pf capacitor If USB hi speed feature is not required leave this pin unconnected to save power USB_VBUS USB VBUS signal Output VBOF USB VBUS...

Page 19: ...d to the product 3 4 3 TWI Pins When these pins are used for TWI the pins are open drain outputs with slew rate limitation and inputs with inputs with spike filtering When used as GPIO pins or used fo...

Page 20: ...rts from 3 3V to 1 8V with a load of up to 100 mA The regulator takes its input voltage from VDDIN and supplies the output voltage on VDDCORE and powers the core memories and peripherals Adequate outp...

Page 21: ...architectures enabling the AVR32 to be implemented as low mid or high performance processors AVR32 extends the AVR family into the world of 32 and 64 bit applications Through a quantitative approach a...

Page 22: ...data RAMs internal to the CPU allows fast access to the RAMs reduces latency and guarantees deterministic timing Also power consumption is reduced by not needing a full High Speed Bus access for memo...

Page 23: ...te and in this case the instruction resides in the ID and EX stages for the required num ber of clock cycles Since there is only three pipeline stages no internal data forwarding is required and no da...

Page 24: ...registers and status register are restored and execution continues at the return address stored popped from stack The stack is also used to store the status register and return address for exceptions...

Page 25: ...f no coprocessors are present retj incjosp popjc pushjc tlbr tlbs tlbw cache 4 3 7 CPU and Architecture Revision Three major revisions of the AVR32UC CPU currently exist The Architecture Revision fiel...

Page 26: ...1 PC SR R12 INT0PC FINTPC INT1PC SMPC R7 R5 R6 R4 R11 R9 R10 R8 R3 R1 R2 R0 SP_SYS LR Bit 0 Bit 31 PC SR R12 INT0PC FINTPC INT1PC SMPC R7 R5 R6 R4 R11 R9 R10 R8 R3 R1 R2 R0 SP_SYS LR Bit 0 Bit 31 PC S...

Page 27: ...privileged resources After a reset the processor will be in supervisor mode 4 4 3 2 Debug State The AVR32 can be set in a debug state which allows implementation of software monitor rou tines that can...

Page 28: ...rs refer to the AVR32UC Technical Reference Manual Table 4 3 System Registers Reg Address Name Function 0 0 SR Status Register 1 4 EVBA Exception Vector Base Address 2 8 ACBA Application Call Base Add...

Page 29: ...in AVR32UC 74 296 TLBARHI Unused in AVR32UC 75 300 PCCNT Unused in AVR32UC 76 304 PCNT0 Unused in AVR32UC 77 308 PCNT1 Unused in AVR32UC 78 312 PCCR Unused in AVR32UC 79 316 BEAR Bus Error Address Re...

Page 30: ...ytes The target address of the event handler is calculated as EVBA event_handler_offset not EVBA event_handler_offset so EVBA and exception code segments must be set up appropriately The same mechanis...

Page 31: ...exception handler has a dedicated handler address and this address uniquely identifies the exception source 3 The Mode bits are set to reflect the priority of the accepted event and the correct regis...

Page 32: ...and DTLB miss exceptions are used to signal that an access address did not map to any of the entries in the MPU TLB multiple hit exception indicates that an access address did map to multiple TLB entr...

Page 33: ...Autovectored Interrupt 0 request External input First non completed instruction 12 EVBA 0x14 Instruction Address CPU PC of offending instruction 13 EVBA 0x50 ITLB Miss MPU 14 EVBA 0x18 ITLB Protectio...

Page 34: ...34 32072H AVR32 10 2012 AT32UC3A3 4 6 Module Configuration All AT32UC3A3 parts implement the CPU and Architecture Revision 2...

Page 35: ...32KBytes accessible independently through the High Speed Bud HSB matrix 5 2 Physical Memory Map The System Bus is implemented as a bus matrix All system bus addresses are fixed and they are never rema...

Page 36: ...AT32UC3A464 Table 5 2 Peripheral Address Mapping Address Peripheral Name 0xFF100000 DMACA DMA Controller DMACA 0xFFFD0000 AES Advanced Encryption Standard AES 0xFFFE0000 USB USB 2 0 Device and Host I...

Page 37: ...RT1 0xFFFF1C00 USART2 Universal Synchronous Asynchronous Receiver Transmitter USART2 0xFFFF2000 USART3 Universal Synchronous Asynchronous Receiver Transmitter USART3 0xFFFF2400 SPI0 Serial Peripheral...

Page 38: ...TWIS0 Two wire Slave Interface TWIS0 0xFFFF5400 TWIS1 Two wire Slave Interface TWIS1 Table 5 2 Peripheral Address Mapping Table 5 3 Local Bus Mapped GPIO Registers Port Register Mode Local Bus Address...

Page 39: ...TOGGLE 0x4000025C Write only Pin Value Register PVR 0x40000260 Read only 3 Output Driver Enable Register ODER WRITE 0x40000340 Write only SET 0x40000344 Write only CLEAR 0x40000348 Write only TOGGLE...

Page 40: ...eased the AVR32 UC CPU starts fetching instructions from the reset address which is 0x8000_0000 This address points to the first address in the internal Flash The internal Flash uses VDDIO voltage dur...

Page 41: ...s clocks are used to clock the main digital logic in the device namely the CPU and the modules and peripherals connected to the HSB PBA and PBB buses The generic clocks are asynchronous clocks which c...

Page 42: ...Generic Clock Generator Reset Controller Oscillator 0 Oscillator 1 RC Oscillator Startup Counter Slow clock Sleep instruction Power On Detector Other reset sources resets Generic clocks Synchronous c...

Page 43: ...5 2 Oscillator 0 and 1 Operation The two main oscillators are designed to be used with an external crystal and two biasing capac itors as shown in Figure 7 2 on page 44 Oscillator 0 can be used for th...

Page 44: ...ed on a zero to one transition of OSC32RDY As a crystal oscillator usually requires a very long startup time up to 1 second the 32 KHz oscillator will keep running across resets except Power On Reset...

Page 45: ...division factors respectively creating the voltage controlled ocillator frequency fVCO and the PLL frequency fPLL if PLLDIV 0 fIN fOSC 2 PLLDIV fVCO PLLMUL 1 PLLDIV fOSC if PLLDIV 0 fIN fOSC fVCO 2 P...

Page 46: ...rying load in the application The clock domains can be shut down in sleep mode as described in Section 7 5 7 Additionally the clocks for each module in the four domains can be individually masked to a...

Page 47: ...omes effective Dur ing this interval the Clock Ready CKRDY flag in ISR will read as 0 If IER CKRDY is written to one the Power Manager interrupt can be triggered when the new clock setting is effectiv...

Page 48: ...r Some of these modules have a rel atively long start up time and are only switched off when very low power consumption is required The CPU and affected modules are restarted when the sleep mode is ex...

Page 49: ...ped before entering the sleep mode Also if there is a chance that any PB write operations are incomplete the CPU should perform a read operation from any register on the PB bus before executing the sl...

Page 50: ...can be disabled by writing CEN to zero or entering a sleep mode that disables the PB clocks In either case the generic clock will be switched off on the first falling edge after the disabling event t...

Page 51: ...on the PBA and PBB buses may use debug qualified PBx clocks This is described in the documentation for the relevant modules The divided PBx clocks are always debug qualified clocks Debug qualified PBx...

Page 52: ...will force a reset of the whole chip Reset source Description Power on Reset Supply voltage below the power on reset detector threshold voltage External Reset RESET_N pin asserted Brownout Reset Suppl...

Page 53: ...enabled either by software or by flash fuses The Brown Out Detector can either gen erate an interrupt or a reset when the supply voltage is below the brown out detection level In any case the BOD out...

Page 54: ...for parametric details Table 7 5 VDDIO pin monitored by BOD33 7 5 11 4 External reset The external reset detector monitors the state of the RESET_N pin By default a low level on this pin will generate...

Page 55: ...nterrupt Status Register ISR Read only 0x00000000 00050 PM Interrupt Clear Register ICR Write only 0x00000000 0x054 Power and Oscillators Status Register POSCSR Read Write 0x00000000 0x060 Generic Clo...

Page 56: ...enabled 0 Oscillator 1 is disabled OSC0EN Oscillator 0 Enable 1 Oscillator 0 is enabled 0 Oscillator 0 is disabled MCSEL Main Clock Select This field contains the clock selected as the main clock 31...

Page 57: ...PBA clock equals main clock divided by 2 PBASEL 1 CPUDIV CPUSEL CPU HSB Division and Clock Select CPUDIV 0 CPU HSB clock equals main clock CPUDIV 1 CPU HSB clock equals main clock divided by 2 CPUSEL...

Page 58: ...h mask register as well as which module clock is controlled by each bit is shown in Table 7 7 on page 58 31 30 29 28 27 26 25 24 MASK 31 24 23 22 21 20 19 18 17 16 MASK 23 16 15 14 13 12 11 10 9 8 MAS...

Page 59: ...et to one if the user wishes to debug the device with a JTAG debugger 2 This bits must be set to one 16 SYSTIMER compare count registers clk TC0 17 TC1 18 ABDAC 19 2 20 2 31 21 Table 7 7 Maskable modu...

Page 60: ...ncy Formula is detallied in Section 7 5 4 1 PLLOPT PLL Option Select the operating range for the PLL PLLOPT 0 Select the VCO frequency range PLLOPT 1 Enable the extra output divider PLLOPT 2 Disable t...

Page 61: ...61 32072H AVR32 10 2012 AT32UC3A3 PLLEN PLL Enable 0 PLL is disabled 1 PLL is enabled...

Page 62: ...r is used with gain G0 XIN from 0 4 MHz to 0 9 MHz 5 Crystal is connected to XIN XOUT Oscillator is used with gain G1 XIN from 0 9 MHz to 3 0 MHz 6 Crystal is connected to XIN XOUT Oscillator is used...

Page 63: ...ted on XIN32 XOUT32 can be used as a I O no crystal 1 Crystal is connected to XIN32 XOUT32 Oscillator is used with automatic gain control 2 to 7 Reserved OSC32EN Enable the 32 KHz oscillator 0 32 KHz...

Page 64: ...Reset Value 0x00000000 Writing a one to a bit in this register will set the corresponding bit in IMR Writing a zero to a bit in this register has no effect 31 30 29 28 27 26 25 24 23 22 21 20 19 18 1...

Page 65: ...Reset Value 0x00000000 Writing a one to a bit in this register will clear the corresponding bit in IMR Writing a zero to a bit in this register has no effect 31 30 29 28 27 26 25 24 23 22 21 20 19 18...

Page 66: ...abled 1 The corresponding interrupt is enabled A bit in this register is cleared when the corresponding bit in IDR is written to one A bit in this register is set when the corresponding bit in IER is...

Page 67: ...Y Oscillator 1 Ready This bit is set when a 0 to 1 transition on the POSCSR OSC1RDY bit is detected Oscillator 1 is stable and ready to be used as clock source This bit is cleared when the correspondi...

Page 68: ...ked and ready to be selected as clock source This bit is cleared when the corresponding bit in ICR is written to one LOCK0 PLL0 locked This bit is set when a 0 to 1 transition on the POSCSR LOCK0 bit...

Page 69: ...00 Writing a zero to a bit in this register has no effect Writing a one to a bit in this register will clear the corresponding bit in ISR and the corresponding interrupt request 31 30 29 28 27 26 25 2...

Page 70: ...cillator 1 is stable and ready to be used as clock source OSC0RDY OSC0 ready 0 Oscillator 0 not enabled or not ready 1 Oscillator 0 is stable and ready to be used as clock source MSKRDY Mask ready 0 M...

Page 71: ...ded source clock 1 The generic clock equals the source clock divided by 2 DIV 1 CEN Clock Enable 0 Clock is stopped 1 Clock is running PLLSEL PLL Select 0 Oscillator is source for the generic clock 1...

Page 72: ...fect FCD Flash Calibration Done Set to 1 when CTRL HYST and LEVEL fields have been updated by the Flash fuses after power on reset or after Flash fuses are reprogrammed The CTRL HYST and LEVEL values...

Page 73: ...e Flash fuses after power on reset or when the Flash fuses are reprogrammed The CALIB field will not be updated again by the Flash fuses until a new power on reset or the FCD field is written to zero...

Page 74: ...Calibration value for Voltage Regulator See Electrical Characteristics for voltage values FCD Flash Calibration Done Set to 1 when the CALIB field has been updated by the Flash fuses after power on re...

Page 75: ...cleared to allow subsequent overwriting of the value by Flash fuses CTRL BOD Control 0 BOD is off 1 BOD is enabled and can reset the chip 2 BOD is enabled and but cannot reset the chip Only interrupt...

Page 76: ...Can be cleared to allow subsequent overwriting of the value by Flash fuses CTRL BOD33 Control 0 BOD33 is off 1 BOD33 is enabled and can reset the chip 2 BOD33 is enabled and but cannot reset the chip...

Page 77: ...it had detected an illegal access JTAG JTAG reset The CPU was reset by setting the bit RC_CPU in the JTAG reset register WDT Watchdog Reset The CPU was reset because of a watchdog timeout EXT Externa...

Page 78: ...ss Type Read Write Offset 0x144 Reset Value USB_WAKEN Wake Up Enable Register Writing a zero to this bit will disable the USB wake up Writing a one to this bit will enable the USB wake up 31 30 29 28...

Page 79: ...purpose 32 bit registers that are reset only by power on reset Any other reset will keep the content of these registers untouched User software can use these register to save context variables in a v...

Page 80: ...bit prescaler which is clocked from the system RC oscillator or the 32KHz crystal oscillator Any tapping of the prescaler can be selected as clock source for the RTC enabling both high resolution and...

Page 81: ...ires the interrupt controller to be programmed first 8 4 4 Debug Operation The RTC prescaler is frozen during debug operation unless the OCD system keeps peripherals running in debug operation 8 5 Fun...

Page 82: ...sleep modes except DeepStop and Static modes 8 5 1 4 RTC wakeup The RTC can also wake up the CPU directly without triggering an interrupt when the ISR TOPI bit is set In this case the CPU will contin...

Page 83: ...000 0x04 Value Register VAL Read Write 0x00000000 0x08 Top Register TOP Read Write 0xFFFFFFFF 0x10 Interrupt Enable Register IER Write only 0x00000000 0x14 Interrupt Disable Register IDR Write only 0x...

Page 84: ...ccepts writes to TOP VAL and CTRL CLK32 32 KHz Oscillator Select 1 The RTC uses the 32 KHz oscillator as clock source 0 The RTC uses the RC oscillator as clock source WAKEN Wakeup Enable 1 The RTC wak...

Page 85: ...ccess Type Read Write Offset 0x04 Reset Value 0x00000000 VAL 31 0 RTC Value This value is incremented on every rising edge of the source clock 31 30 29 28 27 26 25 24 VAL 31 24 23 22 21 20 19 18 17 16...

Page 86: ...egister Name TOP Access Type Read Write Offset 0x08 Reset Value 0xFFFFFFFF VAL 31 0 RTC Top Value VAL wraps at this value 31 30 29 28 27 26 25 24 VAL 31 24 23 22 21 20 19 18 17 16 VAL 23 16 15 14 13 1...

Page 87: ...ess Type Write only Offset 0x10 Reset Value 0x00000000 Writing a zero to a bit in this register has no effect Writing a one to a bit in this register will set the corresponding bit in IMR 31 30 29 28...

Page 88: ...ss Type Write only Offset 0x14 Reset Value 0x00000000 Writing a zero to a bit in this register has no effect Writing a one to a bit in this register will clear the corresponding bit in IMR 31 30 29 28...

Page 89: ...corresponding interrupt is disabled 1 The corresponding interrupt is enabled A bit in this register is cleared when the corresponding bit in IDR is written to one A bit in this register is set when th...

Page 90: ...pe Read only Offset 0x1C Reset Value 0x00000000 TOPI Top Interrupt This bit is set when VAL has wrapped at its top value This bit is cleared when the corresponding bit in ICR is written to one 31 30 2...

Page 91: ...ffset 0x20 Reset Value 0x00000000 Writing a zero to a bit in this register has no effect Writing a one to a bit in this register will clear the corresponding bit in SR and the corresponding interrupt...

Page 92: ...Figure 9 1 WDT Block Diagram 9 4 Product Dependencies In order to use this module other parts of the system must be configured correctly as described below 9 4 1 Power Management When the WDT is enabl...

Page 93: ...run To avoid accidental disabling of the watchdog the CTRL register must be written twice first with the KEY field set to 0x55 then 0xAA without changing the other bits Failure to do so will cause th...

Page 94: ...y This field must be written twice first with key value 0x55 then 0xAA for a write operation to be effective This field always reads as zero PSEL Prescale Select PSEL is used as watchdog timeout perio...

Page 95: ...ue 0x00000000 CLR Writing periodically any value to this field when the WDT is enabled within the watchdog time out period will prevent a watchdog reset This field always reads as zero 31 30 29 28 27...

Page 96: ...egister IPR and an Interrupt Request Register IRR The IPRs are used to assign a priority level and an autovector to each group and the IRRs are used to identify the active interrupt request within eac...

Page 97: ...PU into debug mode the INTC continues normal operation 10 5 Functional Description All of the incoming interrupt requests IREQs are sampled into the corresponding Interrupt Request Register IRR The IR...

Page 98: ...est has priority over all other interrupt requests NMI has a dedicated exception vec tor address defined by the AVR32 architecture so AUTOVECTOR is undefined when INTLEVEL indicates that an NMI is pen...

Page 99: ...2H AVR32 10 2012 AT32UC3A3 pipeline stall which prevents the interrupt from accidentally re triggering in case the handler is exited and the interrupt mask is cleared before the interrupt request is c...

Page 100: ...0x00000000 0x0FC Interrupt Priority Register 63 IPR63 Read Write 0x00000000 0x100 Interrupt Request Register 0 IRR0 Read only N A 0x104 Interrupt Request Register 1 IRR1 Read only N A 0x1FC Interrupt...

Page 101: ...he interrupt handler of the corresponding group 00 INT0 Lowest priority 01 INT1 10 INT2 11 INT3 Highest priority AUTOVECTOR Autovector Address Handler offset is used to give the address of the interru...

Page 102: ...048 possible input lines The IRRs are read by the software interrupt handler in order to determine which interrupt request is pending The IRRs are sampled continuously and are read only 31 30 29 28 27...

Page 103: ...et Value N A CAUSE Interrupt Group Causing Interrupt of Priority n ICRn identifies the group with the highest priority that has a pending interrupt of level n This value is only defined when at least...

Page 104: ...rnal Interrupt Controller EIC 1 2 External Interrupt Controller EIC 2 3 External Interrupt Controller EIC 3 4 External Interrupt Controller EIC 4 5 External Interrupt Controller EIC 5 6 External Inter...

Page 105: ...ersal Synchronous Asynchronous Receiver Transmitter USART2 8 0 Universal Synchronous Asynchronous Receiver Transmitter USART3 9 0 Serial Peripheral Interface SPI0 10 0 Serial Peripheral Interface SPI1...

Page 106: ...DSTT 2 DMA Controller DMACA ERR 3 DMA Controller DMACA SRCT 4 DMA Controller DMACA TFR 26 0 Memory Stick Interface MSI 27 0 Two wire Slave Interface TWIS0 28 0 Two wire Slave Interface TWIS1 29 0 Err...

Page 107: ...filter to remove spikes from the interrupt source Every interrupt pin can also be configured to be asynchronous in order to wake up the part from sleep modes where the CLK_SYNC clock has been disabled...

Page 108: ...cted to the same pin 11 5 2 Power Management All interrupts are available in all sleep modes as long as the EIC module is powered However in sleep modes where CLK_SYNC is stopped the interrupt must be...

Page 109: ...ered interrupts while writing a one to the bit enables level triggered interrupts If INTn is configured as an edge triggered interrupt writing a zero to the INTn bit in the EDGE register will cause th...

Page 110: ...errupt controller by two cycles of CLK_SYNC see Figure 11 2 on page 110 and Figure 11 3 on page 110 for examples FILTER off It is also possible to apply a filter on EXTINTn by writing a one to INTn bi...

Page 111: ...w level and a one in EDGE INTn will be interpreted as high level EIC_WAKE will be set immediately after the source triggers the interrupt while the correspond ing bit in ISR and the interrupt to the i...

Page 112: ...scan pins can be left controlled by the I O Controller or other peripherals The Keypad Scan function is enabled by writing SCAN EN to 1 which starts the keypad scan counter The SCAN outputs are tri s...

Page 113: ...00000000 0x010 Interrupt Clear Register ICR Write only 0x00000000 0x014 Mode Register MODE Read Write 0x00000000 0x018 Edge Register EDGE Read Write 0x00000000 0x01C Level Register LEVEL Read Write 0x...

Page 114: ...iting a zero to this bit has no effect Writing a one to this bit will set the corresponding bit in IMR NMI Non Maskable Interrupt Writing a zero to this bit has no effect Writing a one to this bit wil...

Page 115: ...ing a zero to this bit has no effect Writing a one to this bit will clear the corresponding bit in IMR NMI Non Maskable Interrupt Writing a zero to this bit has no effect Writing a one to this bit wil...

Page 116: ...ding bit in IDR is written to one This bit is set when the corresponding bit in IER is written to one NMI Non Maskable Interrupt 0 The Non Maskable Interrupt is disabled 1 The Non Maskable Interrupt i...

Page 117: ...An interrupt event has occurred This bit is cleared by writing a one to the corresponding bit in ICR NMI Non Maskable Interrupt 0 An interrupt event has not occurred 1 An interrupt event has occurred...

Page 118: ...ng a zero to this bit has no effect Writing a one to this bit will clear the corresponding bit in ISR NMI Non Maskable Interrupt Writing a zero to this bit has no effect Writing a one to this bit will...

Page 119: ...upt n 0 The external interrupt is edge triggered 1 The external interrupt is level triggered NMI Non Maskable Interrupt 0 The Non Maskable Interrupt is edge triggered 1 The Non Maskable Interrupt is l...

Page 120: ...external interrupt triggers on falling edge 1 The external interrupt triggers on rising edge NMI Non Maskable Interrupt 0 The Non Maskable Interrupt triggers on falling edge 1 The Non Maskable Interru...

Page 121: ...The external interrupt triggers on low level 1 The external interrupt triggers on high level NMI Non Maskable Interrupt 0 The Non Maskable Interrupt triggers on low level 1 The Non Maskable Interrupt...

Page 122: ...rnal Interrupt n 0 The external interrupt is not filtered 1 The external interrupt is filtered NMI Non Maskable Interrupt 0 The Non Maskable Interrupt is not filtered 1 The Non Maskable Interrupt is f...

Page 123: ...INTn External Interrupt n If TESTEN is 1 the value written to this bit will be the value to the interrupt detector and the value on the pad will be ignored NMI Non Maskable Interrupt If TESTEN is 1 th...

Page 124: ...t n 0 The external interrupt is synchronized to CLK_SYNC 1 The external interrupt is asynchronous NMI Non Maskable Interrupt 0 The Non Maskable Interrupt is synchronized to CLK_SYNC 1 The Non Maskable...

Page 125: ...scanning is enabled PRESC Prescale select for the keypad scan rate Scan rate 2 SCAN PRESC 1 TRC The RC clock period can be found in the Electrical Characteristics section PIN The index of the current...

Page 126: ...o to this bit has no effect Writing a one to this bit will enable the corresponding external interrupt NMI Non Maskable Interrupt Writing a zero to this bit has no effect Writing a one to this bit wil...

Page 127: ...o to this bit has no effect Writing a one to this bit will disable the corresponding external interrupt NMI Non Maskable Interrupt Writing a zero to this bit has no effect Writing a one to this bit wi...

Page 128: ...rrupt n 0 The corresponding external interrupt is disabled 1 The corresponding external interrupt is enabled NMI Non Maskable Interrupt 0 The Non Maskable Interrupt is disabled 1 The Non Maskable Inte...

Page 129: ...listed in the following tables The module bus clocks listed here are connected to the system bus clocks Please refer to the Power Manager chapter for details Table 11 3 Module Configuration Feature E...

Page 130: ...terfaces a flash block with the 32 bit internal HSB bus Perfor mance for uncached systems with high clock frequency and one wait state is increased by placing words with sequential addresses in altern...

Page 131: ...other read access to the flash The address map of the User page is given in Figure 12 1 12 4 4 Read operations The None provides two different read modes 0 wait state 0ws for clock frequencies access...

Page 132: ...d Read Mode Disable HSDIS control the speed mode When a High Speed Read Mode command is detected the FLASHC automatically inserts additional wait states until it is ready for the next read in flash Af...

Page 133: ...around within the internal memory area address space and appear to be repeated within it When writing to the page buffer the PAGEN field in the FCMD register is updated with the page number correspon...

Page 134: ...of the flash control ler is activated All flash commands except for Quick Page Read QPR will generate an interrupt request upon completion if FRDY is set After a command has been written to FCMD the...

Page 135: ...e is as follows Reset the page buffer with the Clear Page Buffer command Fill the page buffer with the desired contents using only 32 bit access Programming starts as soon as the programming key and t...

Page 136: ...ome regions locked These locked regions are reserved for a boot or default application Locked regions can be unlocked to be erased and then programmed with another application or other data To lock or...

Page 137: ...ered when the security bit is set If the security bit is set only an external JTAG Chip Erase can clear EPFL No internal commands can alter EPFL if the security bit is set When the fuse is erased i e...

Page 138: ...write or erase of any of the special function fuse bits in Table 12 3 was attempted while the flash is locked by the security bit The lock bits are implemented using the lowest 16 general purpose fus...

Page 139: ...bits in FSR are 0 All bits in FGPFR and FCFR are dependent on the programmed state of the fuses they map to Any bits in these registers not mapped to a fuse read 0 Table 12 4 Flash controller registe...

Page 140: ...KE Lock Error Interrupt Enable 0 Lock Error does not generate an interrupt 1 Lock Error generates an interrupt PROGE Programming Error Interrupt Enable 0 Programming Error does not generate an interru...

Page 141: ...corresponding interrupt to be requested if the PROGE bit in FCR is set 31 30 29 28 27 26 25 24 KEY 23 22 21 20 19 18 17 16 PAGEN 15 8 15 14 13 12 11 10 9 8 PAGEN 7 0 7 6 5 4 3 2 1 0 CMD Table 12 5 Set...

Page 142: ...ter If the field is written with a different value the write is not performed and no action is started This field always reads as 0 Quick Page Read User Page 15 QPRUP Read High Speed Enable 16 HSEN Re...

Page 143: ...d since the last read of FSR PROGE Programming Error Status Automatically cleared when FSR is read 0 No invalid commands and no bad keywords were written in the Flash Command Register FCMD 1 An invali...

Page 144: ...provide all flash sizes indicated in the table LOCKx Lock Region x Lock Status 0 The corresponding lock region is not locked 1 The corresponding lock region is locked Table 12 7 Flash size FSZ Flash...

Page 145: ...32 GP fuses GPFxx General Purpose Fuse xx 0 The fuse has a written programmed state 1 The fuse has an erased state 31 30 29 28 27 26 25 24 GPF63 GPF62 GPF61 GPF60 GPF59 GPF58 GPF57 GPF56 23 22 21 20...

Page 146: ...e Fuse xx 0 The fuse has a written programmed state 1 The fuse has an erased state 31 30 29 28 27 26 25 24 GPF31 GPF30 GPF29 GPF28 GPF27 GPF26 GPF25 GPF24 23 22 21 20 19 18 17 16 GPF23 GPF22 GPF21 GPF...

Page 147: ...ription refer to Electrical Characteristics chapter If the BODLEVEL is set higher than VDDCORE and enabled by fuses the part will be in constant reset To recover from this situation apply an external...

Page 148: ...After the JTAG chip erase command the FGPFRLO register value is 0xFFFFFFFF 12 10 Serial number in the factory page Each device has a unique 120 bits serial number located in the factory page and read...

Page 149: ...e normal latency to connect a master to a slave is one cycle except for the default master of the accessed slave which is connected directly zero cycle latency The Bus Matrix provides 16 Special Funct...

Page 150: ...master type no default last access master fixed default master whereas the 4 bit FIXED_DEFMSTR field selects a fixed default master pro vided that DEFMSTR_TYPE is set to fixed default master Please r...

Page 151: ...generated at the end of each sixteen beat boundary inside INCR transfer This selection can be done through the field ULBT of the Master Configuration Registers MCFG Slot Cycle Limit Arbitration The B...

Page 152: ...gorithm It allows the Bus Matrix arbiters to remove the one latency cycle for the fixed default master per slave At the end of the current access the slave remains connected to its fixed default maste...

Page 153: ...00002 0x003C Master Configuration Register 15 MCFG15 Read Write 0x00000002 0x0040 Slave Configuration Register 0 SCFG0 Read Write 0x00000010 0x0044 Slave Configuration Register 1 SCFG1 Read Write 0x00...

Page 154: ...egister B for Slave 9 PRBS9 Read Write 0x00000000 0x00D0 Priority Register A for Slave 10 PRAS10 Read Write 0x00000000 0x00D4 Priority Register B for Slave 10 PRBS10 Read Write 0x00000000 0x00D8 Prior...

Page 155: ...ecial Function Register 10 SFR10 Read Write 0x013C Special Function Register 11 SFR11 Read Write 0x0140 Special Function Register 12 SFR12 Read Write 0x0144 Special Function Register 13 SFR13 Read Wri...

Page 156: ...succession of single accesses allowing re arbitration at each beat of the INCR burst 2 Four Beat Burst The undefined length burst is split into a four beat burst allowing re arbitration at each four b...

Page 157: ...ve access if no other master request is pending the slave stays connected to the last master having accessed it This results in not having one cycle latency when the last master tries to access the sl...

Page 158: ...ype Read Write Offset Reset Value 0x00000000 MxPR Master x Priority Fixed priority of Master x for accessing the selected slave The higher the number the higher the priority 31 30 29 28 27 26 25 24 M7...

Page 159: ...Read Write Offset Reset Value 0x00000000 MxPR Master x Priority Fixed priority of Master x for accessing the selected slave The higher the number the higher the priority 31 30 29 28 27 26 25 24 M15PR...

Page 160: ...Type Read Write Offset 0x110 0x115 Reset Value SFR Special Function Register Fields Those registers are not a HMATRIX specific register The field of those will be defined where they are used 31 30 29...

Page 161: ...rface Each slave has its own arbiter thus allowing a different arbitration per slave The slave number in the table below can be used to index the HMATRIX control registers For example HMATRIX SCFG4 re...

Page 162: ...ve Connections CPU Data 0 CPU Instruction 1 CPU SAB 2 PDCA 3 Internal Flash 0 HSB PB Bridge A 1 HSB PB Bridge B 2 AES 3 HMATRIX SLAVES HMATRIX MASTERS Embedded CPU SRAM 4 DMACA Master 0 4 DMACA Master...

Page 163: ...al NAND Flash support Static Memory Controller on Chip Select 4 Optional CompactFlashTM support Static Memory Controller on Chip Select 5 Optional CompactFlashTM support 14 2 Overview The External Bus...

Page 164: ...emory Controller Compact FLash Logic NAND Flash SmartMedia Logic ECCHRS Controller Address Decoders Chip Select Assignor MUX Logic Peripheral Bus I O Controller DATA 15 0 NWE1 NWE0 NRD NCS 5 0 ADDR 23...

Page 165: ...ow SDA10 SDRAM Address Bus Line 10 Output Low RAS CAS Row and Column Signal Output Low CompactFlash dedicated lines CFCE1 CFCE2 CompactFlash Chip Enable Output Low CFRNW CompactFlash Read Not Write Si...

Page 166: ...CLK_EBI CLK_SDRAMC CLK_SMC ADDR 17 BA1 ADDR 17 SDRAMC Bank 1 SMCAddress Bus Line 17 Output SMC CompactFlash shared lines NRD NRD CFNOE SMC Read Signal CompactFlash CFNOE Output Low NWE0 NWE0 NWE CFNW...

Page 167: ...B X Table 14 3 EBI Special Function Register Fields Description SFR6 Bit Number Bit name Description 31 6 Reserved 5 CS5A 0 Chip Select 5 NCS 5 is connected to a Static Memory device For each access t...

Page 168: ...Multiplexing is also designed to respect the data float times defined in the Memory Controllers Furthermore refresh cycles of the SDRAM are executed independently by the SDRAMC without delaying the ot...

Page 169: ...andattribute memory mode The different modes are accessed through a specific memory mapping as illustrated on Figure 14 2 on page 169 ADDR 23 21 bits of the transfer address are used to select the des...

Page 170: ...f this logic During write operations in all modes the CompactFlash logic drives the write command signal of the SMC on CFNWE signal Addtionnal external logic is required to drive _WE and _IOWR compact...

Page 171: ...en These pins must not be used to drive any other mem ory devices The EBI pins in Table 14 8 on page 172 remain shared between all memory areas when the cor responding CompactFlash interface is enable...

Page 172: ...valid throughout the transfer as does the address bus The CompactFlash _WAIT signal is con nected to the NWAIT input of the Static Memory Controller For details on these waveforms and timings refer t...

Page 173: ...ccessing the address space reserved to NCS 2 and or NCS 3 The NAND Flash logic drives the read and write command signals of the SMC on the NANDOE and NANDWE signals when the NCS 2 and or NCS 3 signal...

Page 174: ...of the NAND Flash device are distinguished by using their address within the NCSx address space The chip enable CE signal of the device and the ready busy R B signals are connected to I O Controller l...

Page 175: ...ic Device Controller SMC DATA 7 0 D 7 0 D 7 0 D 7 0 DATA 15 0 D 15 8 D 15 8 ADDR 0 A 0 NBS0 2 ADDR 1 A 1 A 0 A 0 ADDR 23 2 A 23 2 A 22 1 A 22 1 NCS 0 NCS 5 CS CS CS NRD OE OE OE NWE0 WE WE 1 WE NWE1 W...

Page 176: ...any address bit For details see Section 14 6 6 ADDR 21 CLE 3 ADDR 22 REG ALE 3 NCS 0 NCS 1 SDCS 0 NCS 2 CE0 NCS 3 CE1 NCS 4 CFCS0 1 NCS 5 CFCS1 1 NANDOE OE NANDWE WE NRD OE NWE0 WE NWE1 DQM1 IOR CFRN...

Page 177: ...SDRAM 2Mx8 D 7 0 CS CLK CKE WE RAS CAS DQM A 9 0 A 10 A 11 BA0 BA1 SDRAM 2Mx8 D 7 0 CS CLK CKE WE RAS CAS DQM A 9 0 A 10 A 11 BA0 BA1 DATA 7 0 DATA 15 8 ADDR 11 2 SDA10 ADDR 13 ADDR 16 ADDR 17 ADDR 1...

Page 178: ...32 bytes 15 2 Overview The Static Memory Controller SMC generates the signals that control the access to the exter nal memory devices or peripheral devices It has 6 chip selects and a 24 bit address...

Page 179: ...ADDR 1 ADDR AD_MSB 2 DATA 15 0 NWAIT User Interface Peripheral Bus NCS 5 0 NRD NWR0 NWE A0 NBS0 NWR1 NBS1 A1 NWR2 NBS2 A AD_MSB 2 D 15 0 NWAIT EBI Mux Logic Table 15 1 I O Lines Description Pin Name...

Page 180: ...avoid freezing the SMC in an undefined state 15 6 Functional Description 15 6 1 Application Example Figure 15 2 SMC Connections to Static Memory Devices 15 6 2 External Memory Mapping The SMC provides...

Page 181: ...bit memory on NCS2 15 6 3 2 Byte write or byte select access Each chip select with a 16 bit data bus can operate with one of two different types of write access byte write or byte select access This...

Page 182: ...cess mode is used to connect two 8 bit devices as a 16 bit memory The byte write option is illustrated on Figure 15 6 on page 183 Byte select access In this mode read write operations can be enabled d...

Page 183: ...iplexed Signal Translation 15 6 4 Standard Read and Write Protocols In the following sections the byte access type is not considered Byte select lines NBS0 to NBS1 always have the same timing as the a...

Page 184: ...rd Read Cycle NRD waveform The NRD signal is characterized by a setup timing a pulse width and a hold timing 1 NRDSETUP the NRD setup time is defined as the setup of address before the NRD falling edg...

Page 185: ...l read cycle time is equal to Similarly All NRD and NCS timings are defined separately for each chip select as an integer number of CLK_SMC cycles To ensure that the NRD and NCS timings are coherent t...

Page 186: ...icates which signal of NRD and NCS controls the read operation Read is controlled by NRD MODE READMODE 1 Figure 15 9 on page 187 shows the waveforms of a read operation of a typical asynchronous RAM T...

Page 187: ...lid tPACC after the falling edge of the NCS signal and remains valid until the rising edge of NCS Data must be sampled when NCS is raised In that case the MODE READMODE bit must be written to zero rea...

Page 188: ...ime between NWE falling edge and NWE rising edge 3 NWEHOLD the NWE hold time is defined as the hold time of address and data after the NWE rising edge The NWE waveforms apply to all byte write lines i...

Page 189: ...ed separately for each chip select as an integer num ber of CLK_SMC cycles To ensure that the NWE and NCS timings are coherent the user must define the total write cycle instead of the hold timing Thi...

Page 190: ...itten to one A null value leads to unpredictable behavior 15 6 4 5 Write mode The Write Mode bit in the MODE register MODE WRITEMODE of the corresponding chip select indicates which signal controls th...

Page 191: ...E written to zero The data is put on the bus during the pulse and hold steps of the NCS signal The internal data buffers are turned out after the NCSWRSETUP time and until the end of the write cycle r...

Page 192: ...then it is strictly recommended to pro gram non null values so as to cover possible skews between address NCS and NRD signals For write operations If a null hold value is programmed on NWE the SMC ca...

Page 193: ...lines are all set to high level Figure 15 15 on page 193 illustrates a chip select wait state between access on Chip Select 0 NCS0 and Chip Select 2 NCS2 Figure 15 15 Chip Select Wait State Between a...

Page 194: ...edge Without an early read wait state the write operation could not complete properly in NWE controlled mode MODE WRITEMODE 1 and if there is no hold timing NWEHOLD 0 the feedback of the write contro...

Page 195: ...5 17 Early Read Wait State NCS Controlled Write with No Hold Followed by a Read with No Setup CLK_SMC A AD_MSB 2 NBS0 NBS1 A0 A1 NWE NRD D 15 0 No hold No setup Read cycle READMODE 0 or READMODE 1 Ear...

Page 196: ...the user interface are made to different devices dif ferent chip selects then one single chip select wait state is applied On the other hand if accesses before and after writing the user interface are...

Page 197: ...ata float wait cycles between 0 and 15 before the external device releases the bus and represents the time allowed for the data output to go to high impedance after the memory is disabled Data float w...

Page 198: ...DFCYCLES 2 Figure 15 20 TDF Period in NCS Controlled Read Operation TDFCYCLES 3 CLK_SMC A AD_MSB 2 NBS0 NBS1 A0 A1 NRD NCS D 15 0 tPACC NRD controlled read operation TDF 2 clock cycles CLK_SMC A AD_MS...

Page 199: ...Inserted if the TDF Period Is over when the Next Access Begins 15 6 6 3 TDF optimization disabled MODE TDFMODE 0 When optimization is disabled data float wait states are inserted at the end of the rea...

Page 200: ...n Different Chip Selects CLK_SMC A AD_MSB 2 NBS0 NBS1 A0 A1 Read1 controlling signal NRD Read2 controlling signal NRD D 15 0 Read1 hold 1 Read1 cycle TDFCYCLES 6 Chip Select Wait State 5 TDF WAIT STAT...

Page 201: ...in Page Mode Section 15 6 9 or in Slow Clock Mode Section 15 6 8 The NWAIT signal is assumed to be a response of the external device to the read write request of the SMC Then NWAIT is examined by the...

Page 202: ...Figure 15 26 on page 203 Figure 15 25 Write Access with NWAIT Assertion in Frozen Mode MODE EXNWMODE 2 CLK_SMC A AD_MSB 2 NBS0 NBS1 A0 A1 NWE NCS D 15 0 6 5 4 4 3 3 2 2 1 1 2 1 2 2 1 0 0 FROZEN STATE...

Page 203: ...ozen Mode MODE EXNWMODE 2 CLK_SMC A AD_MSB 2 NBS0 NBS1 A0 A1 NCS NRD NWAIT Internally synchronized NWAIT signal EXNWMODE 2 Frozen READMODE 0 NCS controlled NRDPULSE 2 NRDHOLD 6 NCSRDPULSE 5 NCSRDHOLD...

Page 204: ...d This mode must be selected when the external device uses deassertion of the NWAIT signal to indicate its ability to complete the read or write operation If the NWAIT signal is deasserted before the...

Page 205: ...s Ready Mode EXNWMODE 3 CLK_SMC A AD_MSB 2 NBS0 NBS1 A0 A1 NCS NRD 6 6 5 5 4 4 3 2 3 1 2 1 0 NWAIT Internally synchronized NWAIT signal Read cycle EXNWMODE 3 Ready mode READMODE 0 NCS_controlled NRDPU...

Page 206: ...access without detecting the NWAIT signal assertion This is true in frozen mode as well as in ready mode This is illustrated on Figure 15 29 on page 206 When the MODE EXNWMODE field is enabled ready...

Page 207: ...e slow mode is active on all chip selects 15 6 8 1 Slow clock mode waveforms Figure 15 30 on page 207 illustrates the read and write operations in slow clock mode They are valid on all chip selects Ta...

Page 208: ...ngs Figure 15 32 on page 209 illustrates the recommended procedure to properly switch from one mode to the other Figure 15 31 Clock Rate Transition Occurs while the SMC is Performing a Write Operation...

Page 209: ...detailed in Table 15 6 on page 209 With page mode memory devices the first access to one page tpa takes longer than the subse quent accesses to the page tsa as shown in Figure 15 33 on page 210 When...

Page 210: ...does not check the coherency of timings It will always apply the NCSRDPULSE tim ings as page access timing tpa and the NRDPULSE for accesses to the page tsa even if the programmed value for tpa is sho...

Page 211: ...cess to an 8 bit mem ory device in page mode with 8 byte pages Access to D1 causes a page access with a long access time tpa Accesses to D3 and D7 though they are not sequential accesses only require...

Page 212: ...s the chip select number Sixteen bytes 0x10 are required per chip select The user must complete writing the configuration by writing anyone of the Mode Registers Table 15 8 SMC Register Memory Map Off...

Page 213: ...etup Length in WRITE Access In write access the NCS signal setup length is defined as NWESETUP NWE Setup Length The NWE signal setup length is defined as 31 30 29 28 27 26 25 24 NCSRDSETUP 23 22 21 20...

Page 214: ...page mode read access the NRDPULSE field defines the duration of the subsequent accesses in the page NCSWRPULSE NCS Pulse Length in WRITE Access In write access the NCS signal pulse length is defined...

Page 215: ...of the NRD and NCS signals It is defined as NWECYCLE 8 0 Total Write Cycle Length The total write cycle length is the total duration in clock cycles of the write cycle It is equal to the sum of the s...

Page 216: ...ess 0 TDF optimization is disabled The number of TDF wait states is inserted before the next access begins TDFCYCLES Data Float Time This field gives the integer number of clock cycles required by the...

Page 217: ...will be inserted after the setup of NCS DBW Data Bus Width 0 8 bit bus 1 16 bit bus 2 Reserved 3 Reserved BAT Byte Access Type 0 Byte select access type Write operation is controlled using NCS NWE NBS...

Page 218: ...is marked busy after the rising edge of NCS If TDF optimization is enabled TDFMODE 1 TDF wait states are inserted after the setup of NCS 1 The read operation is controlled by the NRD signal If TDF cyc...

Page 219: ...n by software CAS latency of one two and three supported Auto Precharge command not used 16 2 Overview The SDRAM Controller SDRAMC extends the memory capabilities of a chip by providing the interface...

Page 220: ...A 1 0 RAS CAS SDW E DQM 0 SDRAMC_A 9 0 D 15 0 EBI MUX Logic DATA 15 0 SDCK SDCKE NCS 1 RAS CAS ADDR 17 16 SDW E ADDR 0 DQM 1 NW E1 ADDR 11 2 SDRAMC_A 10 SDA10 SDRAMC_A 12 11 ADDR 13 14 Table 16 1 I O...

Page 221: ...the values set in the SDRAMC Configuration Reg ister CR The SDRAMC s function is to make the SDRAM device access protocol transparent to the user Table 16 2 on page 222 to Table 16 4 on page 222 illus...

Page 222: ...r must issue a Deep power mode command in the Mode MD register and wait for the command to be completed Table 16 2 SDRAM Configuration Mapping 2K Rows 256 512 1024 2048 Columns CPU Address Line 27 26...

Page 223: ...write access to any SDRAM address 5 A minimum pause of 200 s is provided to precede any signal toggle 6 An All Banks Precharge command must be issued to the SDRAM devices The user must write the valu...

Page 224: ...a sequential write access writing to the SDRAM device is carried out If the next access is a write sequential access but the current access is to a boundary page or if the next access is in another ro...

Page 225: ...ter of the SDRAMC After a read command additional wait states are generated to comply with the CAS latency one two or three clock delays specified in the CR register For a single access or an incremen...

Page 226: ...precharge command activates the new row and initiates a read or write command To comply with SDRAM timing parameters an additional clock cycle is inserted between the precharge and active tRP commands...

Page 227: ...s between successive refresh cycles A refresh error interrupt is generated when the previous auto refresh command did not perform In this case a Refresh Error Status bit is set in the Interrupt Status...

Page 228: ...ss by config uring the Timeout field in the Low Power Register LPR TIMEOUT 16 7 6 1 Self refresh mode This mode is selected by writing the value one to the Low Power Configuration Bits field in the SD...

Page 229: ...in in self refresh mode for an indefinite period This is described in Figure 16 8 on page 229 Figure 16 8 Self Refresh Mode Behavior 16 7 6 2 Low power mode This mode is selected by writing the value...

Page 230: ...all internal voltage generators inside the SDRAM are stopped and all data is lost When this mode is enabled the user must not access to the SDRAM until a new initialization sequence is done See Secti...

Page 231: ...231 32072H AVR32 10 2012 AT32UC3A3 Figure 16 10 Deep Power down Mode Behavior SDCS SDCK SDRAMC_A 12 0 RAS CAS SDWE SCKE D 15 0 Input Dnb Dnc Dnd Col d Col c Row n tRP 3...

Page 232: ...Write 0x00000000 0x10 Low Power Register LPR Read Write 0x00000000 0x14 Interrupt Enable Register IER Write only 0x00000000 0x18 Interrupt Disable Register IDR Write only 0x00000000 0x1C Interrupt Mas...

Page 233: ...ues a Load Mode Register command when the SDRAM device is accessed regardless of the cycle This command will load the CR CAS field into the SDRAM device Mode Register All the other parameters of the S...

Page 234: ...is initiated The value to be loaded depends on the SDRAMC clock frequency CLK_SDRAMC the refresh rate of the SDRAM device and the refresh burst length where 15 6 s per row is a typical value for a bu...

Page 235: ...n Activate command and a Read Write command in number of cycles Number of cycles is between 0 and 15 TRP Row Precharge Delay Reset value is three cycles This field defines the delay between a Precharg...

Page 236: ...and three cycles is managed NB Number of Banks Reset value is two banks NR Number of Row Bits Reset value is 11 row bits NC Number of Column Bits Reset value is 8 column bits CAS CAS Latency Cycles 0...

Page 237: ...le Enable A decode cycle can be added on the addresses as soon as a non sequential access is performed on the HSB bus The addition of the decode cycle allows the SDRAMC to gain time to access the SDRA...

Page 238: ...refresh mode is activated the Extended Mode Register of the SDRAM device is accessed automatically and its TCSR parameter value is updated before entry in self refresh mode PASR Partial Array Self Ref...

Page 239: ...AM device the SDCLK clock is deactivated and the SDCKE signal is set low The SDRAM device leaves the self refresh mode when accessed and enters it after the access 2 The SDRAMC issues a power down com...

Page 240: ...ER Access Type Write only Offset 0x14 Reset Value 0x00000000 Writing a zero to a bit in this register has no effect Writing a one to a bit in this register will set the corresponding bit in IMR 31 30...

Page 241: ...R Access Type Write only Offset 0x18 Reset Value 0x00000000 Writing a zero to a bit in this register has no effect Writing a one to a bit in this register will clear the corresponding bit in IMR 31 30...

Page 242: ...0 The corresponding interrupt is disabled 1 The corresponding interrupt is enabled A bit in this register is cleared when the corresponding bit in IDR is written to one A bit in this register is set w...

Page 243: ...Name ISR Access Type Read only Offset 0x20 Reset Value 0x00000000 RES Refresh Error Status This bit is set when a refresh error is detected This bit is cleared when the register is read 31 30 29 28 2...

Page 244: ...ce Register Register Name MDR Access Type Read Write Offset 0x24 Reset Value 0x00000000 MD Memory Device Type 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MD M...

Page 245: ...Type Read only Offset 0xFC Reset Value Variant Variant Number Reserved No functionality associated Version Version Number Version number of the module No functionality associated 31 30 29 28 27 26 25...

Page 246: ...errors correction per sector of 512 bytes of data for a page size of 512 1024 2048 and 4096 bytes with 8 bit data path 17 2 Overview NAND Flash and SmartMedia devices contain by default invalid blocks...

Page 247: ...ent If the CPU enters a sleep mode that disables clocks used by the ECCHRS the ECCHRS will stop functioning and resume operation after the system wakes up from sleep mode 17 4 3 Clocks The clock for t...

Page 248: ...SmartMedia is detected Read and write access must start at a page boundary The ECC results are available as soon as the counter reaches the end of the main area The val ues in the Parity Registers PR...

Page 249: ...Status Registers SR1 ECCERRn SR2 ECCERRn are set An error has been detected in the ECC code stored in the Flash memory The position of the corrupted bit can be found by the application performing an...

Page 250: ...byte page size th byte page size 1 th byte page size 2 th byte Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit...

Page 251: ...P5 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 1st byte 4th byte 3rd byte 2nd byte page size 3 th byte page size th byte page size 1 th byte page size 2 th byte Bit 7 Bit 6 Bit 5 Bit 4 Bit 3...

Page 252: ...ms an algorithm according to the scheme in Figure 17 6 on page 252 Figure 17 6 Partial Syndrome Block Diagram If the Correction Enable bit is set in the ECC Mode Register MD CORRS4 then the polynomial...

Page 253: ...an error has occurred at symbol N according to the scheme in Figure 17 8 on page 253 Figure 17 8 Chien Search Block Diagram 0 4 1 5 3 7 4 1 3 5 7 Array Mult Rom 1024x10 GF 2 inverted odd j 10 ErrorLoc...

Page 254: ...Read only 0x00000000 0x030 Parity Register 8 PR8 Read only 0x00000000 0x034 Parity Register 9 PR9 Read only 0x00000000 0x038 Parity Register 10 PR10 Read only 0x00000000 0x03C Parity Register 11 PR11...

Page 255: ...e only Offset 0x000 Reset Value 0x00000000 RST RESET Parity Writing a one to this bit will reset the ECC Parity registers Writing a zero to this bit has no effect This bit always reads as zero 31 30 2...

Page 256: ...FREEZE Halt of Computation Writing a one to this bit will stop the computation Writing a zero to this bit will allow the computation as soon as read write command to the NAND Flash or the SmartMedia...

Page 257: ...e TYPECORREC 0b1xx i e for NAND Flash device with page size of 4096 bytes and 128 bytes extra area ECC RS can manage any sub page of 512 bytes up to 8 Page Size Description 0 528 words 1 1056 words 2...

Page 258: ...R6 RECERR6 23 22 21 20 19 18 17 16 MULERR5 ECCERR5 RECERR5 MULERR4 ECCERR4 RECERR4 15 14 13 12 11 10 9 8 MULERR3 ECCERR3 RECERR3 MULERR2 ECCERR2 RECERR2 7 6 5 4 3 2 1 0 MULERR1 ECCERR1 RECERR1 MULERR0...

Page 259: ...alysis The SYNVEC n bit is set when there is at least one error in the corresponding sector The SYNVEC n bit is cleared when a read write command is detected or a software reset is performed 1 At leas...

Page 260: ...260 32072H AVR32 10 2012 AT32UC3A3 5 2560 3071 6 3072 3583 7 3584 4095 Bit Index n Sector Boundaries...

Page 261: ...g on the memory plane organization where an error occurred if a single error was detected If multiple errors were detected this field is meaningless BITADDR Bit Address During a page read this field c...

Page 262: ...ing a page read this field contains the word address 8 bit word where an error occurred if a single error was detected If multiple errors were detected this field is meaningless BITADDR0 Corrupted Bit...

Page 263: ...ng a page read this field contains the word address 8 bit word where an error occurred if a single error was detected If multiple errors were detected this field is meaningless BITADDR0 Corrupted Bit...

Page 264: ...egister must be written in the extra area used for redundancy for a 512 byte page size address 514 515 Using ECC H code one bit correction per sector of 256 bytes MD TYPECORREC 0b001 31 30 29 28 27 26...

Page 265: ...s Using ECC H code one bit correction per sector of 512 bytes MD TYPECORREC 0b010 Once the entire main area of a page is written with data this register content must be stored at any free location of...

Page 266: ...R14 23 22 21 20 19 18 17 16 MULERR13 ECCERR13 RECERR13 MULERR12 ECCERR12 RECERR12 15 14 13 12 11 10 9 8 MULERR11 ECCERR11 RECERR11 MULERR10 ECCERR10 RECERR10 7 6 5 4 3 2 1 0 MULERR9 ECCERR9 RECERR9 MU...

Page 267: ...RS This bit is cleared when a read write command is detected or a software reset is performed 1 Multiple errors detected more than four errors Registers for one ECC for a page of 512 1024 2048 4096 by...

Page 268: ...in the packet number n of 256 bytes in the page During a page read this field contains the word address 8 bit word where an error occurred if a single error was detected If multiple errors were detect...

Page 269: ...512 bytes in the page During a page read this field contains the word address 8 bit word where an error occurred if a single error was detected If multiple errors were detected this field is meaningl...

Page 270: ...bytes the entire redundancy words are made of 8 words of 10 bits All those redundancies words are concatenated to a word of 80 bits and then cut to 10 words of 8 bits to facilitate their writing in t...

Page 271: ...l the codeword and partial syndrome word for the sub page 3 PARSYND30 PARSYND39 this conclude all the codeword and partial syndrome word for the sub page 4 PARSYND40 PARSYND49 this conclude all the co...

Page 272: ...ASKDATA At the end of the correction process this field contains the mask to be XORed with the data read to perform the final correction This XORed is under the responsibility of the software This fie...

Page 273: ...only Offset 0x1A0 0x1AC Reset Value 0x00000000 OFFSET At the end of correction process this field contains the offset address of the data read to be corrected This field is meaningless if MD CORRS4 is...

Page 274: ...me IER Access Type Write only Offset 0x1B0 Reset Value 0x00000000 ENDCOR Writing a zero to this bit has no effect Writing a one to this bit will set the corresponding bit in IMR 31 30 29 28 27 26 25 2...

Page 275: ...me IDR Access Type Write only Offset 0x1B4 Reset Value 0x00000000 ENDCOR Writing a zero to this bit has no effect Writing a one to this bit will clear the corresponding bit in IMR 31 30 29 28 27 26 25...

Page 276: ...00000 ENDCOR 0 The corresponding interrupt is disabled 1 The corresponding interrupt is enabled This bit is cleared when the corresponding bit in IDR is written to one This bit is set when the corresp...

Page 277: ...cess Type Read only Offset 0x1BC Reset Value 0x00000000 ENDCOR This bit is cleared when the corresponding bit in ISCR is written to one This bit is set when a correction process has ended 31 30 29 28...

Page 278: ...e Write only Offset 0x1C0 Reset Value 0x00000000 ENDCOR Writing a zero to this bit has no effect Writing a one to this bit will clear the corresponding bit in ISR and the corresponding interrupt reque...

Page 279: ...Offset 0x1FC Reset Value 0x00000000 VARIANT Variant Number Reserved No functionality associated VERSION Version Number Version number of the module No functionality associated 31 30 29 28 27 26 25 24...

Page 280: ...ance is listed in the following tables The module bus clocks listed here are connected to the system bus clocks according to the table in the Power Manager section Table 17 2 Module clock name Module...

Page 281: ...CPU intervention for data transfers improving the performance of the microcon troller The PDCA can transfer data from memory to a peripheral or from a peripheral to memory The PDCA consists of multipl...

Page 282: ...LK_PDCA_HSB and one Peripheral Bus clock CLK_PDCA_PB These clocks are generated by the Power Man ager Both clocks are enabled at reset and can be disabled in the Power Manager It is recommended to dis...

Page 283: ...sed by one Both MAR and TCR can be read while the PDCA channel is active to monitor the DMA progress See Section 18 5 3 The channel must be enabled for a transfer to start A channel is enable by writi...

Page 284: ...the different peripherals and then to the peripheral specific chapter for information about the size option available for the different registers 18 5 7 Enabling and Disabling Each DMA channel is ena...

Page 285: ...f stall cycles since last channel reset both for read and write The maximum latency since last channel reset both for read and write These measurements can be extracted by software and used to generat...

Page 286: ...ster Table 18 2 PDCA Channel Configuration Registers Offset Register Register Name Access Reset 0x000 n 0x040 Memory Address Register MAR Read Write 0x00000000 0x004 n 0x040 Peripheral Select Register...

Page 287: ...04 Channel0 Read Data Cycles PRDATA0 Read only 0x00000000 0x808 Channel0 Read Stall Cycles PRSTALL0 Read only 0x00000000 0x80C Channel0 Read Max Latency PRLAT0 Read only 0x00000000 0x810 Channel0 Writ...

Page 288: ...Memory Address Address of memory buffer MADDR should be programmed to point to the start of the memory buffer when configuring the PDCA During transfer MADDR will point to the next memory location to...

Page 289: ...channel Writing a PID will select both which handshake interface to use the direction of the transfer and also the address of the Receive Transfer Holding Register for the peripheral See the Module C...

Page 290: ...x00000000 TCV Transfer Counter Value Number of data items to be transferred by the PDCA TCV must be programmed with the total number of transfers to be made During transfer TCV contains the number of...

Page 291: ...0x040 Reset Value 0x00000000 MARV Memory Address Reload Value Reload Value for the MAR register This value will be loaded into MAR when TCR reaches zero if the TCRR register has a non zero value 31 30...

Page 292: ...fer Counter Reload Value Reload value for the TCR register When TCR reaches zero it will be reloaded with TCRV if TCRV has a positive value If TCRV is zero no more transfers will be performed for the...

Page 293: ...R Clearing the SR TERR bit will allow the channel to transmit data The memory address must first be set to point to a valid location TDIS Transfer Disable Writing a zero to this bit has no effect Writ...

Page 294: ...Access Type Read Write Offset 0x018 n 0x040 Reset Value 0x00000000 SIZE Size of Transfer 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SIZE Table 18 5 Size of T...

Page 295: ...00000000 TEN Transfer Enabled This bit is cleared when the TDIS bit in CR is written to one This bit is set when the TEN bit in CR is written to one 0 Transfer is disabled for the DMA channel 1 Transf...

Page 296: ...e Write only Offset 0x020 n 0x040 Reset Value 0x00000000 Writing a zero to a bit in this register has no effect Writing a one to a bit in this register will set the corresponding bit in IMR 31 30 29 2...

Page 297: ...Write only Offset 0x024 n 0x040 Reset Value 0x00000000 Writing a zero to a bit in this register has no effect Writing a one to a bit in this register will clear the corresponding bit in IMR 31 30 29...

Page 298: ...e corresponding interrupt is disabled 1 The corresponding interrupt is enabled A bit in this register is cleared when the corresponding bit in IDR is written to one A bit in this register is set when...

Page 299: ...it is set when one or more transfer errors has occurred since reset or the last write to CR ECLR TRC Transfer Complete This bit is cleared when the TCR and or the TCRR holds a non zero value This bit...

Page 300: ...unter Reset Writing a zero to this bit has no effect Writing a one to this bit will reset the counter in the channel specified in MON0CH This bit always reads as zero CH1OF Channel 1 Overflow Freeze 0...

Page 301: ...RDATA0 Access Type Read only Offset 0x804 Reset Value 0x00000000 DATA Data Cycles Counted Since Last Reset Clock cycles are counted using the CLK_PDCA_HSB clock 31 30 29 28 27 26 25 24 DATA 31 24 23 2...

Page 302: ...ALL0 Access Type Read only Offset 0x808 Reset Value 0x00000000 STALL Stall Cycles Counted Since Last Reset Clock cycles are counted using the CLK_PDCA_HSB clock 31 30 29 28 27 26 25 24 STALL 31 24 23...

Page 303: ...et Value 0x00000000 LAT Maximum Transfer Initiation Cycles Counted Since Last Reset Clock cycles are counted using the CLK_PDCA_HSB clock This counter is saturating The register is reset only when PCO...

Page 304: ...PWDATA0 Access Type Read only Offset 0x810 Reset Value 0x00000000 DATA Data Cycles Counted Since Last Reset Clock cycles are counted using the CLK_PDCA_HSB clock 31 30 29 28 27 26 25 24 DATA 31 24 23...

Page 305: ...TALL0 Access Type Read only Offset 0x814 Reset Value 0x00000000 STALL Stall Cycles Counted Since Last Reset Clock cycles are counted using the CLK_PDCA_HSB clock 31 30 29 28 27 26 25 24 STALL 31 24 23...

Page 306: ...et Value 0x00000000 LAT Maximum Transfer Initiation Cycles Counted Since Last Reset Clock cycles are counted using the CLK_PDCA_HSB clock This counter is saturating The register is reset only when PCO...

Page 307: ...RDATA1 Access Type Read only Offset 0x81C Reset Value 0x00000000 DATA Data Cycles Counted Since Last Reset Clock cycles are counted using the CLK_PDCA_HSB clock 31 30 29 28 27 26 25 24 DATA 31 24 23 2...

Page 308: ...ALL1 Access Type Read only Offset 0x820 Reset Value 0x00000000 STALL Stall Cycles Counted Since Last Reset Clock cycles are counted using the CLK_PDCA_HSB clock 31 30 29 28 27 26 25 24 STALL 31 24 23...

Page 309: ...et Value 0x00000000 LAT Maximum Transfer Initiation Cycles Counted Since Last Reset Clock cycles are counted using the CLK_PDCA_HSB clock This counter is saturating The register is reset only when PCO...

Page 310: ...PWDATA1 Access Type Read only Offset 0x828 Reset Value 0x00000000 DATA Data Cycles Counted Since Last Reset Clock cycles are counted using the CLK_PDCA_HSB clock 31 30 29 28 27 26 25 24 DATA 31 24 23...

Page 311: ...TALL1 Access Type Read only Offset 0x82C Reset Value 0x00000000 STALL Stall Cycles Counted Since Last Reset Clock cycles are counted using the CLK_PDCA_HSB clock 31 30 29 28 27 26 25 24 STALL 31 24 23...

Page 312: ...et Value 0x00000000 LAT Maximum Transfer Initiation Cycles Counted Since Last Reset Clock cycles are counted using the CLK_PDCA_HSB clock This counter is saturating The register is reset only when PCO...

Page 313: ...ad only Offset 0x834 Reset Value VARIANT Variant Number Reserved No functionality associated VERSION Version Number Version number of the module No functionality associated 31 30 29 28 27 26 25 24 23...

Page 314: ...heral Table 18 6 PDCA Configuration Features PDCA Number of channels 8 Table 18 7 Register Reset Values Register Reset Value PSRn n VERSION 0x00000110 Table 18 8 PDCA Handshake Signals PID Value Direc...

Page 315: ...315 32072H AVR32 10 2012 AT32UC3A3 21 TX SPI0 TDR 22 TX SPI1 TDR 23 TX ABDAC SDR Table 18 8 PDCA Handshake Signals PID Value Direction Peripheral Instance Peripheral Register...

Page 316: ...d Gather Operations Channel Locking Bus Locking FIFO Mode Pseudo Fly by Operation 19 2 Overview The DMA Controller DMACA is an HSB central DMA controller core that transfers data from a source periphe...

Page 317: ...operation must be terminated before entering sleep mode 19 4 3 Clocks The CLK_DMACA to the DMACA is generated by the Power Manager PM Before using the DMACA the user must ensure that the DMACA clock...

Page 318: ...f the master interfaces or on a separate layer Handshaking interface A set of signal registers that conform to a protocol and handshake between the DMACA and source or destination peripheral to contro...

Page 319: ...tions single and bursts These are in turn broken into a sequence of System Bus transfers Transaction A basic unit of a DMACA transfer as determined by either the hardware or soft ware handshaking inte...

Page 320: ...g The DMACA automatically reloads the channel registers at the end of each block to the value when the channel was first enabled Contiguous blocks Where the address between successive blocks is select...

Page 321: ...r left to reach a gather scatter boundary are re initialized to the source gather count SGRx SGC and destination scatter count DSRx DSC respectively at the start of each block transfer Figure 19 4 Des...

Page 322: ...System Bus transfer before requesting the master bus interface Pseudo fly by operation Typically it takes two System Bus cycles to complete a transfer one for reading the source and one for writing t...

Page 323: ...numbered channel is granted In other words if a peripheral request attached to Channel 7 and a peripheral request attached to Channel 8 have the same priority then the peripheral attached to Channel...

Page 324: ...n the hardware clears the SglReqSrcReg x SglReqD stReg x and ReqSrcReg x ReqDstReg x registers 19 8 1 2 Single Transactions Writing a 1 to the SglReqSrcReg SglReqDstReg initiates a single transaction...

Page 325: ...destination FIFO an active edge should be triggered on nDMAREQx when the destination FIFO drops below the watermark level The source transaction length CTLx SRC_MSIZE and destination transaction lengt...

Page 326: ...ed list item Each LLI block descriptor contains the corre sponding block descriptor SARx DARx LLPx CTLx To set up block chaining a sequence of linked lists must be programmed in memory The SARx DARx L...

Page 327: ...single None single No 2 Auto Reload multi block transfer with contiguous SAR Yes 0 0 0 1 CTLx LLPx are reloaded from initial values Contiguous Auto Reload No 3 Auto Reload multi block transfer with c...

Page 328: ...transfer until a write to the block interrupt clear register ClearBlock n is performed by software This clears the channel block complete interrupt For rows 2 3 4 7 and 9 of Table 19 1 on page 327 SA...

Page 329: ...lowed rows for block N 1 are rows 10 5 or 1 19 10 Programming a Channel Three registers the LLPx the CTLx and CFGx need to be programmed to set up whether single or multi block transfers take place an...

Page 330: ...o transfer the block of data assuming non memory peripherals The DMACA acknowledges at the com pletion of every transaction burst and single in the block and carry out the block transfer 6 Once the tr...

Page 331: ...e cleared 8 Clear any pending interrupts on the channel from the previous DMA transfer by writing to the Interrupt Clear registers ClearTfr ClearBlock ClearSrcTran ClearDstTran ClearErr Reading the In...

Page 332: ...address are con tiguous but the amount of data to be transferred is greater than the maximum block size CTLx BLOCK_TS then this can be achieved using the type of multi block transfer as shown in Figur...

Page 333: ...d Destination Blocks are Contiguous The DMA transfer flow is shown in Figure 19 11 on page 336 SAR 2 SAR 1 SAR 0 DAR 2 DAR 1 DAR 0 Block 2 Block 1 Block 0 Block 0 Block 1 Block 2 Address of Source Lay...

Page 334: ...MA transfer by writing to the Interrupt Clear registers ClearTfr ClearBlock ClearSrcTran ClearDstTran ClearErr Reading the Interrupt Raw Status and Interrupt Status registers confirms that all interru...

Page 335: ...software handshaking interface to handle source destination requests ii If the hardware handshaking interface is activated for the source or destination peripheral assign handshaking interface to the...

Page 336: ...all until it detects a write to the block complete interrupt clear register but starts the next block transfer immediately In this case software must clear the reload bits in the CFGx RELOAD_SR and CF...

Page 337: ...n and flow control peripheral by programming the TT_FC of the CTLx register b Set up the transfer characteristics such as i Transfer width for the source in the SRC_TR_WIDTH field ii Transfer width fo...

Page 338: ...memory is cleared 9 Clear any pending interrupts on the channel from the previous DMA transfer by writing to the Interrupt Clear registers ClearTfr ClearBlock ClearSrcTran ClearDstTran ClearErr Readin...

Page 339: ...block transfer immediately In this case software must clear the source reload bit CFGx RELOAD_SR to put the device into Row 1 of Table 19 1 on page 327 before the last block of the DMA transfer has c...

Page 340: ...I Fetch yes no no yes Hardware reprograms DARx CTLx LLPx DMAC block transfer Source destination status fetch Reload SARx Block Complete interrupt generated here DMAC Transfer Complete interrupt genera...

Page 341: ...r fixed address for destination in DINC field e Write the channel configuration information into the CFGx register for channel x i Designate the handshaking interface type hardware or software for the...

Page 342: ...he last block in the DMA transfer then the source reload bit should remain enabled to keep the DMACA in Row3 as shown in Table 19 1 on page 327 b If interrupts are disabled CTLx INT_EN 0 or the block...

Page 343: ...mory or non memory peripheral for source and desti nation and flow control device by programming the TT_FC of the CTLx register b Set up the transfer characteristics such as i Transfer width for the s...

Page 344: ...Make sure that the LLI SARx register location of all LLIs in memory point to the start source block address proceeding that LLI fetch 8 Make sure that the LLI CTLx DONE field of the LLI CTLx register...

Page 345: ...igure 19 17 on page 345 Note that the des tination address is decrementing Figure 19 17 DMA Transfer with Linked List Source Address and Contiguous Destination Address The DMA transfer flow is shown i...

Page 346: ...in conjunction with the FIFO_EMPTY bit in the Channel Configuration Register CFGx register 1 If software wishes to disable a channel prior to the DMA transfer completion then it can set the CFGx CH_S...

Page 347: ...nfirmed that the channel is disabled by reading back 0 A case where the channel is not be disabled after a chan nel disable request is where either the source or destination has received a split or re...

Page 348: ...09C Channel 1 Configuration Register High CFG1H Read Write 0x00000004 0x0A0 Channel 1Source Gather Register SGR1 Read Write 0x00000000 0x0A8 Channel 1 Destination Scatter Register DSR1 Read Write 0x00...

Page 349: ...r Read Write 0x00000000 0x338 Clear for IntTfr Interrupt ClearTfr Write only 0x00000000 0x340 Clear for IntBlock Interrupt ClearBlock Write only 0x00000000 0x348 Clear for IntSrcTran Interrupt ClearSr...

Page 350: ...fore the start of the DMA transfer As the DMA transfer is in progress this register is updated to reflect the source address of the current System Bus transfer Updated after each source System Bus tra...

Page 351: ...fore the start of the DMA transfer As the DMA transfer is in progress this register is updated to reflect the desti nation address of the current System Bus transfer Updated after each destination Sys...

Page 352: ...ed lists are NOT enabled This register must be programmed prior to enabling the channel in order to set up the transfer type It LLP LOC 0 contains the pointer to the next Linked Listed Item for block...

Page 353: ...source side if the LLP_SRC_EN field is high and LLPx LOC is non zero LLP_DST_EN Block chaining is only enabled on the destination side if the LLP_DST_EN field is high and LLPx LOC is non zero SMS Sour...

Page 354: ...control SRC_GATHER_EN Source Gather Enable 0 Gather disabled 1 Gather enabled Gather on the source side is applicable only when the CTLx SINC bit indicates an incrementing or decrementing address con...

Page 355: ...r device is fetching data from a source peripheral FIFO with a fixed address then set this field to No change DINC Destination Address Increment Indicates whether to increment or decrement the destina...

Page 356: ...A3 SRT_TR_WIDTH Source Transfer Width DSC_TR_WIDTH Destination Transfer Width INT_EN Interrupt Enable Bit If set then all five interrupt generating sources are enabled SRC_TR_WIDTH DST_TR_WIDTH Size b...

Page 357: ...user before the channel is enabled to indicate the block size The number programmed into BLOCK_TS indicates the total number of single transactions to perform for every block transfer unless the tran...

Page 358: ...ination Handshaking Interface Polarity 0 Active high 1 Active low HS_SEL_SRC Source Software or Hardware Handshaking Select This register selects which of the handshaking interfaces hardware or softwa...

Page 359: ...hannel 1 Channel s FIFO empty 0 Channel s FIFO not empty CH_SUSP Channel Suspend Suspends all DMA data transfers from the source until this bit is cleared There is no guarantee that the current transa...

Page 360: ...rect DMACA operation only one peripheral source or destination should be assigned to the same handshaking interface PROTCTL Protection Control Bits used to drive the System Bus HPROT 3 1 bus The Syste...

Page 361: ...ransaction requests are serviced when they occur Data pre fetching is enabled 1 Source transaction requests are not serviced until a destination transaction request occurs In this mode the amount of d...

Page 362: ...ce transfers of CTLx SRC_TR_WIDTH between successive gather intervals This is defined as a gather boundary SGI Source Gather Interval Specifies the source address increment decrement in multiples of C...

Page 363: ...tiguous destination transfers of CTLx DST_TR_WIDTH between successive scatter boundaries DSI Destination Scatter Interval Specifies the destination address increment decrement in multiples of CTLx DST...

Page 364: ...single burst transaction from the handshaking interface on the source side If the source for a channel is memory then that channel never generates a IntSrcTran interrupt and hence the correspond ing...

Page 365: ...Interrupt Status Registers before masking RawTfr RawBlock RawSrcTran RawDstTran RawErr Each Raw Interrupt Status register has a bit allocated per channel for example RawTfr 2 is Chan nel 2 s raw tran...

Page 366: ...re stored in these Interrupt Status Registers after masking StatusTfr StatusBlock StatusSrcTran StatusDstTran StatusErr Each Interrupt Status register has a bit allocated per channel for example Sta t...

Page 367: ...bit in the INT_MASK_WE field is asserted on the same System Bus write transfer This allows software to set a mask bit without performing a read modified write operation For example writing hex 01x1 to...

Page 368: ...s and Status registers is cleared on the same cycle by writing a 1 to the corresponding location in the Clear registers ClearTfr ClearBlock ClearSrcTran ClearDstTran ClearErr Each Interrupt Clear regi...

Page 369: ...StatusErr is OR ed to produce a single bit per interrupt type in the Combined Status Register StatusInt ERR OR of the contents of StatusErr Register DSTT OR of the contents of StatusDstTran Register S...

Page 370: ...rite enable bit in the REQ_WE field is asserted on the same System Bus write transfer For example writing 0x101 writes a 1 into ReqSrcReg 0 while ReqSrcReg 4 1 remains unchanged Writing hex 0x0yy leav...

Page 371: ...ndshaking is not enabled for the source of channel n A channel DST_REQ bit is written only if the corresponding channel write enable bit in the REQ_WE field is asserted on the same System Bus write tr...

Page 372: ...aking is not enabled for the source of channel n A channel S_SG_REQ bit is written only if the corresponding channel write enable bit in the REQ_WE field is asserted on the same System Bus write trans...

Page 373: ...king is not enabled for the source of channel n A channel D_SG_REQ bit is written only if the corresponding channel write enable bit in the REQ_WE field is asserted on the same System Bus write transf...

Page 374: ...e source of channel n A channel LSTSRC bit is written only if the corresponding channel write enable bit in the LSTSRC_WE field is asserted on the same System Bus write transfer LSTSRC_WE 11 8 Source...

Page 375: ...source of channel n A channel LSTDST bit is written only if the corresponding channel write enable bit in the LSTDST_WE field is asserted on the same System Bus write transfer LSTDST_WE 11 8 Destinati...

Page 376: ...e the DMACA which must be done before any channel activity can begin If the global channel enable bit is cleared while any channel is still active then DmaCfgReg DMA_EN still returns 1 to indi cate th...

Page 377: ...EnReg 7 1 remains unchanged CH_EN 3 0 0 Disable the Channel 1 Enable the Channel Enables Disables the channel Setting this bit enables a channel clearing this bit disables the channel The ChEnReg CH_E...

Page 378: ...110 DMA_COMP_TYPE DesignWare component type number 0x44571110 This assigned unique hex value is constant and is derived from the two ASCII letters DW followed by a 32 bit unsigned number 31 30 29 28 2...

Page 379: ...CompIdRegH Access Type Read only Offset 0x3FC Reset Value 0x3230362A DMA_COMP_VERSION Version of the component 31 30 29 28 27 26 25 24 DMA_COMP_VERSION 31 24 23 22 21 20 19 18 17 16 DMA_COMP_VERSION 2...

Page 380: ...are handshaking interface is connected to the input of the AES modulel Table 19 6 DMACA Handshake Interfaces PER Value Hardware Handshaking Interface 0 AES RX 1 AES TX 2 MCI RX 3 MCI TX 4 MSI RX 5 MSI...

Page 381: ...iew The General Purpose Input Output Controller manages the I O pins of the microcontroller Each I O line may be dedicated as a general purpose I O or be assigned to a function of an embedded peripher...

Page 382: ...enerated by the Power Manager This clock is enabled at reset and can be disabled in the Power Manager The CLK_GPIO must be enabled in order to access the configuration registers of the GPIO or to use...

Page 383: ...ster 1 PMR1 20 5 1 3 Output control When the I O line is assigned to a peripheral function i e the corresponding bit in GPER is writ ten to zero the drive of the I O line is controlled by the peripher...

Page 384: ...p resistor The pull up resistor can be enabled or disabled by writing a one or a zero to the corresponding bit in the Pull up Enable Register PUER Control of the pull up resistor is possible whether a...

Page 385: ...ngle interrupt signal to the interrupt controller The Interrupt Flag Register IFR can by read to determine which pin s caused the interrupt The interrupt bit must be cleared by writing a one to the In...

Page 386: ...hapter each GPIO line has a unique number Note that the PA PB PC and PX ports do not directly corre spond to the GPIO ports To find the corresponding port and pin the following formula can be used GPI...

Page 387: ...ER Read Write 1 0x44 Output Driver Enable Register Set ODERS Write Only 0x48 Output Driver Enable Register Clear ODERC Write Only 0x4C Output Driver Enable Register Toggle ODERT Write Only 0x50 Output...

Page 388: ...to one Again all bits written to zero remain unchanged Note that for some registers e g IFR not all access methods are permitted Note that for ports with less than 32 bits the corresponding control re...

Page 389: ...C Reset Value P0 P31 Pin Enable 0 A peripheral function controls the corresponding pin 1 The GPIO controls the corresponding pin 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19...

Page 390: ...Set Clear Toggle Offset 0x10 0x14 0x18 0x1C Reset Value P0 31 Peripheral Multiplexer Select bit 0 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P1...

Page 391: ...x24 0x28 0x2C Reset Value P0 31 Peripheral Multiplexer Select bit 1 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9...

Page 392: ...t Value P0 31 Output Driver Enable 0 The output driver is disabled for the corresponding pin 1 The output driver is enabled for the corresponding pin 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P2...

Page 393: ...8 0x5C Reset Value P0 31 Output Value 0 The value to be driven on the I O line is 0 1 The value to be driven on the I O line is 1 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19...

Page 394: ...line is at level 0 1 The I O line is at level 1 Note that the level of a pin can only be read when GPER is set or interrupt is enabled for the pin 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25...

Page 395: ...1 Pull up Enable 0 The internal pull up resistor is disabled for the corresponding pin 1 The internal pull up resistor is enabled for the corresponding pin 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27...

Page 396: ...9C Reset Value P0 31 Interrupt Enable 0 Interrupt is disabled for the corresponding pin 1 Interrupt is enabled for the corresponding pin 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 2...

Page 397: ...d Write Set Clear Toggle Offset 0xA0 0xA4 0xA8 0xAC Reset Value P0 31 Interrupt Mode Bit 0 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P...

Page 398: ...0xB8 0xBC Reset Value P0 31 Interrupt Mode Bit 1 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12...

Page 399: ...litch filter is enabled for the corresponding pin NOTE The value of this register should only be changed when IER is 0 Updating this GFER while interrupt on the corresponding pin is enabled can cause...

Page 400: ...ince reset or the last time it was cleared The number of interrupt request lines is dependant on the number of I O pins on the MCU Refer to the product specific data for details Note also that a bit i...

Page 401: ...this example that a subroutine delay exists that returns after a given time 20 7 2 Configuration of USART pins The example below shows how to configure a peripheral module to control I O pins It assum...

Page 402: ...00 orh R1 0x0003 st w R0 AVR32_GPIO_ODERC R1 Make the GPIO control the pins st w R0 AVR32_GPIO_GPERS R1 Select peripheral B on PC16 PC17 st w R0 AVR32_GPIO_PMR0S R1 st w R0 AVR32_GPIO_PMR1C R1 Enable...

Page 403: ...onnections section The reset values for all GPIO registers are zero with the following exceptions Table 20 2 Module configuration Feature GPIO Number of GPIO ports 4 Number of peripheral functions 4 T...

Page 404: ...Peripheral Interface is essentially a shift register that serially transmits data bits to other SPIs During a data transfer one SPI system acts as the master which controls the data flow while the oth...

Page 405: ...ck Diagram Single Master Multiple Slave Implementation Spi Interface Interrupt Control Peripheral DMA Controller I O Controller CLK_SPI Peripheral Bus SPI Interrupt SPCK NPCS3 NPCS2 NPCS1 NPCS0 NSS MO...

Page 406: ...aster mode or in slave mode Operation in master mode is configured by writing a one to the Master Slave Mode bit in the Mode Register MR MSTR The pins NPCS0 to NPCS3 are all configured as outputs the...

Page 407: ...s a master slave pair must use the same parameter pair values to com municate If multiple slaves are used and fixed in different configurations the master must reconfigure itself each time it needs to...

Page 408: ...e Shift Register to RDR the data in TDR is loaded in the Shift Register and a new transfer starts The transfer of a data written in TDR in the Shift Register is indicated by the Transmit Data Reg iste...

Page 409: ...red in the RDR the transfer is paused until the RDR is read In this mode no overrun error can occur Please note that if this mode is enabled it is useless to activate the FIFO in reception Figure 21 5...

Page 410: ...RF 1 TDRE NPCS 0xF Delay DLYBCS Fixed peripheral Variable peripheral Delay DLYBCT 0 1 CSAAT 0 TDRE 1 0 PS 0 1 TDR PCS NPCS no yes MR PCS NPCS no NPCS 0xF Delay DLYBCS NPCS TDR PCS NPCS 0xF Delay DLYBC...

Page 411: ...hange and consecutive transfers on the same chip select Three delays can be configured to modify the transfer waveforms The delay between chip selects programmable only once for all the chip selects b...

Page 412: ...the number of bits 8 to16 to be transferred through MISO and MOSI lines with the CSRn registers This is not the optimal means in term of memory size for the buffers but it provides a very effective me...

Page 413: ...e two transfers This might lead to difficulties for interfacing with some serial peripherals requiring the chip select to be de asserted after each transfer To facilitate interfacing with such devices...

Page 414: ...roller with either internal or external pullup resistors If the I O Controller does not have open drain capability mode fault detection must be disabled by writing a one to the Mode Fault Detection bi...

Page 415: ...the MOSI line When all the bits are processed the received data is transferred in the Receive Data Register and the SR RDRF bit rises If the RDR register has not been read before new data is received...

Page 416: ...012 AT32UC3A3 Figure 21 9 Slave Mode Functional Block Diagram Shift Register SPCK SPIENS LSB MSB NSS MOSI SPI Clock TDRE TDR TD RDRF OVRES CSR0 CPOL NCPHA BITS SPIEN SPIDIS MISO UNDES RDR RD 4 Charact...

Page 417: ...Write only 0x00000000 0x10 Status Register SR Read only 0x00000000 0x14 Interrupt Enable Register IER Write only 0x00000000 0x18 Interrupt Disable Register IDR Write only 0x00000000 0x1C Interrupt Mas...

Page 418: ...set the SPI A software triggered hardware reset of the SPI interface is performed The SPI is in slave mode after software reset Peripheral DMA Controller channels are not affected by software reset 0...

Page 419: ...is only used if Fixed Peripheral Select is active PS 0 If PCSDEC 0 PCS xxx0NPCS 3 0 1110 PCS xx01NPCS 3 0 1101 PCS x011NPCS 3 0 1011 PCS 0111NPCS 3 0 0111 PCS 1111forbidden no peripheral is selected...

Page 420: ...of the SPI 0 Mode fault detection is enabled PCSDEC Chip Select Decode 0 The chip selects are directly connected to a peripheral device 1 The four chip select lines are connected to a 4 to 16 bit deco...

Page 421: ...Access Type Read only Offset 0x08 Reset Value 0x00000000 RD Receive Data Data received by the SPI Interface is stored in this register right justified Unused bits read zero 31 30 29 28 27 26 25 24 23...

Page 422: ...This field is only used if Variable Peripheral Select is active MR PS 1 PCS Peripheral Chip Select If PCSDEC 0 PCS xxx0NPCS 3 0 1110 PCS xx01NPCS 3 0 1101 PCS x011NPCS 3 0 1011 PCS 0111NPCS 3 0 0111 P...

Page 423: ...Status 1 This bit is set when an overrun has occurred An overrun occurs when RDR is loaded at least twice from the serializer since the last read of the RDR 0 This bit is cleared when the SR register...

Page 424: ...ly Offset 0x14 Reset Value 0x00000000 Writing a zero to a bit in this register has no effect Writing a one to a bit in this register will set the corresponding bit in IMR 31 30 29 28 27 26 25 24 23 22...

Page 425: ...ly Offset 0x18 Reset Value 0x00000000 Writing a zero to a bit in this register has no effect Writing a one to a bit in this register will clear the corresponding bit in IMR 31 30 29 28 27 26 25 24 23...

Page 426: ...terrupt is disabled 1 The corresponding interrupt is enabled A bit in this register is cleared when the corresponding bit in IDR is written to one A bit in this register is set when the corresponding...

Page 427: ...CK clock period Otherwise the following equations determine the delay SCBR Serial Clock Baud Rate In Master Mode the SPI Interface uses a modulus counter to derive the SPCK baud rate from the CLK_SPI...

Page 428: ...n each transfer performed on the same slave for a minimal duration of if DLYBCT field is different from 0 if DLYBCT field equals 0 NCPHA Clock Phase 1 Data is captured after the leading inactive to ac...

Page 429: ...72H AVR32 10 2012 AT32UC3A3 CPOL is used to determine the inactive state value of the serial clock SPCK It is used with NCPHA to produce the required clock data relationship between master and slave d...

Page 430: ...CK clock period Otherwise the following equations determine the delay SCBR Serial Clock Baud Rate In Master Mode the SPI Interface uses a modulus counter to derive the SPCK baud rate from the CLK_SPI...

Page 431: ...n each transfer performed on the same slave for a minimal duration of if DLYBCT field is different from 0 if DLYBCT field equals 0 NCPHA Clock Phase 1 Data is captured after the leading inactive to ac...

Page 432: ...72H AVR32 10 2012 AT32UC3A3 CPOL is used to determine the inactive state value of the serial clock SPCK It is used with NCPHA to produce the required clock data relationship between master and slave d...

Page 433: ...CK clock period Otherwise the following equations determine the delay SCBR Serial Clock Baud Rate In Master Mode the SPI Interface uses a modulus counter to derive the SPCK baud rate from the CLK_SPI...

Page 434: ...n each transfer performed on the same slave for a minimal duration of if DLYBCT field is different from 0 if DLYBCT field equals 0 NCPHA Clock Phase 1 Data is captured after the leading inactive to ac...

Page 435: ...72H AVR32 10 2012 AT32UC3A3 CPOL is used to determine the inactive state value of the serial clock SPCK It is used with NCPHA to produce the required clock data relationship between master and slave d...

Page 436: ...CK clock period Otherwise the following equations determine the delay SCBR Serial Clock Baud Rate In Master Mode the SPI Interface uses a modulus counter to derive the SPCK baud rate from the CLK_SPI...

Page 437: ...n each transfer performed on the same slave for a minimal duration of if DLYBCT field is different from 0 if DLYBCT field equals 0 NCPHA Clock Phase 1 Data is captured after the leading inactive to ac...

Page 438: ...72H AVR32 10 2012 AT32UC3A3 CPOL is used to determine the inactive state value of the serial clock SPCK It is used with NCPHA to produce the required clock data relationship between master and slave d...

Page 439: ...If a value is written in SPIWPEN the value is taken into account only if SPIWPKEY is written with SPI SPI written in ASCII Code i e 0x535049 in hexadecimal SPIWPEN SPI Write Protection Enable 1 The Wr...

Page 440: ...Type Read only Offset 0xE8 Reset Value 0x00000000 SPIWPVSRC SPI Write Protection Violation Source This Field indicates the Peripheral Bus Offset of the register concerned by the violation MR or CSRx 3...

Page 441: ...read 5 The Write Protection has blocked a Write access to a protected register and write accesses have been detected on MR while a chip select was active or on CSRi while the Chip Select i was active...

Page 442: ...VERSION Access Type Read only Offset 0xFC Reset Value MFN Reserved No functionality associated VERSION Version number of the module No functionality associated 31 30 29 28 27 26 25 24 23 22 21 20 19 1...

Page 443: ...listed in the following tables The module bus clocks listed here are connected to the system bus clocks Please refer to the Power Manager section for details Table 21 4 Module Clock Name Module Name...

Page 444: ...w The Atmel Two wire Slave Interface TWIS interconnects components on a unique two wire bus made up of one clock line and one data line with speeds of up to 400 kbit s based on a byte oriented transfe...

Page 445: ...Standard SMBus Standard Atmel TWIS Bus Timeouts Supported Address Resolution Protocol Supported Alert Supported Packet Error Checking Supported Table 22 3 Abbreviations Abbreviation Description TWI Tw...

Page 446: ...n col lector to perform the wired AND function TWALM is used to implement the optional SMBus SMBALERT signal TWALM TWD and TWCK pins may be multiplexed with I O Controller lines To enable the TWIS the...

Page 447: ...nterrupt controller Using the TWIS inter rupts requires the interrupt controller to be programmed first 22 7 6 Debug Operation When an external debugger forces the CPU into debug mode the TWIS continu...

Page 448: ...iagram 22 8 2 1 Bus Timing The Timing Register TR is used to control the timing of bus signals driven by the TWIS TR describes bus timings as a function of cycles of the prescaled CLK_TWIS The clock p...

Page 449: ...er of bytes to transfer and which addresses to match The interrupt system can be set up to generate interrupt request on specific events or error con ditions for example when a byte has been received...

Page 450: ...d set SR URUN Module is in slave receiver mode a byte has been received and placed into the internal shifter but RHR is full Discard the received byte and set SR ORUN 22 8 2 5 Bus Errors If a bus erro...

Page 451: ...ust not be cleared before the SR BTF bit is set to ensure correct TWIS behavior 6 If STOP is received SR TCOMP and SR STO will be set 7 If REPEATED START is received SR REP will be set The TWI transfe...

Page 452: ...is written to one NBYTES is incremented otherwise NBYTES is decremented NBYTES is usually configured to count downwards if PEC is used 4 After a data byte has been received the slave transmits an ACK...

Page 453: ...BYTES is incremented by one each time a data has been transmitted or received This allows the user to detect how much data was actually transferred by the DMA system To assure correct behavior respect...

Page 454: ...r calculates a PEC value and transmits it to the slave after all data bytes have been transmitted Upon reception of this PEC byte the slave will compare it to the PEC value it has computed itself If t...

Page 455: ...ave enters appropriate transfer direction mode and data transfer can commence Start Sadr on bus current slave is addressed corresponding address match enable bit in CR set SR STREN and SR SOAM are set...

Page 456: ...tten to bus SR URUN is set SMBus timeout received SR SMBTOUT is set TWCK and TWD are immediately released Slave transmitter in SMBus PEC mode has transmitted a PEC byte that was not identical to the P...

Page 457: ...00000 0x08 Timing Register TR Read Write 0x00000000 0x0C Receive Holding Register RHR Read only 0x00000000 0x10 Transmit Holding Register THR Write only 0x00000000 0x14 Packet Error Check Register PEC...

Page 458: ...the ACK cycle of the data phase in slave receiver mode PECEN Packet Error Checking Enable 0 Disables SMBus PEC CRC generation and check 1 Enables SMBus PEC CRC generation and check SMHH SMBus Host Hea...

Page 459: ...mpty GCMATCH General Call Address Match 0 Causes the TWIS not to acknowledge the General Call Address 1 Causes the TWIS to acknowledge the General Call Address SMATCH Slave Address Match 0 Causes the...

Page 460: ...x00000000 NBYTES Number of Bytes to Transfer Writing to this field updates the NBYTES counter The field can also be read to learn the progress of the transfer NBYTES can be incremented or decremented...

Page 461: ...ock cycles for data setup count Used to time TSU_DAT Data is driven SUDAT cycles after TWCK low detected This timing is used for timing the ACK NAK bits and any data bits driven in slave transmitter m...

Page 462: ...cess Type Read only Offset 0x0C Reset Value 0x00000000 RXDATA Received Data Byte When the RXRDY bit in the Status Register SR is one this field contains a byte received from the TWI bus 31 30 29 28 27...

Page 463: ...lding Register Name THR Access Type Write only Offset 0x10 Reset Value 0x00000000 TXDATA Data Byte to Transmit Write data to be transferred on the TWI bus here 31 30 29 28 27 26 25 24 23 22 21 20 19 1...

Page 464: ...tomatically by hardware after each byte has been transferred Reset by hardware after a STOP condition Provided if the user manually wishes to control when the PEC byte is transmitted or wishes to acce...

Page 465: ...en the corresponding bit in SCR is written to one This bit is set when the received address matched the SMBus Host Header Address SMBALERTM SMBus Alert Response Address Match This bit is cleared when...

Page 466: ...n slave receiver mode Can only occur if CR STREN is zero URUN Underrun This bit is cleared when the corresponding bit in SCR is written to one This bit is set when an underrun has occurred in slave tr...

Page 467: ...0 Writing a zero to a bit in this register has no effect Writing a one to a bit in this register will write a one to the corresponding bit in IMR 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 BTF RE...

Page 468: ...000000 Writing a zero to a bit in this register has no effect Writing a one to a bit in this register will clear the corresponding bit in IMR 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 BTF REP ST...

Page 469: ...led 1 The corresponding interrupt is enabled This bit is cleared when the corresponding bit in IDR is written to one This bit is set when the corresponding bit in IER is written to one 31 30 29 28 27...

Page 470: ...a zero to a bit in this register has no effect Writing a one to a bit in this register will clear the corresponding bit in SR and the corresponding interrupt request 31 30 29 28 27 26 25 24 23 22 21 2...

Page 471: ...71 32072H AVR32 10 2012 AT32UC3A3 22 9 12 Parameter Register Name PR Access Type Read only Offset 0x2C Reset Value 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0...

Page 472: ...only Offset 0x30 Reset Value VARIANT Variant Number Reserved No functionality associated VERSION Version Number Version number of the module No functionality associated 31 30 29 28 27 26 25 24 23 22 2...

Page 473: ...ted in the following tables The module bus clocks listed here are connected to the system bus clocks according to the table in the Power Manager section Table 22 7 Module Clock Name Module name Clock...

Page 474: ...e oriented transfer format It can be used with any Atmel Two wire Interface bus serial EEPROM and I C compatible device such as a real time clock RTC dot matrix graphic LCD controller and temperature...

Page 475: ...SMBus Standard Atmel TWIM Bus Timeouts Supported Address Resolution Protocol Supported Alert Supported Host Functionality Supported Packet Error Checking Supported Table 23 3 Abbreviations Abbreviatio...

Page 476: ...BALERT signal The TWALM TWD and TWCK pins may be multiplexed with I O Controller lines To enable the TWIM the user must perform the following steps Program the I O Controller to Dedicate TWD TWCK and...

Page 477: ...troller Using the TWIM DMA functionality requires the Peripheral DMA Controller to be programmed after setting up the TWIM 23 7 5 Interrupts The TWIM interrupt request lines are connected to the inter...

Page 478: ...igure 23 4 A high to low transition on the TWD line while TWCK is high defines the START condition A low to high transition on the TWD line while TWCK is high defines a STOP condition Figure 23 3 STAR...

Page 479: ...hold count Used to time THD_DAT TSU_DAT EXP Specifies the clock prescaler setting Note that the total clock low time generated is the sum of THD_DAT TSU_DAT TLOW Any slave or other bus master taking...

Page 480: ...ll have to restart the transmission by clearing the error bits in SR after resolving the cause for the NACK After a data or address NACK from the slave a STOP will be transmitted automatically Note th...

Page 481: ...Figure 23 7 Master Write with Multiple Data Bytes 23 8 4 Master Receiver Mode A START condition is transmitted and master receiver mode is initiated when the bus is free and CMDR has been written with...

Page 482: ...uire the master to acknowledge each received data byte During the acknowledge clock pulse 9th pulse the slave releases the data line HIGH enabling the mas ter to pull it down in order to generate the...

Page 483: ...TWIM ADR NBYTES etc 3 Start the transfer by enabling the Peripheral DMA Controller to receive 4 Wait for the Peripheral DMA Controller end of receive flag 5 Disable the Peripheral DMA Controller 23 8...

Page 484: ...receiver mode the CMDR ACKLAST bit must also be controlled TWCK TWD DATA sent by a master STOP sent by the master START sent by the TWI DATA sent by the TWI Bus is busy Bus is free A transfer is prog...

Page 485: ...byte to transfer to THR 6 Wait until SR TXRDY 1 then write fourth data byte to transfer to THR 23 8 7 2 Read Followed by Read Consider the following transfer START DADR R DATA A DATA NA REPSTART DADR...

Page 486: ...DADR R DATA A DATA NA REPSTART DADR W DATA A DATA A STOP Figure 23 13 Combining a Read and Write Transfer To generate this transfer 1 Write CMDR with START 1 STOP 0 DADR NBYTES 2 and READ 1 2 Write N...

Page 487: ...ave for reads using 10 bit addressing To perform a master receiver transfer 1 Write CMDR with TENBIT 1 REPSAME 0 READ 0 START 1 STOP 0 NBYTES 0 and the desired address 2 Write NCMDR with TENBIT 1 REPS...

Page 488: ...e it to the PEC value it has computed itself If the values match the data was received correctly If the PEC values differ data was corrupted and SR PECERR is set In master receiver mode the PEC byte i...

Page 489: ...t set CMDR VALID remains set STOP automatically transmitted on bus Arbitration lost SR ARBLST is set SR CCOMP not set CMDR VALID remains set TWCK and TWD immediately released to a pulled up state SMBu...

Page 490: ...ming Register SMBTR Read Write 0x00000000 0x0C Command Register CMDR Read Write 0x00000000 0x10 Next Command Register NCMDR Read Write 0x00000000 0x14 Receive Holding Register RHR Read only 0x00000000...

Page 491: ...ransfers are halted immediately possibly violating the bus semantics If the TWIM master interface is not enabled it must first be enabled before writing a one to this bit Writing a zero to this bit ha...

Page 492: ...tup and hold count Prescaled by CWGR EXP Used to time THD_DAT TSU_DAT STASTO START and STOP Cycles Clock cycles in clock high count Prescaled by CWGR EXP Used to time THD_STA TSU_STA TSU_STO HIGH Cloc...

Page 493: ...escaled by SMBTR EXP Used for bus free detection Used to time THIGH MAX NOTE Uses the prescaler specified by CWGR NOT the prescaler specified by SMBTR TLOWM Master Clock Stretch Maximum Cycles Clock c...

Page 494: ...bytes in the transfer After the specified number of bytes have been transferred a STOP condition is transmitted if CMDR STOP is one In SMBus mode if PEC is used NBYTES includes the PEC byte i e there...

Page 495: ...receiver mode Write this bit to zero otherwise TENBIT Ten Bit Addressing Mode 0 Use 7 bit addressing mode 1 Use 10 bit addressing mode Must not be used when the TWIM is in SMBus mode SADR Slave Addres...

Page 496: ...R When the VALID bit in CMDR becomes 0 the content of NCMDR is copied into CMDR clearing the VALID bit in NCMDR If the VALID bit in CMDR is cleared when NCMDR is written the content is copied immediat...

Page 497: ...Access Type Read only Offset 0x14 Reset Value 0x00000000 RXDATA Received Data When the RXRDY bit in the Status Register SR is one this field contains a byte received from the TWI bus 31 30 29 28 27 26...

Page 498: ...Holding Register Name THR Access Type Write only Offset 0x18 Reset Value 0x00000000 TXDATA Data to Transmit Write data to be transferred on the TWI bus here 31 30 29 28 27 26 25 24 23 22 21 20 19 18...

Page 499: ...ting 1 to the corresponding bit in the Status Clear Register SCR ARBLST Arbitration Lost This bit is one when the actual state of the SDA line did not correspond to the data driven onto it indicating...

Page 500: ...lave This bit is cleared by writing 1 to the corresponding bit in the Status Clear Register SCR CRDY Ready for More Commands This bit is one when CMDR and or NCMDR is ready to receive one or more comm...

Page 501: ...set Value 0x00000000 Writing a zero to a bit in this register has no effect Writing a one to a bit in this register will set the corresponding bit in IMR 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 1...

Page 502: ...set Value 0x00000000 Writing a zero to a bit in this register has no effect Writing a one to a bit in this register will clear the corresponding bit in IMR 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17...

Page 503: ...rupt is disabled 1 The corresponding interrupt is enabled This bit is cleared when the corresponding bit in IDR is written to one This bit is set when the corresponding bit in IER is written to one 31...

Page 504: ...0x00000000 Writing a zero to a bit in this register has no effect Writing a one to a bit in this register will clear the corresponding bit in SR and the corresponding interrupt request 31 30 29 28 27...

Page 505: ...5 32072H AVR32 10 2012 AT32UC3A3 23 9 13 Parameter Register PR Name PR Access Type Read only Offset 0x30 Reset Value 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1...

Page 506: ...only Offset 0x34 Reset Value VARIANT Variant Number Reserved No functionality associated VERSION Version Number Version number of the module No functionality associated 31 30 29 28 27 26 25 24 23 22 2...

Page 507: ...ted in the following tables The module bus clocks listed here are connected to the system bus clocks according to the table in the Power Manager section Table 23 7 Module Clock Name Module name Clock...

Page 508: ...ation protocols generally used in audio and telecom applications such as I2S Short Frame Sync Long Frame Sync etc The SSC consists of a receiver a transmitter and a common clock divider Both the recei...

Page 509: ...erface Peripheral DMA Controller Peripheral Bus Bridge High Speed Bus Peripheral Bus Power Manager CLK_SSC I O Controller Interrupt Control SSCInterrupt TX_FRAME_SYNC RX_FRAME_SYNC TX_CLOCK RX_CLOCK R...

Page 510: ...the interrupt controller to be programmed first 24 7 Functional Description This chapter contains the functional description of the following SSC functional block clock management data framing format...

Page 511: ...llows the SSC to support many Master and Slave Mode data transfers Clock Divider User Interface Peripheral Bus CLK_SSC Interrupt Control Start Selector Receive Shift Register Receive Holding Register...

Page 512: ...f the divided clock has a duration of the peripheral clock multiplied by CMR DIV This ensures a 50 duty cycle for the divided clock regardless of whether the CMR DIV value is even or odd Figure 24 5 D...

Page 513: ...clock the divider clock or an external clock scanned on the RX_CLOCK pin The receive clock is selected by writing to the Receive Clock Selection field in the Receive Clock Mode Register RCMR CKS The r...

Page 514: ...ata before data transmission The start event is configured by writing to the TCMR register See Section 24 7 4 The frame synchronization is configured by writing to the Transmit Frame Mode Register TFM...

Page 515: ...ter The data is transferred from the shift register depending on the data format selected When the receiver shift register is full the SSC transfers this data in the Receive Holding Regis ter RHR the...

Page 516: ...of a low high level on TX_FRAME_SYNC RX_FRAME_SYNC On detection of a level change or an edge on TX_FRAME_SYNC RX_FRAME_SYNC A start can be programmed in the same manner on either side of the Transmit...

Page 517: ...utput Start High Level on TX_FRAME_SYNC TX_DATA Output Start Low Level on TX_FRAME_SYNC TX_FRAME_SYNC Input TX_CLOCK Input STTDLY STTDLY STTDLY STTDLY STTDLY STTDLY RX_CLOCK RX_FRAME_SYNC Input RX_DAT...

Page 518: ...g the Frame Sync signal the receiver can sample the RX_DATA line and store the data in the Receive Sync Holding Register RSHR and the transmitter can transfer the Transmit Sync Holding Register TSHR i...

Page 519: ...n independently select the event that starts the data transfer RCMR START and TCMR START the delay in number of bit periods between the start event and the first data bit RCMR STTDLY and TCMR STTDLY t...

Page 520: ...EN Up to 256 Size of Synchro data register TFMR RFMR MSBF Most significant bit first TFMR FSDEN Enable send TSHR TFMR DATDEF Data default value ended Table 24 3 Data Framing Format Registers Transmitt...

Page 521: ...s The SSC can be programmed to generate an interrupt when it detects an event The interrupt is controlled by writing to the Interrupt Enable Register IER and Interrupt Disable Register IDR These regis...

Page 522: ...7 Audio Application Block Diagram Figure 24 18 Codec Application Block Diagram Clock SCK Word Select WS Data SD MSB Left Channel LSB MSB Right Channel Data SD Word Select WS Clock SCK SSC TX_CLOCK TX_...

Page 523: ...Block Diagram CODEC First Time Slot CODEC Second Time Slot Data in Data Out FSYNC SCLK Serial Data Clock SCLK Frame sync FSYNC Serial Data Out Serial Data In Dstart First Time Slot Second Time Slot D...

Page 524: ...Mode Register TFMR Read Write 0x00000000 0x20 Receive Holding Register RHR Read only 0x00000000 0x24 Transmit Holding Register THR Write only 0x00000000 0x30 Receive Synchronization Holding Register...

Page 525: ...0 Writing a zero to this bit has no effect TXEN Transmit Enable 1 Writing a one to this bit will enable the transmission if the TXDIS bit is not written to one 0 Writing a zero to this bit has no effe...

Page 526: ...Divider The divided clock equals the CLK_SSC divided by two times DIV The maximum bit rate is CLK_SSC 2 The minimum bit rate is CLK_SSC 2 x 4095 CLK_SSC 8190 The clock divider is not active when DIV...

Page 527: ...between the start event and the actual start of reception When the receiver is programmed to start synchronously with the transmitter the delay is also applied Note It is very important that STTDLY be...

Page 528: ...bled and immediately after the end of transfer of the previous data 1 Transmit start 2 Detection of a low level on RX_FRAME_SYNC signal 3 Detection of a high level on RX_FRAME_SYNC signal 4 Detection...

Page 529: ...ed data to be compared to the Compare 0 or Compare 1 register Note The four most significant bits for this field are located in the FSLENHI field The pulse length is equal to FSLENHI FSLEN 1 receive c...

Page 530: ...bit of the data register is sampled first in the bit stream LOOP Loop Mode 1 RX_DATA is driven by TX_DATA RX_FRAME_SYNC is driven by TX_FRAME_SYNC and TX_CLOCK drives RX_CLOCK 0 Normal operating mode...

Page 531: ...start synchronously with the receiver the delay is also applied Note STTDLY must be written carefully in relation to Transmit Sync Data transmission START Transmit Start Selection 31 30 29 28 27 26 25...

Page 532: ...transmit clock falling edge The Frame sync signal input is sampled on transmit clock rising edge CKO Transmit Clock Output Mode Selection CKS Transmit Clock Selection CKG Transmit Clock Gating 0 None...

Page 533: ...ion FSLEN Transmit Frame Sync Length This field defines the length of the Transmit Frame Sync signal and the number of bits shifted out from the TSHR register if TFMR FSDEN is equal to one Note The fo...

Page 534: ...ata register is shifted out first in the bit stream DATDEF Data Default Value This bit defines the level driven on the TX_DATA pin while out of transmission Note that if the pin is defined as multi dr...

Page 535: ...s Type Read only Offset 0x20 Reset value 0x00000000 RDAT Receive Data Right aligned regardless of the number of data bits defined by the RFMR DATLEN field 31 30 29 28 27 26 25 24 RDAT 31 24 23 22 21 2...

Page 536: ...Type Write only Offset 0x24 Reset value 0x00000000 TDAT Transmit Data Right aligned regardless of the number of data bits defined by the TFMR DATLEN field 31 30 29 28 27 26 25 24 TDAT 31 24 23 22 21...

Page 537: ...ive Synchronization Holding Register Name RSHR Access Type Read only Offset 0x30 Reset value 0x00000000 RSDAT Receive Synchronization Data 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 1...

Page 538: ...mit Synchronization Holding Register Name TSHR Access Type Read Write Offset 0x34 Reset value 0x00000000 TSDAT Transmit Synchronization Data 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12...

Page 539: ...24 9 11 Receive Compare 0 Register Name RC0R Access Type Read Write Offset 0x38 Reset value 0x00000000 CP0 Receive Compare Data 0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8...

Page 540: ...24 9 12 Receive Compare 1 Register Name RC1R Access Type Read Write Offset 0x3C Reset value 0x00000000 CP1 Receive Compare Data 1 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8...

Page 541: ...hen compare 1 has occurred This bit is cleared when the SR register is read CP0 Compare 0 This bit is set when compare 0 has occurred This bit is cleared when the SR register is read OVRUN Receive Ove...

Page 542: ...2H AVR32 10 2012 AT32UC3A3 TXRDY Transmit Ready This bit is set when the THR register is empty This bit is cleared when data has been loaded in the THR register and is waiting to be loaded in the TSR...

Page 543: ...Offset 0x44 Reset value 0x00000000 Writing a zero to a bit in this register has no effect Writing a one to a bit in this register will set the corresponding bit in IMR 31 30 29 28 27 26 25 24 23 22 2...

Page 544: ...Offset 0x48 Reset value 0x00000000 Writing a zero to a bit in this register has no effect Writing a one to a bit in this register will clear the corresponding bit in IMR 31 30 29 28 27 26 25 24 23 22...

Page 545: ...rupt is disabled 1 The corresponding interrupt is enabled A bit in this register is cleared when the corresponding bit in IDR is written to one A bit in this register is set when the corresponding bit...

Page 546: ...ernal clock frequency LIN Mode Compliant with LIN 1 3 and LIN 2 0 specifications Master or slave Processing of Frames with up to 256 data bytes Configurable response data length optionally defined aut...

Page 547: ...are handshaking feature enables an out of band flow control automatically managing RTS and CTS pins The Peripheral DMA Con troller connection enables memory transactions and the USART supports chained...

Page 548: ...implemented on the USART On USARTs not equipped with the corresponding pins the associated control bits and statuses have no effect on the behavior of the USART Table 25 1 SPI Operating Mode PIN USART...

Page 549: ...abled at reset and can be disabled in the Power Manager It is recommended to dis able the USART before disabling the clock to avoid freezing the USART in an undefined state 25 5 3 Interrupts The USART...

Page 550: ...selected by writing to the Mode field in the Mode Register MR MODE In addition Synchronous or Asynchronous mode is selected by writing to the Synchronous Mode Select bit in MR MR SYNC By default MR M...

Page 551: ...ually in both Synchronous and Asynchronous operating modes MR SYNC One start bit up to 9 data bits an optional parity bit and up to two stop bits are successively shifted out on the TXD pin at each fa...

Page 552: ...cted by the same bits and fields as for the transmitter MR CHRL MR MODE9 MR MSBF MR PAR and MR NBSTOP The synchronization mechanism will only consider one stop bit regardless of the used protocol and...

Page 553: ...t is transferred to the Received Character field in the Receive Holding Register RHR RXCHR and the Receiver Ready bit in the Channel Status Register CSR RXRDY is set An interrupt request is generated...

Page 554: ...par ity is selected MR PAR is 0x0 the parity bit will be zero if there is an even number of ones in the data character and one if there is an odd number For odd parity the reverse applies If space or...

Page 555: ...bit whose duration is selected by the Timeguard Value field in the Transmitter Timeguard Register TTGR TG The transmitter will hold the TXD line high for TTGR TG bit periods in addition to the number...

Page 556: ...ated if the Receiver Time out bit in the Interrupt Mask Register IMR TIMEOUT is set Clearing TIMEOUT can be done in two ways Writing a one to the Start Time out bit CR STTTO This also aborts count dow...

Page 557: ...RK The break is treated as a nor mal 0x00 character transmission clearing CSR TXRDY and CSR TXEMPTY but with zeroes for preambles start parity stop and time guard bits Writing a one to the Stop Break...

Page 558: ...s one the divider is bypassed and inactive The Clock Selection field in the Mode Register MR USCLKS selects clock source between CLK_USART internal clock refer to Power Manager chapter for details CLK...

Page 559: ...f the reference source clock This fractional part is selected with Table 25 7 Baud Rate Example OVER 0 Source Clock Hz ExpectedBaud Rate bit s Calculation Result CD Actual Baud Rate bit s Error 3 686...

Page 560: ...n the system clock and when either CLK or CLK_USART DIV are selected BRGR CD must be even to ensure a 50 50 duty cycle If CLK_USART is selected the generator ensures this regardless of value 25 6 5 RS...

Page 561: ...6 6 Hardware Handshaking The USART features an out of band hardware handshaking flow control mechanism imple mentable by connecting the RTS and CTS pins with the remote device as shown in Figure 25 17...

Page 562: ...e 25 18 illustrates receiver functionality and Figure 25 19 illustrates transmitter functionality Figure 25 18 Receiver Behavior when Operating with Hardware Handshaking Figure 25 19 Transmitter Behav...

Page 563: ...MR MODE 25 6 8 1 ISO7816 Mode Overview ISO7816 specifies half duplex communication on one bidirectional line The baud rate is a frac tion of the clock provided by the master on the CLK pin see Baud Ra...

Page 564: ...d off to an integral so the user has to select a FI_DI_RATIO value that comes as close as possible to the expected Fi Di ratio The FI_DI_RATIO reset value is 0x174 372 in decimal and is the most commo...

Page 565: ...T 1 In T 1 protocol the character resembles an asynchronous format with only one stop bit The parity is generated when transmitting and checked when receiving Parity errors set PARE 25 6 8 5 Receive E...

Page 566: ...ad be accepted as valid and CSR ITER is set 25 6 9 IrDA Mode The USART features an IrDA mode supporting asynchronous half duplex point to point wire less communication It embeds the modulator and demo...

Page 567: ...mples of BRGR CD values baud rate error and pulse duration Note that the maximal acceptable error rate of 1 87 must be met Table 25 12 IrDA Pulse Duration Baud Rate Pulse Duration 3 16 2 4 Kbit s 78 1...

Page 568: ...terconnect Network LIN 1 3 and 2 0 compliant mode embed ding full error checking and reporting automatic frame processing with up to 256 data bytes customizable response data lengths and requiring min...

Page 569: ...t The Break field consists of 13 dominant bits the break and one recessive bit the break delim iter The Sync field consists of a start bit the Sync byte the character 0x55 and a stop bit refer to Figu...

Page 570: ...most significant bits counter value divided by 8 becomes the new clock divider BRGR CD and the three least significant bits the remainder becomes the new fractional part BRGR FP Figure 25 30 Slave Nod...

Page 571: ...the fractional part is not used the synchronization accuracy is much lower The 16 most signif icant bits added with the first least significant bit becomes the new clock divider CD The equation of th...

Page 572: ...in a small LIN cluster Response from master to slave1 Master NACT PUBLISH Slave1 NACT SUBSCRIBE Slave2 NACT IGNORE Response from slave1 to master Master NACT SUBSCRIBE Slave1 NACT PUBLISH Slave2 NACT...

Page 573: ...25 6 10 12 Frame Slot Mode A LIN master can be configured to use frame slots with a pre defined minimum length This Frame Slot mode is enabled by default and is disabled by writing a one to the Frame...

Page 574: ...ror CSR LINSNRE This error is generated if no valid message appears within the TFrame_Maximum time frame slot while the USART is expecting a response from another node NACT SUBSCRIBE Checksum Error CS...

Page 575: ...ck for LIN errors Case 2 LINMR NACT is 0x1 SUBSCRIBE the USART receives the response Wait until CSR RXRDY is one Read RHR RXCHR Repeat the two previous steps until there is no more data to read Wait u...

Page 576: ...errors clear errors and CSR LINIR by writing a one to CR RSTSTA Read LINIR IDCHR IMPORTANT If LINMR NACT is 0x0 PUBLISH and this field is already correct the LINMR register must still be written with...

Page 577: ...ontroller The USART can be used together with the Peripheral DMA Controller in order to transfer data without processor intervention The Peripheral DMA Controller uses the CSR TXRDY and Break Synch Pr...

Page 578: ...e buffer Since data transfer size is a byte the transfer is split into two accesses The first writes the NACT PARDIS CHKDIS CHKTYP DLM and FSDIS bits in the LINMR register while the second writes the...

Page 579: ...Request Any node in a sleeping LIN cluster may request a wake up By writing to the Wakeup Signal Type bit LINMR WKUPTYP the user can choose to send either a LIN 1 3 WKUPTYP is one or a LIN 2 0 WKUPTYP...

Page 580: ...ti master protocol and one master may shift data simultaneously into several slaves but only one slave may respond at a time A slave is selected when its slave select NSS signal has been raised by the...

Page 581: ...TXD pin at each edge There are no start parity or stop bits and MSB is always sent first The SPI Clock Polarity MR CPOL and SPI Clock Phase MR CPHA bits configure CLK by selecting the edges upon whic...

Page 582: ...ways inserted in between characters In order to address slave devices supporting the Chip Select Active After Transfer CSAAT mode NSS can be forced low by writing a one to the Force SPI Chip Select bi...

Page 583: ...r II Biphase format Depending on polarity configuration selected by the Transmission Manchester Polarity bit in the Manchester Configuration Register MAN TX_MOPL a logic level zero or one is transmitt...

Page 584: ...bit MR MODSYNC selects sync pattern and this also defines if the character is data MODSYNC 0 with a zero to one transition or a command MODSYNC 1 with a one to zero transition When direct memory acce...

Page 585: ...he Manchester decoder can detect selectable preamble sequences and start frame delimiters The Receiver Manchester Polarity bit in the Manchester Configuration Register MAN RX_MPOL selects input stream...

Page 586: ...imiter is detected the receiver continues decoding with the same synchronization If a non valid preamble pattern or a start frame delimiter is detected the receiver re synchronizes at the next valid e...

Page 587: ...ction with the RF module and may sometimes be filtered away from the endec stream Using the ASK modulation scheme a one is transmitted as an RF signal at the down stream frequency while a zero is tran...

Page 588: ...to a transmitter TXD pin Figure 25 54 Normal Mode Configuration 25 6 17 2 Automatic Echo Mode Automatic echo mode allows bit by bit retransmission When a bit is received on the RXD pin it is also sen...

Page 589: ...e state Figure 25 56 Local Loopback Mode Configuration 25 6 17 4 Remote Loopback Mode Remote loopback mode connects the RXD pin to the TXD pin as shown in Figure 25 57 The transmitter and the receiver...

Page 590: ...put Change Flag A change has been detected on the DCD pin DSRIC Data Set Ready Input Change Flag A change has been detected on the DSR pin RIIC Ring Indicator Input Change Flag A change has been detec...

Page 591: ...in the Interrupt Disable Register IDR The interrupt request remains active until the corresponding bit in CSR is cleared The clearing of the bits in CSR is described in Channel Status Register on pag...

Page 592: ...592 32072H AVR32 10 2012 AT32UC3A3 Manchester Configuration Register on page 614...

Page 593: ...RHR Read only 0x00000000 0x1C Transmitter Holding Register THR Write only 0x00000000 0x20 Baud Rate Generator Register BRGR Read write 0x00000000 0x24 Receiver Time out Register RTOR Read write 0x0000...

Page 594: ...is bit when USART is in SPI master mode forces NSS RTS pin low even if USART is not transmitting in order to address SPI slave devices supporting the CSAAT Mode Chip Select Active After Transfer DTRDI...

Page 595: ...shift register have been sent No effect if a break signal is already being generated CSR TXRDY and CSR TXEMPTY will be cleared RSTSTA Reset Status Bits Writing a zero to this bit has no effect Writin...

Page 596: ...value MAX_ITERATION This field determines the number of acceptable consecutive NACKs when in protocol T 0 VAR_SYNC Variable Synchronization of Command Data Sync Start Frame Delimiter 0 Sync pattern ac...

Page 597: ...chronous mode SYNC 1 USART operates in Synchronous mode If USART operates in SPI Mode CPHA determines which edge of CLK causes data to change and which edge causes data to be captured CPHA is used wit...

Page 598: ...t the end of this chapter MODE Table 25 21 CHRL Character Length 0 0 5 bits 0 1 6 bits 1 0 7 bits 1 1 8 bits Table 25 22 USCLKS Selected Clock 0 0 CLK_USART 0 1 CLK_USART DIV 1 1 0 Reserved 1 1 CLK Ta...

Page 599: ...INTC LIN Transfer Completed LINIDR LIN Identifier NACK Non Acknowledge RXBUFF Reception Buffer Full ITER UNRE Max number of Repetitions Reached or SPI Underrun Error TXEMPTY Transmitter Empty TIMEOUT...

Page 600: ...LINTC LIN Transfer Completed LINIDR LIN Identifier NACK Non Acknowledge RXBUFF Reception Buffer Full ITER UNRE Max number of Repetitions Reached or SPI Underrun Error TXEMPTY Transmitter Empty TIMEOU...

Page 601: ...Input Change Flag RIIC Ring Indicator Input Change Flag LINTC LIN Transfer Completed LINIDR LIN Identifier NACK Non Acknowledge RXBUFF Reception Buffer Full ITER UNRE Max number of Repetitions Reache...

Page 602: ...E LIN Inconsistent Sync Field Error 0 No LIN Inconsistent Sync Field Error has been detected since the last RSTSTA 1 The USART is configured as a Slave node and a LIN Inconsistent Sync Field Error has...

Page 603: ...is bit is cleared by writing a one to CR RSTSTA NACK Non Acknowledge 0 No Non Acknowledge has been detected since the last RSTNACK 1 At least one Non Acknowledge has been detected since the last RSTNA...

Page 604: ...A RXBRK Break Received End of Break 0 No Break received or End of Break detected since the last RSTSTA 1 Break received or End of Break detected since the last RSTSTA This bit is cleared by writing a...

Page 605: ...00000000 Reading this register will clear the CSR RXRDY bit RXSYNH Received Sync 0 Last character received is a data sync 1 Last character received is a command sync RXCHR Received Character Last rece...

Page 606: ...cter sent is encoded as data and the start frame delimiter is a data sync 1 If MR VARSYNC is one the next character sent is encoded as a command and the start frame delimiter is a command sync TXCHR C...

Page 607: ...d 1 7 Baud rate resolution defined by FP x 1 8 CD Clock Divider 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 FP 15 14 13 12 11 10 9 8 CD 15 8 7 6 5 4 3 2 1 0 CD 7 0 Table 25 24 Baud Rate in Asynchr...

Page 608: ...608 32072H AVR32 10 2012 AT32UC3A3 Table 25 26 Baud Rate in ISO7816 Mode CD Baud Rate 0 Baud Rate Clock Disabled 1 to 65535 Baud Rate Selected Clock FI_DI_RATIO CD...

Page 609: ...in the Write Protect Mode Register WPMR WPEN is zero TO Time out Value 0 The receiver Time out is disabled 1 131071 The receiver Time out is enabled and the time out delay is TO x bit period Note that...

Page 610: ...register can only be written if write protection is disabled in the Write Protect Mode Register WPMR WPEN is zero TG Timeguard Value 0 The transmitter Timeguard is disabled 1 255 The transmitter timeg...

Page 611: ...bled in the Write Protect Mode Register WPMR WPEN is zero FI_DI_RATIO FI Over DI Ratio Value 0 If ISO7816 mode is selected the baud rate generator does not generate a signal 1 2047 If ISO7816 mode is...

Page 612: ...Type Read only Offset 0x44 Reset Value 0x00000000 NB_ERRORS Number of Errors Total number of errors that occurred during an ISO7816 transfer This register is automatically cleared when read 31 30 29 2...

Page 613: ...4C Reset Value 0x00000000 This register can only be written if write protection is disabled in the Write Protect Mode Register WPMR WPEN is zero IRDA_FILTER IrDA Filter Configures the IrDA demodulator...

Page 614: ...coded as one to zero transitions and ones are encoded as a zero to one transitions RX_PP Receiver Preamble Pattern detected RX_PL Receiver Preamble Length 0 The receiver preamble pattern detection is...

Page 615: ...TX_PL Transmitter Preamble Length 0 The transmitter preamble pattern generation is disabled 1 15 The preamble length is TX_PL bit periods Table 25 28 TX_PP Preamble Pattern default polarity assumed TX...

Page 616: ...is enabled 1 The Frame Slot mode is disabled DLM Data Length Mode 0 The response data length is defined by DLC 1 The response data length is defined by bits 4 and 5 of the Identifier LINIR IDCHR CHKTY...

Page 617: ...617 32072H AVR32 10 2012 AT32UC3A3 0 1 SUBSCRIBE The USART receives the response 1 0 IGNORE The USART does not transmit and does not receive the response 1 1 Reserved Table 25 29...

Page 618: ...HR Identifier Character If USART is in LIN master mode the IDCHR field is read write and its value is the Identifier character to be transmitted If USART is in LIN slave mode the IDCHR field is read o...

Page 619: ...clears WPSR WPVSRC and WPSR WPVS WPEN Write Protect Enable 0 Write protection disabled 1 Write protection enabled Protects the registers Mode Register on page 596 Baud Rate Generator Register on page...

Page 620: ...ter was unsuccessfully written to either by address offset or code WPVS Write Protect Violation Status 0 No write protect violation has occurred since the last WPSR read 1 A write protect violation ha...

Page 621: ...SION Access Type Read only Offset 0xFC Reset Value MFN Reserved No functionality associated VERSION Version of the module No functionality associated 26 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16...

Page 622: ...Logic Not Implemented Implemented RS485 Logic Not Implemented Implemented Fractional Baudrate Implemented Implemented ISO7816 Not Implemented Implemented DIV value for divided CLK_USART 8 8 Receiver...

Page 623: ...623 32072H AVR32 10 2012 AT32UC3A3 26 1 2 Register Reset Values Table 26 4 Register Reset Values Register Reset Value VERSION 0x00000420...

Page 624: ...the CPU or the DMA while the other is read or written by the USBB core This feature is mandatory for iso chronous pipes endpoints Table 27 1 on page 624 describes the hardware configuration of the US...

Page 625: ...to clock an internal DLL module to recover the USB dif ferential data at 480Mbit s Figure 27 1 USBB Block Diagram 1 PEP1 512 bytes 2 2 PEP2 512 bytes 2 3 PEP3 256 bytes 1 Table 27 2 Example of Configu...

Page 626: ...power source bus powered or self powered there are different typical hardware implementations 27 4 1 Device Mode 27 4 1 1 Bus Powered device Figure 27 2 Bus Powered Device Application Block Diagram US...

Page 627: ...2 Host Mode Figure 27 4 Host Application Block Diagram USB 2 0 Core USB_VBUS DMFS DPFS USB_ID USB_VBOF I O Controller UTMI DMHS DPHS USB Connector VBus D D ID GND 39 ohms 39 ohms USB 2 0 Core USB_VBU...

Page 628: ...B_VBUS VBus Bus Power Measurement Port Input DMFS FS Data Full Speed Differential Data Line Port Input Output DPFS FS Data Full Speed Differential Data Line Port Input Output DMHS HS Data Hi Speed Dif...

Page 629: ...corresponding pin can be used for other purposes by the I O Controller or by other peripherals 27 6 2 Clocks The clock for the USBB bus interface CLK_USBB is generated by the Power Manager This clock...

Page 630: ...USBB Enable bit in the General Control register USBCON USBE is zero The macro clock is stopped in order to minimize power consumption The Freeze USB Clock bit in USBCON USBON FRZCLK is set The UTMI is...

Page 631: ...e The USBB can be disabled at any time by writing a zero to USBCON USBE In fact writing a zero to USBCON USBE acts as a hardware reset except that the OTGPADE VBUSPO FRZCLK UIDE UIMOD and LS bits are...

Page 632: ...TXINI UESTAX RXOUTI UECONX RXOUTE UESTAX RXSTPI UECONX RXSTPE UESTAX UNDERFI UECONX UNDERFE UESTAX NAKOUTI UECONX NAKOUTE UESTAX NAKINI UECONX NAKINE UESTAX OVERFI UECONX OVERFE UESTAX STALLEDI UECON...

Page 633: ...the Frozen mode except that the USB generic clock and other clocks are stopped so the USB macro is frozen Only the asynchronous USB interrupt sources can wake up the MCU in these modes 1 The Power Man...

Page 634: ...cts the speed of the connected device which is reflected by the Speed Status SPEED field in USBSTA 27 7 1 6 DPRAM management Pipes and endpoints can only be allocated in ascending order from the pipe...

Page 635: ...e data of these pipes endpoints is potentially lost Note that There is no way the data of the pipe endpoint 0 can be lost except if it is de allocated as memory allocation and de allocation may affect...

Page 636: ...nes In the Active state the pad is working Figure 27 9 on page 636 illustrates the pad events leading to a PAD state change Figure 27 9 Pad Events The SUSP bit is set and the Wake Up Interrupt WAKEUP...

Page 637: ...han or equal to 4 4V In device mode the USBSTA VBUS bit follows the Session_valid comparator output It is set when the voltage on the USB_VBUS pad is higher than or equal to 1 4V It is cleared when th...

Page 638: ...BSTA ID is one what corresponds to the case where no Mini A plug is connected i e no plug or a Mini B plug is connected and the USB_ID pin is kept high by the internal pull up resis tor from the I O C...

Page 639: ...device mode are reset The endpoint banks are de allocated Neither D nor D is pulled up DETACH is written to one D or D will be pulled up according to the selected speed as soon as the DETACH bit is w...

Page 640: ...oint UECFGn UESTAn the Endpoint n Control UECONn register except its configuration ALLOC EPBK EPSIZE EPDIR EPTYPE and the Data Toggle Sequence DTSEQ field of the UESTAn register Note that the interrup...

Page 641: ...this address to the USB Address UADD field in UDCON and write a zero to the Address Enable ADDEN bit in UDCON so the actual address is still 0 The user sends a zero length IN packet from the control...

Page 642: ...DEVICE_REMOTE_WAKEUP request from the host First the USBB must have detected a Suspend state on the bus i e the Remote Wake Up request can only be sent after a SUSP interrupt has been set The user ma...

Page 643: ...irrelevant for control endpoints The user shall therefore never use them on these endpoints When read their value are always zero Control endpoints are managed using The RXSTPI bit which is set when...

Page 644: ...ption sets RXOUTI and TXINI Handle this with the following software algorithm set TXINI wait for RXOUTI OR TXINI if RXOUTI then clear bit and return if TXINI then continue Once the OUT status stage ha...

Page 645: ...NnCLR TXINIC to acknowledge the interrupt what has no effect on the endpoint FIFO The user then writes into the FIFO see USB Pipe Endpoint n FIFO Data Register USBFIFOn DATA on page 747 and write a on...

Page 646: ...s the controller to send the bank and switches to the next bank if any by clearing FIFOCON If the endpoint uses several banks the current one can be written while the previous one is being read by the...

Page 647: ...hat has no effect on the endpoint FIFO The user then reads from the FIFO see USB Pipe Endpoint n FIFO Data Register USBFIFOn DATA on page 747 and clears the FIFOCON bit to free the bank If the OUT end...

Page 648: ...frame is read or the bank is empty in which case RWALL is cleared and BYCT reaches zero The user frees the bank and switches to the next bank if any by clearing FIFOCON If the endpoint uses several ba...

Page 649: ...is filled with all the first bytes of the packet that fit in An overflow can not occur during IN stage on a CPU action since the user may write only if the bank is not full TXINI is one or RWALL is on...

Page 650: ...ce global interrupts are The Suspend SUSP interrupt The Start of Frame SOF interrupt with no frame number CRC error the Frame Number CRC Error FNCERR bit in the Device Frame Number UDFNUM register is...

Page 651: ...DMA interrupts The processing device DMA interrupts are The End of USB Transfer Status EOTSTA interrupt The End of Channel Buffer Status EOCHBUFFSTA interrupt The Descriptor Loaded Status DESCLDSTA in...

Page 652: ...a device endpoint considering the device configu ration descriptors 27 7 3 2 Power On and reset Figure 27 22 on page 652 describes the USBB host mode main states Figure 27 22 Host Mode States After a...

Page 653: ...s previously in a Suspend state the Start of Frame Generation Enable SOFE bit in UHCON is zero the USBB automatically switches it to the Resume state the Host Wake Up Interrupt HWUPI bit in UHINT is s...

Page 654: ...pipes When starting an enumeration the user gets the device descriptor by sending a GET_DESCRIPTOR USB request This descriptor contains the maximal packet size of the device default control endpoint b...

Page 655: ...ntrol pipes A control transaction is composed of three stages SETUP Data IN or OUT Status OUT or IN The user has to change the pipe token according to each stage For the control pipe and only for it e...

Page 656: ...dated in accordance with the status of the next bank RXINI shall always be cleared before clearing FIFOCON The Read Write Allowed RWALL bit in UPSTAn is set when the current bank is not empty i e the...

Page 657: ...s are updated in accordance with the status of the next bank TXOUTI shall always be cleared before clearing FIFOCON The UPSTAn RWALL bit is set when the current bank is not full i e the software can w...

Page 658: ...if no CRC error had occurred RXINI is set 27 7 3 13 Interrupts See the structure of the USB host interrupt system on Figure 27 6 on page 632 There are two kinds of host interrupts processing i e thei...

Page 659: ...ransmitted OUT Data Interrupt TXOUTI The Transmitted SETUP Interrupt TXSTPI The Short Packet Interrupt SHORTPACKETI The Number of Busy Banks NBUSYBK interrupt The exception host pipe interrupts are Th...

Page 660: ...hanges which are very clock cycle consuming will then likely not occur or occur once instead of dozens of times during a single big USB packet DMA transfer in case other HSB masters address the memory...

Page 661: ...Channel n Control Register DMAnCONTROL 27 7 4 3 Programming a chanel Each DMA transfer is unidirectionnal Direction depends on the type of the associated endpoint IN or OUT Three registers the UDDMAnN...

Page 662: ...y released even if there are some residual datas inside i e OUT packet truncation at the end of DMA buffer when the dma channel byte lenght is not an integral multiple of the endpoint size Programming...

Page 663: ...channel byte length is reached after one or multiple processed OUT packet the UDDMAnCONTROL CHEN bit is cleared As a conse quence the UDDMAnSTATUS CHEN bit is also cleared and the UDDMAnSTATUS EOCHBU...

Page 664: ...OUT packet As soon as an OUT packet is stored inside the endpoint the UDDMAnSTATUS CHACTIVE bit is set to one Then after a few cycle latency the new descriptor is loaded from the memory and the UDDMAn...

Page 665: ...UECFG5 Read Write 0x00002000 0x0118 Endpoint 6 Configuration Register UECFG6 Read Write 0x00002000 0x011C Endpoint 7Configuration Register UECFG7 Read Write 0x00002000 0x0130 Endpoint 0 Status Regist...

Page 666: ...l Set Register UECON2SET Write Only 0x00000000 0x01FC Endpoint 3 Control Set Register UECON3SET Write Only 0x00000000 0x0200 Endpoint 4 Control Set Register UECON4SET Write Only 0x00000000 0x0204 Endp...

Page 667: ...344 Device DMA Channel 4 HSB Address Register UDDMA4 ADDR Read Write 0x00000000 0x0348 Device DMA Channel 4 Control Register UDDMA4 CONTROL Read Write 0x00000000 0x034C Device DMA Channel 4 Status Reg...

Page 668: ...Write 0x00000000 0x0504 Pipe 1 Configuration Register UPCFG1 Read Write 0x00000000 0x0508 Pipe 2 Configuration Register UPCFG2 Read Write 0x00000000 0x050C Pipe 3 Configuration Register UPCFG3 Read W...

Page 669: ...4 Pipe 5 Control Register UPCON5 Read Only 0x00000000 0x05D8 Pipe 6 Control Register UPCON6 Read Only 0x00000000 0x05DC Pipe 7 Control Register UPCON7 Read Only 0x00000000 0x05F0 Pipe 0 Control Set Re...

Page 670: ...00000 0x069C Pipe 7 Error Register UPERR7 Read Write 0x00000000 0x0710 Host DMA Channel 1 Next Descriptor Address Register UHDMA1 NEXTDESC Read Write 0x00000000 0x0714 Host DMA Channel 1 HSB Address R...

Page 671: ...trol Register UHDMA6 CONTROL Read Write 0x00000000 0x076C Host DMA Channel 6 Status Register UHDMA6 STATUS Read Write 0x00000000 0x0770 Host DMA Channel 7 Next Descriptor Address Register UHDMA7 NEXTD...

Page 672: ...ister USB FIFO1DATA Read Write Undefined 0x20000 0x2FFFC Pipe Endpoint 2 FIFO Data Register USB FIFO2DATA Read Write Undefined 0x30000 0x3FFFC Pipe Endpoint 3 FIFO Data Register USB FIFO3DATA Read Wri...

Page 673: ...it does not reset this bit UNLOCK Timer Access Unlock 1 The TIMPAGE and TIMVALUE fields are unlocked 0 The TIMPAGE and TIMVALUE fields are locked The TIMPAGE and TIMVALUE fields can always be read wha...

Page 674: ...FRZCLK is one Disabling the USBB by writing a zero to the USBE bit does not reset this bit VBUSHWC VBus Hardware Control 1 The hardware control over the USB_VBOF output pin is disabled 0 The hardware...

Page 675: ...e This bit is cleared when the USB_ID level is low even if USBE is zero This bit is set when the USB_ID level is high event if USBE is zero VBUSRQ VBus Request This bit is set when the USBSTASET VBUSR...

Page 676: ...This bit is set when a VBus drop has been detected This triggers a USB interrupt if VBERRE is one This bit is cleared when the UBSTACLR VBERRIC bit is written to one This bit shall only be used in ho...

Page 677: ...808 Read Value 0x00000000 Writing a one to a bit in this register will clear the corresponding bit in UBSTA Writing a zero to a bit in this register has no effect This bit always reads as zero 31 30 2...

Page 678: ...00 Writing a one to a bit in this register will set the corresponding bit in UBSTA what may be useful for test or debug purposes Writing a zero to a bit in this register has no effect This bit always...

Page 679: ...Read Only Offset 0x0818 Read Value VARIANT Variant Number Reserved No functionality associated VERSION Version Number Version number of the module No functionality associated 31 30 29 28 27 26 25 24 2...

Page 680: ...te Capability 1 The DPRAM is natively byte write capable 0 The DPRAM byte write lanes have shadow logic implemented in the USBB IP interface FIFOMAXSIZE Maximal FIFO Size This field indicates the maxi...

Page 681: ...er of DMA Channels This field indicates the number of hardware implemented DMA channels EPTNBRMAX Maximal Number of Pipes Endpoints This field indicates the number of hardware implemented pipes endpoi...

Page 682: ...Read Only Offset 0x0820 Read Value UADDRSIZE IP PB Address Size This field indicates the size of the PB address space reserved for the USBB IP interface 31 30 29 28 27 26 25 24 UADDRSIZE 31 24 23 22...

Page 683: ...ccess Type Read Only Offset 0x0824 Read Value UNAME1 IP Name Part One This field indicates the first part of the ASCII encoded name of the USBB IP 31 30 29 28 27 26 25 24 UNAME1 31 24 23 22 21 20 19 1...

Page 684: ...ccess Type Read Only Offset 0x0828 Read Value UNAME2 IP Name Part Two This field indicates the second part of the ASCII encoded name of the USBB IP 31 30 29 28 27 26 25 24 UNAME2 31 24 23 22 21 20 19...

Page 685: ...mode is operational 4 a_suspend The A device operating as a host is in the suspend mode 5 a_peripheral The A device operates as a peripheral 6 a_wait_vfall In this state the A device waits for the vo...

Page 686: ...is state the B device waits for the A device to signal a connect before becoming B Host 14 b_host In this state the B device acts as the Host 15 b_srp_init In this state the B device attempts to start...

Page 687: ...iver is in normal operation mode TSTK Test mode K 1 The UTMI transceiver generates high speed K state for test purpose 0 The UTMI transceiver is in normal operation mode TSTJ Test mode J 1 The UTMI tr...

Page 688: ...a zero to this bit will reconnect the device ADDEN Address Enable Writing a one to this bit will activate the UADD field USB address Writing a zero to this bit has no effect This bit is cleared when...

Page 689: ...USBB detects a valid End of Resume signal initiated by the host This triggers a USB interrupt if EORSME is one This bit is cleared when the UDINTCLR EORSMC bit is written to one to acknowledge the int...

Page 690: ...speed mode when a USB Micro Start of Frame PID SOF has been detected every 125 us This triggers a USB interrupt if MSOFE is one The MFNUM field is updated The FNUM field is unchanged This bit is clea...

Page 691: ...set 0x0008 Read Value 0x00000000 Writing a one to a bit in this register will clear the corresponding bit in UDINT Writing a zero to a bit in this register has no effect This bit always reads as zero...

Page 692: ...t in this register will set the corresponding bit in UDINT what may be useful for test or debug purposes Writing a zero to a bit in this register has no effect This bit always reads as zero 31 30 29 2...

Page 693: ...led A bit in this register is set when the corresponding bit in UDINTESET is written to one A bit in this register is cleared when the corresponding bit in UDINTECLR is written to one 31 30 29 28 27 2...

Page 694: ...r will clear the corresponding bit in UDINTE Writing a zero to a bit in this register has no effect This bit always reads as zero 31 30 29 28 27 26 25 24 DMA7INTEC DMA6INTEC DMA5INTEC DMA4INTEC DMA3IN...

Page 695: ...r will set the corresponding bit in UDINTE Writing a zero to a bit in this register has no effect This bit always reads as zero 31 30 29 28 27 26 25 24 DMA7INTES DMA6INTES DMA5INTES DMA4INTES DMA3INTE...

Page 696: ...eld DTSEQ which can be cleared by setting the RSTDT bit by writing a one to the RSTDTS bit The endpoint configuration remains active and the endpoint is still enabled Writing a zero to this bit will c...

Page 697: ...ld contains the 11 bit frame number information It is provided in the last received SOF packet This field is cleared upon receiving a USB reset FNUM is updated even if a corrupted SOF is received MFNU...

Page 698: ...to know if the high bandwidth isochronous feature is supported by the device EPTYPE Endpoint Type This field shall be written to select the endpoint type This field is cleared upon receiving a USB res...

Page 699: ...s field shall be written to select the number of banks for the endpoint For control endpoints a single bank endpoint 0b00 shall be selected This field is cleared upon receiving a USB reset except for...

Page 700: ...ndpoint and to the maximal FIFO size i e the DPRAM size If this bit is cleared the user shall rewrite correct values to the EPBK and EPSIZE fields in the UECFGn register CTRLDIR Control Direction This...

Page 701: ...bandwidth isochronous OUT endpoint transaction error Interrupt This bit is set when a transaction error occurs during the current micro frame the data toggle sequencing does not respect the usb 2 0 st...

Page 702: ...ow can occur during OUT stage if the host attempts to write into a bank that is too small for the packet The packet is acknowledged and the RXOUTI bit is set as if no overflow had occurred The bank is...

Page 703: ...iggers an EPnINT interrupt if RXOUTE is one Shall be cleared for isochronous bulk and interrupt OUT endpoints by writing a one to the RXOUTIC bit This will acknowledge the interrupt what has no effect...

Page 704: ...000 Writing a one to a bit in this register will clear the corresponding bit in UESTA Writing a zero to a bit in this register has no effect This bit always reads as zero 31 30 29 28 27 26 25 24 23 22...

Page 705: ...in this register will set the corresponding bit in UESTA what may be useful for test or debug purposes Writing a zero to a bit in this register has no effect This bit always reads as zero 31 30 29 28...

Page 706: ...et when the EPDISHDMAS is written to one This will pause the on going DMA channel n transfer on any Endpoint n interrupt EPnINT whatever the state of the Endpoint n Interrupt Enable bit EPnINTE The us...

Page 707: ...rupt ERRORTRANS This bit is cleared when the ERRORTRANSEC bit is written to one This will disable the transaction error interrupt ERRORTRANS DATAXE DataX Interrupt Enable This bit is set when the DATA...

Page 708: ...ceived SETUP Interrupt Enable This bit is set when the RXSTPES bit is written to one This will enable the Received SETUP interrupt RXSTPI This bit is cleared when the RXSTPEC bit is written to one Thi...

Page 709: ...ister will clear the corresponding bit in UECONn Writing a zero to a bit in this register has no effect This bit always reads as zero 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 STALLRQC NYETDISC...

Page 710: ...er will set the corresponding bit in UECONn Writing a zero to a bit in this register has no effect This bit always reads as zero 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 STALLRQS RSTDTS NYETDIS...

Page 711: ...0 Reset Value 0x00000000 NXTDESCADDR Next Descriptor Address This field contains the bits 31 4 of the 16 byte aligned address of the next channel descriptor to be processed This field is written eithe...

Page 712: ...updated at the end of the address phase of the current access to the HSB bus It is incremented of the HSB access byte width The HSB access width is 4 bytes or less at packet start or end if the start...

Page 713: ...ted when a Descriptor has been loaded from the system bus 0 The Descriptor Loaded interrupt is disabled EOBUFFIRQEN End of Buffer Interrupt Enable 1 The end of buffer interrupt is enabled This interru...

Page 714: ...EN Channel Enable Writing this bit to zero will disabled the DMA channel and no transfer will occur upon request If the LDNXTCHDESCEN bit is written to zero the channel is frozen and the channel regis...

Page 715: ...will be cancelled by the DMA and the EOTSTA will be set whatever the UDDMAnCONTROL CHEN bit is This bit is automatically cleared when read by software CHACTIVE Channel Active 0 the DMA channel is no l...

Page 716: ...scriptor if the UDDMAnCONTROL LDNXTCHDESCEN bit is zero 1 the DMA channel is currently enabled and transfers data upon request If a channel request is currently serviced when the UDDMAnCONTROL CHEN bi...

Page 717: ...te a zero to this bit when a device disconnection is detected UHINT DDISCI is one whereas a USB Reset is being sent SOFE Start of Frame Generation Enable Writing a one to this bit will generate SOF on...

Page 718: ...t controller is in the Idle state USBSTA VBUSRQ is zero no VBus is generated This interrupt is generated even if the clock is frozen by the FRZCLK bit HSOFI Host Start of Frame Interrupt This bit is s...

Page 719: ...t is set when the device has been removed from the USB bus This bit is cleared when the DDISCIC bit is written to one DCONNI Device Connection Interrupt This bit is set when a new device has been conn...

Page 720: ...0x0408 Read Value 0x00000000 Writing a one to a bit in this register will clear the corresponding bit in UHINT Writing a zero to a bit in this register has no effect This bit always reads as zero 31 3...

Page 721: ...this register will set the corresponding bit in UHINT what may be useful for test or debug purposes Writing a zero to a bit in this register has no effect This bit always reads as zero 31 30 29 28 27...

Page 722: ...le the Upstream Resume Received interrupt RXRSMI This bit is cleared when the RXRSMIEC bit is written to one This will disable the Downstream Resume interrupt RXRSMI RSMEDIE Downstream Resume Sent Int...

Page 723: ...r will clear the corresponding bit in UHINTE Writing a zero to a bit in this register has no effect This bit always reads as zero 31 30 29 28 27 26 25 24 DMA7INTEC DMA6INTEC DMA5INTEC DMA4INTEC DMA3IN...

Page 724: ...er will set the corresponding bit in UHINT Writing a zero to a bit in this register has no effect This bit always reads as zero 31 30 29 28 27 26 25 24 DMA7INTES DMA6INTES DMA5INTES DMA4INTES DMA3INTE...

Page 725: ...contains the 8 high order bits of the 16 bit internal frame counter at 30MHz counter length is 3750 to ensure a SOF generation every 125 us FNUM Frame Number This field contains the current SOF numbe...

Page 726: ...his field contains the address of the Pipe2 of the USB Device This field is cleared when a USB reset is requested UHADDRP1 USB Host Address This field contains the address of the Pipe1 of the USB Devi...

Page 727: ...This field contains the address of the Pipe6 of the USB Device This field is cleared when a USB reset is requested UHADDRP5 USB Host Address This field contains the address of the Pipe5 of the USB Dev...

Page 728: ...rt from the Data Toggle management The endpoint configuration remains active and the endpoint is still enabled Writing a zero to this bit will complete the reset operation and allow to start using the...

Page 729: ...UT token is sent every BINTERVAL micro frame until it is ACKed by the peripheral If BINTERVAL 0 and PINGEN 0 multiple consecutive OUT token is sent in the same micro frame until it is ACKed This value...

Page 730: ...a USB reset PBK Pipe Banks This field contains the number of banks for the pipe For control endpoints a single bank pipe 0b00 should be selected This field is cleared upon sending a USB reset 0 1 Isoc...

Page 731: ...OC Pipe Memory Allocate Writing a one to this bit will allocate the pipe memory Writing a zero to this bit will free the pipe memory This bit is cleared when a USB Reset is requested Refer to the DPRA...

Page 732: ...BK and size UPCFGn PSIZE are correct compared to the maximal allowed number of banks and size for this pipe and to the maximal FIFO size i e the DPRAM size If this bit is cleared the user should rewri...

Page 733: ...TIC bit is written to one RXSTALLDI Received STALLed Interrupt This bit is set for all endpoints but isochronous when a STALL handshake has been received on the current bank of the pipe The Pipe is au...

Page 734: ...OUT pipe when a transaction underflow occurs in the current pipe the pipe can t send the OUT data packet in time because the current bank is not ready A zero length packet ZLP will be sent instead of...

Page 735: ...Value 0x00000000 Writing a one to a bit in this register will clear the corresponding bit in UPSTAn Writing a zero to a bit in this register has no effect This bit always reads as zero 31 30 29 28 27...

Page 736: ...to a bit in this register will set the corresponding bit in UPSTAn what may be useful for test or debug purposes Writing a zero to a bit in this register has no effect This bit always reads as zero 3...

Page 737: ...s set when the current bank is free at the same time than TXOUTI or TXSTPI This bit is cleared when the FIFOCONC bit is written to one This will send the FIFO data and switch the bank For IN Pipe This...

Page 738: ...r Interrupt Enable This bit is set when the PERRES bit is written to one This will enable the Transmitted IN Data interrupt PERRE This bit is cleared when the PERREC bit is written to one This will di...

Page 739: ...ng a one to a bit in this register will clear the corresponding bit in UPCONn Writing a zero to a bit in this register has no effect This bit always reads as zero 31 30 29 28 27 26 25 24 23 22 21 20 1...

Page 740: ...ing a one to a bit in this register will set the corresponding bit in UPCONn Writing a zero to a bit in this register has no effect This bit always reads as zero 31 30 29 28 27 26 25 24 23 22 21 20 19...

Page 741: ...number of IN requests This number is the INRQ field INRQ IN Request Number before Freeze This field contains the number of IN transactions before the USBB freezes the pipe The USBB will perform INRQ...

Page 742: ...Writing a one to this bit has no effect TIMEOUT Time Out Error This bit is set when a Time Out error has been detected Writing a zero to this bit will clear the bit Writing a one to this bit has no e...

Page 743: ...ster Register Name UHDMAnNEXTDESC n in 1 7 Access Type Read Write Offset 0x0710 n 1 0x10 Reset Value 0x00000000 Same as Section 27 8 2 17 31 30 29 28 27 26 25 24 NXTDESCADDR 31 24 23 22 21 20 19 18 17...

Page 744: ...Register Register Name UHDMAnADDR n in 1 7 Access Type Read Write Offset 0x0714 n 1 0x10 Reset Value 0x00000000 Same as Section 27 8 2 18 31 30 29 28 27 26 25 24 HSBADDR 31 24 23 22 21 20 19 18 17 16...

Page 745: ...fset 0x0718 n 1 0x10 Reset Value 0x00000000 Same as Section 27 8 2 19 just replace the IN endpoint term by OUT endpoint and vice versa 31 30 29 28 27 26 25 24 CHBYTELENGTH 15 8 23 22 21 20 19 18 17 16...

Page 746: ...ister Name UHDMAnSTATUS n in 1 7 Access Type Read Write Offset 0x071C n 1 0x10 Reset Value 0x00000000 Same as Section 27 8 2 20 31 30 29 28 27 26 25 24 CHBYTECNT 15 8 23 22 21 20 19 18 17 16 CHBYTECNT...

Page 747: ...ncrement is fully handled by hardware Byte half word and word access are supported Data should be access in a big endian way For instance if the application wants to write into the Endpoint Pipe3 it c...

Page 748: ...us clocks listed here are connected to the system bus clocks Please refer to the Power Manager chapter for details Table 27 7 Module Clock Name Module name Clock name Clock name USBB CLK_USBB_HSB CLK_...

Page 749: ...r Counter channels Each channel can be independently programmed to perform a wide range of functions including frequency measurement event counting interval measurement pulse generation delay timing a...

Page 750: ...ral functions I O Controller TC2XC2S INT0 INT1 INT2 TIOA0 TIOA1 TIOA2 TIOB0 TIOB1 TIOB2 XC2 TCLK0 TCLK1 TCLK2 TCLK0 TCLK1 TCLK2 TCLK0 TCLK1 TCLK2 TIOA1 TIOA2 TIOA0 TIOA2 TIOA1 Interrupt Controller CLK...

Page 751: ...cal in operation The regis ters for channel programming are listed in Figure 28 3 on page 766 28 6 1 1 Channel I O Signals As described in Figure 28 1 on page 750 each Channel has the following I O si...

Page 752: ...ources This selection is made by the Clock Selection field in the Channel n Mode Register CMRn TCCLKS The selected clock can be inverted with the Clock Invert bit in CMRn CMRn CLKI This allows countin...

Page 753: ...mpare always starts the clock In Capture mode the clock can be stopped by an RB load event if the Counter Clock Stopped with RB Loading bit in CMRn is written to one CMRn LDBSTOP In Waveform mode it c...

Page 754: ...on of the pulses must be longer than the CLK_TC period in order to be detected Regardless of the trigger used it will be taken into account at the following active edge of the selected clock This mean...

Page 755: ...trig ger can be defined The TIOA or TIOB External Trigger Selection bit in CMRn CMRn ABETRG selects TIOA or TIOB input signal as an external trigger The External Trigger Edge Selection bit in CMRn CM...

Page 756: ...pare RC 16 bit Counter ABETRG SWTRG ETRGEDG CPCTRG IMR Trig LDRBS LDRAS ETRGS SR LOVRS COVFS SYNC 1 MTIOB TIOA MTIOA LD R A LDBSTOP If RA is not Loaded or RB is Loaded If RA is Loaded LDBDIS CPCS INT...

Page 757: ...onfigured as an output and TIOB is defined as an output if it is not used as an external event Figure 28 5 on page 758 shows the configuration of the TC channel when programmed in Waveform operating m...

Page 758: ...E E VTEDG SYNC SWTRG EN E T R G WAVSEL IMR T rig ACPC ACPA AEEVT ASWTRG BCPC BCPB BEEVT BSWTRG TIOA MTIOA TIOB MTIOB CPAS COVFS ETRGS SR CPCS CPBS CLK OVF RESET O utput Contr oller O utput Cont r olle...

Page 759: ...trigger or a software trigger can reset the value of CVn It is important to note that the trigger may occur at any time See Figure 28 7 on page 760 RC Compare cannot be programmed to generate a trigg...

Page 760: ...n incremented and so on See Figure 28 8 on page 761 It is important to note that CVn can be reset at any time by an external event or a software trig ger if both are programmed correctly See Figure 28...

Page 761: ...from 0 to 0xFFFF Once 0xFFFF is reached the value of CVn is decremented to 0 then re incremented to 0xFFFF and so on See Figure 28 10 on page 762 Time Counter Value RC RB RA TIOB TIOA Counter cleared...

Page 762: ...o generate a trigger in this configuration At the same time RC Compare can stop the counter clock CMRn CPCSTOP 1 and or dis able the counter clock CMRn CPCDIS 1 Figure 28 10 WAVSEL 1 Without Trigger F...

Page 763: ...external event or a software trigger can modify CVn at any time If a trigger occurs while CVn is incrementing CVn then decrements If a trigger is received while CVn is decrementing CVn then increments...

Page 764: ...nnel can only generate a waveform on TIOA When an external event is defined it can be used as a trigger by writing a one to the CMRn ENETRG bit As in Capture mode the SYNC signal and the software trig...

Page 765: ...765 32072H AVR32 10 2012 AT32UC3A3 RB Compare Effect on TIOB CMRn BCPB RC Compare Effect on TIOA CMRn ACPC RA Compare Effect on TIOA CMRn ACPA...

Page 766: ...Channel 1 Register B RB1 Read Write 1 0x00000000 0x5C Channel 1 Register C RC1 Read Write 0x00000000 0x60 Channel 1 Status Register SR1 Read only 0x00000000 0x64 Channel 1 Interrupt Enable Register IE...

Page 767: ...767 32072H AVR32 10 2012 AT32UC3A3 Notes 1 Read only if CMRn WAVE is zero 2 The reset values are device specific Please refer to the Module Configuration section at the end of this chapter...

Page 768: ...and the clock is started 0 Writing a zero to this bit has no effect CLKDIS Counter Clock Disable Command 1 Writing a one to this bit will disable the clock 0 Writing a zero to this bit has no effect C...

Page 769: ...RC Compare resets the counter and starts the counter clock 0 RC Compare has no effect on the counter and its clock ABETRG TIOA or TIOB External Trigger Selection 1 TIOA is used as an external trigger...

Page 770: ...topped when RB loading occurs BURST Burst Signal Selection CLKI Clock Invert 1 The counter is incremented on falling edge of the clock 0 The counter is incremented on rising edge of the clock TCCLKS C...

Page 771: ...TRG Software Trigger Effect on TIOB BEEVT External Event Effect on TIOB 31 30 29 28 27 26 25 24 BSWTRG BEEVT BCPC BCPB 23 22 21 20 19 18 17 16 ASWTRG AEEVT ACPC ACPA 15 14 13 12 11 10 9 8 WAVE WAVSEL...

Page 772: ...ware Trigger Effect on TIOA AEEVT External Event Effect on TIOA ACPC RC Compare Effect on TIOA BCPC Effect 0 none 1 set 2 clear 3 toggle BCPB Effect 0 none 1 set 2 clear 3 toggle ASWTRG Effect 0 none...

Page 773: ...is configured as an input and no longer generates waveforms and subse quently no IRQs EEVTEDG External Event Edge Selection CPCDIS Counter Clock Disable with RC Compare 1 Counter clock is disabled whe...

Page 774: ...Counter is incremented on falling edge of the clock 0 Counter is incremented on rising edge of the clock TCCLKS Clock Selection BURST Burst Signal Selection 0 The clock is not gated by an external sig...

Page 775: ...nter Value Register Name CV Access Type Read only Offset 0x10 n 0x40 Reset Value 0x00000000 CV Counter Value CV contains the counter value in real time 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16...

Page 776: ...A Access Type Read only if CMRn WAVE 0 Read Write if CMRn WAVE 1 Offset 0x14 n 0X40 Reset Value 0x00000000 RA Register A RA contains the Register A value in real time 31 30 29 28 27 26 25 24 23 22 21...

Page 777: ...B Access Type Read only if CMRn WAVE 0 Read Write if CMRn WAVE 1 Offset 0x18 n 0x40 Reset Value 0x00000000 RB Register B RB contains the Register B value in real time 31 30 29 28 27 26 25 24 23 22 21...

Page 778: ...el Register C Name RC Access Type Read Write Offset 0x1C n 0x40 Reset Value 0x00000000 RC Register C RC contains the Register C value in real time 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14...

Page 779: ...at TIOA pin is low If CMRn WAVE is one this means that TIOA is driven low CLKSTA Clock Enabling Status 1 This bit is set when the clock is enabled 0 This bit is cleared when the clock is disabled ETRG...

Page 780: ...pare has occurred and CMRn WAVE is one 0 This bit is cleared when the SR register is read LOVRS Load Overrun Status 1 This bit is set when RA or RB have been loaded at least twice without any read of...

Page 781: ...Offset 0x24 n 0x40 Reset Value 0x00000000 Writing a zero to a bit in this register has no effect Writing a one to a bit in this register will set the corresponding bit in IMR 31 30 29 28 27 26 25 24...

Page 782: ...Offset 0x28 n 0x40 Reset Value 0x00000000 Writing a zero to a bit in this register has no effect Writing a one to a bit in this register will clear the corresponding bit in IMR 31 30 29 28 27 26 25 2...

Page 783: ...ng interrupt is disabled 1 The corresponding interrupt is enabled A bit in this register is cleared when the corresponding bit in IDR is written to one A bit in this register is set when the correspon...

Page 784: ...C0 Reset Value 0x00000000 SYNC Synchro Command 1 Writing a one to this bit asserts the SYNC signal which generates a software trigger simultaneously for each of the channels 0 Writing a zero to this b...

Page 785: ...0000 TC2XC2S External Clock Signal 2 Selection TC1XC1S External Clock Signal 1 Selection 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TC2XC2S TC1XC1S TC0XC0S T...

Page 786: ...786 32072H AVR32 10 2012 AT32UC3A3 TC0XC0S External Clock Signal 0 Selection TC0XC0S Signal Connected to XC0 0 TCLK0 1 none 2 TIOA1 3 TIOA2...

Page 787: ...ge type is PB to HSB 0 Bridge type is not PB to HSB UPDNIMPL Up down is implemented 1 Up down counter capability is implemented 0 Up down counter capability is not implemented CTRSIZE Counter size Thi...

Page 788: ...only Offset 0xFC Reset Value VARIANT Variant number Reserved No functionality associated VERSION Version number Version number of the module No functionality associated 31 30 29 28 27 26 25 24 23 22...

Page 789: ...ble in the Power Manager section 28 8 1 Clock Connections Each Timer Counter channel can independently select an internal or external clock source for its counter Table 28 4 Module Clock Name Module n...

Page 790: ...cessive Approximation Register SAR 10 bit ADC It also integrates an 8 to 1 analog multiplexer making possible the analog to digital conversions of 8 analog lines The conversions extend from 0V to VDDA...

Page 791: ...e I O Controller Table 29 1 ADC Pins Description Pin Name Description VDDANA Analog power supply AD 0 AD 7 Analog input channels TRIGGER External trigger AD AD AD Dedicated Analog Inputs AD AD AD Anal...

Page 792: ...tional Description 29 6 1 Analog to digital Conversion The ADC uses the ADC Clock to perform conversions Converting a single analog value to a 10 bit digital data requires sample and hold clock cycles...

Page 793: ...f the current channel and in the LCDR register Channels are enabled by writing a one to the Channel n Enable bit CHn in the CHER register The corresponding channel End of Conversion bit in the Status...

Page 794: ...ically cleared when the SR register is read Figure 29 3 GOVRE and OVREn Flag Behavior Warning If the corresponding channel is disabled during a conversion or if it is disabled and then reenabled durin...

Page 795: ...he resulting data buffers should be interpreted accordingly Warning Enabling hardware triggers does not disable the software trigger functionality Thus if a hardware trigger is selected the start of a...

Page 796: ...for the ADC to guarantee the best converted final value between two channels selection This time has to be defined through the Sample and Hold Time field in the Mode Register MR SHTIM This time depen...

Page 797: ...nly 0x00000000 0x14 Channel Disable Register CHDR Write only 0x00000000 0x18 Channel Status Register CHSR Read only 0x00000000 0x1C Status Register SR Read only 0x000C0000 0x20 Last Converted Data Reg...

Page 798: ...one to this bit will begin an analog to digital conversion Writing a zero to this bit has no effect This bit always reads zero SWRST Software Reset Writing a one to this bit will reset the ADC Writing...

Page 799: ...ution is selected TRGSEL Trigger Selection TRGEN Trigger Enable 1 The hardware trigger selected by the TRGSEL field is enabled 0 The hardware triggers are disabled Starting a conversion is only possib...

Page 800: ...0x10 Reset Value 0x00000000 CHn Channel n Enable Writing a one to these bits will set the corresponding bit in CHSR Writing a zero to these bits has no effect These bits always read a zero 31 30 29 28...

Page 801: ...bit in CHSR Writing a zero to these bits has no effect These bits always read a zero Warning If the corresponding channel is disabled during a conversion or if it is disabled then reenabled during a...

Page 802: ...tus These bits are set when the corresponding bits in CHER is written to one These bits are cleared when the corresponding bits in CHDR is written to one 1 The corresponding channel is enabled 0 The c...

Page 803: ...is bit is cleared when the LCDR register is read 0 No data has been converted since the last read of the LCDR register 1 At least one data has been converted and is available in the LCDR register OVRE...

Page 804: ...set 0x20 Reset Value 0x00000000 LDATA Last Data Converted The analog to digital conversion data is placed into this register at the end of a conversion and remains until a new conversion is completed...

Page 805: ...0 Writing a zero to a bit in this register has no effect Writing a one to a bit in this register will set the corresponding bit in IMR 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RXBUFF ENDRX GOVR...

Page 806: ...0 Writing a zero to a bit in this register has no effect Writing a one to a bit in this register will clear the corresponding bit in IMR 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RXBUFF ENDRX GO...

Page 807: ...g interrupt is enabled A bit in this register is cleared when the corresponding bit in IDR is written to one A bit in this register is cleared when the corresponding bit in IER is written to one 31 30...

Page 808: ...rted Data The analog to digital conversion data is placed into this register at the end of a conversion and remains until a new conversion is completed The Convert Data Register CDR is only loaded if...

Page 809: ...only Offset 0xFC Reset Value VARIANT Variant Number Reserved No functionality associated VERSION Version Number Version number of the module No functionality associated 31 30 29 28 27 26 25 24 23 22...

Page 810: ...0 Internal Trigger 1 TIOB Ouput B of the Timer Counter 0 Channel 0 Internal Trigger 2 TIOA Ouput A of the Timer Counter 0 Channel 1 Internal Trigger 3 TIOB Ouput B of the Timer Counter 0 Channel 1 In...

Page 811: ...to measure the activity and stall cycles on the High Speed Bus HSB Up to 4 device specific masters can be measured Each of these masters is part of a measure ment channel Which masters that are connec...

Page 812: ...urements can be extracted by software and used to generate indicators for bus latency bus load and maximum bus latency Each of the counters have a fixed width and may therefore overflow When overflow...

Page 813: ...y register LAT0 Read 0x00000000 0x20 Channel1 Data Cycles register DATA1 Read 0x00000000 0x24 Channel1 Stall Cycles register STALL1 Read 0x00000000 0x28 Channel1 Max Initiation Latency register LAT1 R...

Page 814: ...it has no effect This bit always reads as zero CHnOF Channel Overflow Freeze 1 All channel n registers are frozen just before DATA or STALL overflows 0 The channel n registers are reset if DATA or STA...

Page 815: ...les Register Name DATAn Access Type Read Only Offset 0x10 n 0x10 Reset Value 0x00000000 DATA Data cycles counted since the last reset 31 30 29 28 27 26 25 24 DATA 31 24 23 22 21 20 19 18 17 16 DATA 23...

Page 816: ...Register Name STALLn Access Type Read Only Offset 0x14 n 0x10 Reset Value 0x00000000 STALL Stall cycles counted since the last reset 31 30 29 28 27 26 25 24 STALL 31 24 23 22 21 20 19 18 17 16 STALL...

Page 817: ...ffset 0x18 n 0x10 Reset Value 0x00000000 LAT This field is cleared whenever the DATA or STALL register is reset Maximum transfer initiation cycles counted since the last reset This counter is saturati...

Page 818: ...ss Type Read only Offset 0x50 Reset Value CHnIMP Channel Implementation 1 The corresponding channel is implemented 0 The corresponding channel is not implemented 31 30 29 28 27 26 25 24 23 22 21 20 19...

Page 819: ...only Offset 0x54 Reset Value VARIANT Variant Number Reserved No functionality associated VERSION Version Number Version number of the module No functionality associated 31 30 29 28 27 26 25 24 23 22...

Page 820: ...820 32072H AVR32 10 2012 AT32UC3A3 30 7 Module Configuration Table 30 2 Register Reset Values Register Reset Value VERSION 0x00000100 PARAMETER 0x0000000F...

Page 821: ...sters RSPRn data registers time out counters and error detection logic that automatically handle the transmission of com mands and when required the reception of the associated responses and data with...

Page 822: ...ation Block Diagram CMD CLK DATA I O controller DMA Controller MCI Interface Interrupt Control MCI Interrupt CLK_MCI Power Manager Peripheral Bus Peripheral Bus Brigde 1 2 3 4 5 6 MMC 7 1 9 2 3 4 5 7...

Page 823: ...s clock is enabled at reset and can be disabled in the Power Manager It is recommended to disable the MCI before disabling the clock to avoid freezing the MCI in an undefined state 31 5 4 Interrupt Th...

Page 824: ...MCI Pin Name 2 Slot z 1 DAT 3 I O PP Data DATAz 3 2 CMD I O PP OD Command response CMDz 3 VSS1 S Supply voltage ground VSS 4 VDD S Supply voltage VDD 5 CLK I O Clock CLK 6 VSS2 S Supply voltage ground...

Page 825: ...r Name Type 1 Description MCI Pin Name 2 Slot z 1 CD DAT 3 I O PP Card detect Data line Bit 3 DATAz 3 2 CMD PP Command response CMDz 3 VSS1 S Supply voltage ground VSS 4 VDD S Supply voltage VDD 5 CLK...

Page 826: ...col Each message is represented by one of the following tokens Command a command is a token that starts an operation A command is sent from the host either to a single card addressed command or to all...

Page 827: ...command follows on the CMD line similarly to the sequential read or when a multiple block transmission has a pre defined block count See Sec tion 31 6 3 on page 829 The MCI provides a set of register...

Page 828: ...ommand The MCI embeds an error detection to prevent any corrupted data during the transfer The following flowchart shows how to send a command to the card and read the response if needed In this examp...

Page 829: ...ted setting the Transfer Type field in the CMDR regis ter CMDR TRTYP These operations can be done using the features of the DMA Controller In all cases the Data Block Length must be defined either in...

Page 830: ...ot required at the end of this type of multiple block read or write unless terminated with an error In order to start a multiple block read or write with pre defined block count the host must correctl...

Page 831: ...ad with DMA Write a zero in the DMA DMAEN bit Write the BlockLenght in the MR BLKLEN field 2 Write the block count in the BLKR BCNT field if necessary Read data in the RDR register Number of words to...

Page 832: ...used when padding data otherwise 0xFF is used Write a one in the DMA Hardware Handshaking Enable bit in the DMA Configuration Register DMA DMAEN enables DMA transfer The following flowchart shows how...

Page 833: ...ngth 4 Number of words to write 0 No No Yes Read the SR register SR TXRDY 0 Write Data to transmit in the TDR register Number of words to write Number of words to write 1 RETURN RETURN Yes No Read the...

Page 834: ...ollowing flowchart shows how to manage a multiple write block transfer with the DMA Con troller see Figure 31 12 on page 835 Polling or interrupt method can be used to wait for the end of write accord...

Page 835: ...t the card Send SET_BLOCKLEN command 1 No Read the SR register SR BLKE 0 Enable the DMA channel X Write a zero in the DMA DMAEN bit Write the block lenght in the MR BLKLEN field 2 Write the block coun...

Page 836: ...XFRDONE bit is set 2 Write the block length in the card This value defines the value block_lenght 3 Write the MR BLKLEN with block_lenght value 4 Configure the DMA Channel in the DMA Controller 5 Wri...

Page 837: ...port SDIO can use small devices designed for the SD form factor such as GPS receivers Wi Fi or Bluetooth adapters modems barcode readers IrDA adapters FM radio tuners RFID readers digital cameras and...

Page 838: ...register space CE ATA utilizes five MMC commands GO_IDLE_STATE CMD0 used for hard reset STOP_TRANSMISSION CMD12 causes the ATA command currently executing to be aborted FAST_IO CMD39 Used for single r...

Page 839: ...TE CMD0 all device initialization needs to be completed again If the CE ATA device completes all MMC commands correctly but fails the ATA command with the ERR bit set in the ATA Status register no err...

Page 840: ...d enable the relevant channel 5 Issue the Boot Operation Request command by writing to the MCI_CMDR register with SPCND set to BOOTREQ TRDIR set to READ and TRCMD set to start data transfer 6 DMA cont...

Page 841: ...gister CMDR Write only 0x00000000 0x018 Block Register BLKR Read write 0x00000000 0x01C Completion Signal Time out Register CSTOR Read write 0x00000000 0x020 Response Register RSPR Read only 0x0000000...

Page 842: ...0x054 Configuration Register CFG Read write 0x00000000 0x0E4 Write Protection Mode Register WPMR Read write 0x00000000 0x0E8 Write Protection Status Register WPSR Read only 0x00000000 0x0FC Version Re...

Page 843: ...PWSEN Power Save Mode Enable Writing a one to this bit and a zero to PWSDIS will enable the Power Saving Mode Writing a one to this bit and a one to PWSDIS will disable the Power Saving Mode Writing a...

Page 844: ...blocks with a size different from modulo 4 can be supported Warning BLKLEN value depends on FBYTE Writing a one to this bit will enable the Force Byte Transfer Writing a zero to this bit will disable...

Page 845: ...Interface clock is divided by 2 PWSDIV 1 when entering Power Saving Mode Warning This value must be different from zero before enabling the Power Save Mode in the CR register CR PWSEN CLKDIV Clock Di...

Page 846: ...ual to DTOCYC x Multiplier If the data time out defined by DTOCYC and DTOMUL has been exceeded the Data Time out Error bit in the SR register SR DTOE is set DTOMUL Data Time out Multiplier Multiplier...

Page 847: ...t Value 0x00000000 SDCBUS SDCard SDIO Bus Width SDCSEL SDCard SDIO Slot 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SDCBUS SDCSEL SDCBUS BUS WIDTH 0 1 bit 1 R...

Page 848: ...RGR Access Type Read Write Offset 0x010 Reset Value 0x00000000 ARG 31 0 Command Argument this field contains the argument field of the command 31 30 29 28 27 26 25 24 ARG 31 24 23 22 21 20 19 18 17 16...

Page 849: ...ount of time defined with DTOMUL and DTOCYC fields located in the DTOR register If the acknowledge pattern is not received then an acknowledge timeout error is raised If the acknowledge pattern is cor...

Page 850: ...re the open drain command SPCMD Special Command TRTYP Transfer Type 0 MMC SDCard Single Block 1 MMC SDCard Multiple Block 2 MMC Stream 3 Reserved 4 SDIO Byte 5 SDIO Block others Reserved TRCMD Transfe...

Page 851: ...851 32072H AVR32 10 2012 AT32UC3A3 RSPTYP Response Type CMDNB Command Number The Command Number to transmit RSP Response Type 0 No response 1 48 bit response 2 136 bit response 3 R1b response type...

Page 852: ...s or block s to transfer The transfer data type and the authorized values for BCNT field are determined by CMDR TRTYP field Warning In SDIO Byte and Block modes writing to the seven last bits of BCNT...

Page 853: ...al The data transfer comprises data phase and the optional busy phase If a non DATA ATA command is issued the MCI starts waiting immediately after the end of the response until the completion signal I...

Page 854: ...04 Reset Value 0x00000000 RSP 31 0 Response The response register can be read by N access es at the same RSPRn or at consecutive addresses 0x20 n 0x04 N depends on the size of the response 31 30 29 28...

Page 855: ...ata Register Name RDR Access Type Read only Offset 0x030 Reset Value 0x00000000 DATA 31 0 Data to Read The last data received 31 30 29 28 27 26 25 24 DATA 31 24 23 22 21 20 19 18 17 16 DATA 23 16 15 1...

Page 856: ...Data Register Name TDR Access Type Write only Offset 0x034 Reset Value 0x00000000 DATA 31 0 Data to Write The data to send 31 30 29 28 27 26 25 24 DATA 31 24 23 22 21 20 19 18 17 16 DATA 23 16 15 14...

Page 857: ...ead This bit is cleared when sending a new data transfer command if CFG FERRCTRL is zero or when reading the SR register if CFG FERRCTRL is one XFRDONE Transfer Done This bit is set when the CR regist...

Page 858: ...rror This bit is set when a mismatch is detected between the command index sent and the response index received This bit is cleared when writing the CMDR register TXBUFE TX Buffer Empty Status This bi...

Page 859: ...ent data transfer is in progress This bit is cleared at the end of the CRC16 calculation 1 The current data transfer is still in progress 0 No data transfer in progress BLKE Data Block Ended This bit...

Page 860: ...has no effect Writing a one to a bit in this register will set the corresponding bit in IMR 31 30 29 28 27 26 25 24 UNRE OVRE ACKRCVE ACKRCV XFRDONE FIFOEMPTY DMADONE BLKOVRE 23 22 21 20 19 18 17 16 C...

Page 861: ...as no effect Writing a one to a bit in this register will clear the corresponding bit in IMR 31 30 29 28 27 26 25 24 UNRE OVRE ACKRCVE ACKRCV XFRDONE FIFOEMPTY DMADONE BLKOVRE 23 22 21 20 19 18 17 16...

Page 862: ...ter is cleared when the corresponding bit in IDR is written to one A bit in this register is set when the corresponding bit in IER is written to one 31 30 29 28 27 26 25 24 UNRE OVRE ACKRCVE ACKRCV XF...

Page 863: ...831 or Figure 31 11 on page 833 CHKSIZE DMA Channel Read and Write Chunk Size The CHKSIZE field indicates the number of data available when the DMA chunk transfer request is asserted OFFSET DMA Write...

Page 864: ...trol mode 1 When an underflow overflow condition bit is set reading SR resets the bit 0 When an underflow overflow condition bit is set a new Write Read command is needed to reset the bit FIFOMODE MCI...

Page 865: ...ield should be written at value 0x4D4349 ASCII code for MCI Writing any other value in this field has no effect WPEN Write Protection Enable 1 This bit enables the Write Protection if WPKEY correspond...

Page 866: ...21 20 19 18 17 16 WPVSRC 15 8 15 14 13 12 11 10 9 8 WPVSRC 7 0 7 6 5 4 3 2 1 0 WPVS WPVS Definition 0 No Write Protection Violation occurred since the last read of this register WPSR 1 Write Protecti...

Page 867: ...nly Offset 0x0FC Reset Value VARIANT Variant Number Reserved No functionality associated VERSION Version Number Version number of the module No functionality associate 31 30 29 28 27 26 25 24 23 22 21...

Page 868: ...emory Aperture Name Access Read Write Offset 0x200 0x3FFC Reset Value 0x000000000 DATA 31 0 Data to read or Data to write 31 30 29 28 27 26 25 24 DATA 31 24 23 22 21 20 19 18 17 16 DATA 23 16 15 14 13...

Page 869: ...lowing tables The module bus clocks listed here are connected to the system bus clocks according to the table in the Power Manager section Table 31 8 Module Clock Name Module name Clock name MCI CLK_M...

Page 870: ...rupt request When the protocol is started and enters the data transfer state data is requested by issuing a DMA transfer request via DMACA or an interrupt request to the CPU The RDY time out time when...

Page 871: ...nes The I O controller must be configured so that MSI can drive these I O lines 32 4 2 Power Manager MSI is clocked through the Power Manager PM thus programmer must first configure the PM to enable t...

Page 872: ...lock SCLK is maximum 20 MHz in serial mode and maxi mum 40 MHz in parallel mode SCLK is derived from peripheral clock CLK_MSI f_SCLK f_CLK_MSI 2 CLKDIV 1 where CLKDIV 0 255 Pin DATA 1 is a power suppl...

Page 873: ...END 1 MSINT 1 in IER Set FIFO direction to CPU to MS write FDIR 1 in SYS Write the command data to the FIFO write DAT Write the TPC and the data transfer size to the command register to start the prot...

Page 874: ...tes 1 3 Media Identification Process Set the Memory Stick to parallel interface mode by executing TPC commands SET_R W_REG_ADRS then WRITE_REG to set System Parameter bit PAM 1 Write SRAC 0 and REI 0...

Page 875: ...cally cleared when FIFO is accessed DMACA channel should be configured first and the data size should be a multiple of 64 bits FIFO size is 4 64bits 32 6 5 Interrupts The interrupt sources of MSI are...

Page 876: ...Memory Map Offset Register Name Access Reset State 0x0000 Command register CMD Read Write 0x00000000 0x0004 Data register DAT Read Write 0x4C004C00 0x0008 Status register SR Read Only 0x00001020 0x000...

Page 877: ...17 16 15 14 13 12 11 10 9 8 TPC DSL DSZ 7 6 5 4 3 2 1 0 DSZ code dec TPC Description 2 READ_LONG_DATA Transfer data from Data Buffer 512 bytes 3 READ_SHORT_DATA Transfer data from Data Buffer 32 256...

Page 878: ...878 32072H AVR32 10 2012 AT32UC3A3 1 Reserved DSZ Data size Length can be set from 1 byte to 1024 bytes However 1024 bytes is set when DSZ 0...

Page 879: ...Read Write Offset 0x04 Reset Value 0x4C004C00 This register is used to acces internal FIFO Even when the data is less than 8 bytes always read and write 8 bytes of data 31 30 29 28 27 26 25 24 DATA 2...

Page 880: ...1 FIFO is empty FUL FIFO Full This bit is cleared to 0 by writing system register bit FCLR 1 0 FIFO has empty space 1 FIFO is full CED MS Command End In parallel mode this bit reflects the CED bit in...

Page 881: ...access a Memory Sticks page buffer In serial mode this bit is always 0 It is cleared to 0 by writing to the command register CMD CNK MS Command No Acknowledge In parallel mode this bit reflects the C...

Page 882: ...C No CRC computation 0 Write 0 to enable CRC output During read protocol the CRC check is performed as usual regardless of NOCRC 1 Write 1 to disable CRC output When NOCRC 1 the write protocol is exec...

Page 883: ...llel communication This setting cannot be changed during protocol execution 0 Write 0 to synchronize outputs with the falling edge of SCLK 1 Write 1 to synchronize outputs with the rising edge of SCLK...

Page 884: ...esponding bit in ISCR is set to 1 1 This bit is set when protocol ends with CRC error MSINT Memory Stick interruption 0 This bit is cleared to 0 when the corresponding bit in ISCR is set to 1 1 This b...

Page 885: ...ing 0 has no effect 1 Writing 1 clears corresponding bit in ISR CRC CRC error clear bit 0 Writing 0 has no effect 1 Writing 1 clears corresponding bit in ISR MSINT Memory Stick interruption clear bit...

Page 886: ...in IMR CRC CRC error interrupt enable 0 Writing 0 has no effect 1 Writing 1 set to 1 corresponding bit in IMR MSINT Memory Stick interrupt enable 0 Writing 0 has no effect 1 Writing 1 set to 1 corresp...

Page 887: ...IMR CRC CRC error interrupt disable 0 Writing 0 has no effect 1 Writing 1 clears to 0 corresponding bit in IMR MSINT Memory Stick interrupt disable 0 Writing 0 has no effect 1 Writing 1 clears to 0 co...

Page 888: ...disabled 1 Interrupt is enabled CRC CRC error interrupt mask 0 Interrupt is disabled 1 Interrupt is enabled MSINT Memory Stick interrupt mask 0 Interrupt is disabled 1 Interrupt is enabled DRQ Data R...

Page 889: ...Offset 0x24 Reset Value 0x00000210 VARIANT Variant Number Reserved No functionality associated VERSION Version Number Version number of the module No functionality associated 31 30 29 28 27 26 25 24...

Page 890: ...ication The AES supports all five confidentiality modes of operation for symmetrical key block cipher algorithms ECB CBC OFB CFB and CTR as specified in the NIST Special Publication 800 38A Recommenda...

Page 891: ...bit 256 bit key is defined in the KEYWnR Registers KEYWnR The input to the encryption processes of the CBC CFB and OFB modes includes in addition to the plaintext a 128 bit data block called the init...

Page 892: ...nd may lead to errors in processing Note In 32 bit 16 bit and 8 bit CFB modes writing to IDATA2R IDATA3R and IDATA4R registers is not allowed and may lead to errors in processing Write the START bit i...

Page 893: ...address to write processed data Note Transmit and receive buffers can be identical Enable the DMA Controller in transmission and reception to start the processing The processing completion should be...

Page 894: ...ns When MR LOD is one The ISR DATRDY bit is cleared when at least one IDATAnR register is written so before the start of a new transfer No more ODATAnR register reads are necessary between consecutive...

Page 895: ...ults D M A C ontroller Interrupt M ultiple encryption or decryption processes Enable D M A C ontroller C hannels R eceive and Transm it C hannels Enable DMA Controller Channels only Transmit Channel I...

Page 896: ...Random Number Generator Seed Loading bit in the CR register CR LOADSEED allows a new seed to be loaded in the embedded random number generator used for the different countermeasures 33 4 4 2 Unspecifi...

Page 897: ...0000000 0x30 Key Word 5 Register KEYW5R Write only 0x00000000 0x34 Key Word 6 Register KEYW6R Write only 0x00000000 0x38 Key Word 7 Register KEYW7R Write only 0x00000000 0x3C Key Word 8 Register KEYW8...

Page 898: ...er generator used for the different countermeasures writing a zero to this bit has no effect SWRST Software Reset Writing a one to this bit will reset the AES writing a zero to this bit has no effect...

Page 899: ...CIPHER CTYPE Description X X X X 0 Countermeasure type 1 is disabled X X X X 1 Add random spurious power consumption during some configuration settings X X X 0 X Countermeasure type 2 is disabled X X...

Page 900: ...LOD mode Writing a zero to this bit will disabled the LOD mode These mode is described in the Table 33 3 on page 895 OPMOD Operation Mode KEYSIZE Key Size CFBS Description 0 128 bit 1 64 bit 2 32 bit...

Page 901: ...o 0 Writing a value to this field will update the processing time Reading this field will give the current processing delay CIPHER Processing Mode 0 Decrypts data is enabled 1 Encrypts data is enabled...

Page 902: ...Type Write only Offset 0x10 Reset Value 0x00000000 Writing a zero to a bit in this register has no effect Writing a one to a bit in this register will set the corresponding bit in IMR 31 30 29 28 27...

Page 903: ...Type Write only Offset 0x14 Reset Value 0x00000000 Writing a zero to a bit in this register has no effect Writing a one to a bit in this register will clear the corresponding bit in IMR 31 30 29 28 2...

Page 904: ...rresponding interrupt is disabled 1 The corresponding interrupt is enabled A bit in this register is cleared when the corresponding bit in IDR is written to one A bit in this register is set when the...

Page 905: ...ast one unspecified register access has been detected since the last software reset This bit is cleared when SWRST bit in the Control Register is set to one 31 30 29 28 27 26 25 24 23 22 21 20 19 18 1...

Page 906: ...906 32072H AVR32 10 2012 AT32UC3A3 DATRDY Data Ready This bit is set clear as described in the Table 33 3 on page 895 This bit is also cleared when SWRST bit in the Control Register is set to one...

Page 907: ...aphic key used for encryption decryption in the four six eight 32 bit Key Word registers KEYW1 corresponds to the first word of the key and respectively KEYW4 KEYW6 KEYW8 to the last one This field al...

Page 908: ...used for encryption decryption in the four 32 bit Input Data registers IDATA1 corresponds to the first word of the data to be encrypted decrypted and IDATA4 to the last one This field always read as...

Page 909: ...lue 0x00000000 ODATAn 31 0 Output Data n Reading the four 32 bit ODATAnR give the 128 bit data block that has been encrypted decrypted ODATA1 corresponds to the first word ODATA4 to the last one 31 30...

Page 910: ...s used by some modes of operation as an additional initial input IV1 corresponds to the first word of the Initialization Vector IV4 to the last one This field is always read as zero to prevent the Ini...

Page 911: ...Read only Offset 0xFC Reset Value VARIANT Variant Number Reserved No functionality associated VERSION 11 0 Version number of the module No functionality associated 31 30 29 28 27 26 25 24 23 22 21 20...

Page 912: ...is listed in the following tables The module bus clocks listed here are connected to the system bus clocks according to the table in the System Bus Clock Connections section Table 33 5 Module clock na...

Page 913: ...ANn should be as ideal as possible before filtering to achieve the best SNR and THD quality The outputs can be connected to a class D amplifier output stage to drive a speaker directly or it can be lo...

Page 914: ...configured in order for the Audio Bitstream DAC I O lines to be in Audio Bitstream DAC peripheral mode Table 34 1 I O Lines Description Pin Name Pin Description Type DATA0 Output from Audio Bitstream...

Page 915: ...34 5 on page 914 must be resolved Particular attention should be given to the configuration of clocks and I O lines in order to ensure correct operation of the Audio Bitstream DAC The Audio Bitstream...

Page 916: ...filter Comb4 before being applied to the Sigma Delta Modulator In order to compensate for the pass band frequency response of the interpolation filter and flatten the overall frequency response the i...

Page 917: ...2072H AVR32 10 2012 AT32UC3A3 34 6 9 Frequency Response Figure 34 2 Frequency Response EQ FIR COMB4 0 1 2 3 4 5 6 7 8 9 1 0 x 1 0 4 6 0 5 0 4 0 3 0 2 0 1 0 0 1 0 F r e q u e n c y F s A m p l i t u d...

Page 918: ...ter SDR Read Write 0x00000000 0x08 Control Register CR Read Write 0x00000000 0x0C Interrupt Mask Register IMR Read only 0x00000000 0x10 Interrupt Enable Register IER Write only 0x00000000 0x14 Interru...

Page 919: ...e 0x00000000 CHANNEL1 Sample Data for Channel 1 signed 16 bit Sample Data for channel 1 CHANNEL0 Signed 16 bit Sample Data for Channel 0 signed 16 bit Sample Data for channel 0 31 30 29 28 27 26 25 24...

Page 920: ...0x00000000 EN Enable Audio Bitstream DAC 1 The module is enabled 0 The module is disabled SWAP Swap Channels 1 The swap of CHANNEL0 and CHANNEL1 samples is enabled 0 The swap of CHANNEL0 and CHANNEL1...

Page 921: ...sponding interrupt is enabled 0 The corresponding interrupt is disabled A bit in this register is set when the corresponding bit in IER is written to one A bit in this register is cleared when the cor...

Page 922: ...ype Write only Offset 0x10 Reset Value 0x00000000 Writing a one to a bit in this register will set the corresponding bit in IMR Writing a zero to a bit in this register has no effect 31 30 29 28 27 26...

Page 923: ...pe Write only Offset 0x14 Reset Value 0x00000000 Writing a one to a bit in this register will clear the corresponding bit in IMR Writing a zero to a bit in this register has no effect 31 30 29 28 27 2...

Page 924: ...0x18 Reset Value 0x00000000 Writing a one to a bit in this register will clear the corresponding bit in ISR and the corresponding interrupt request Writing a zero to a bit in this register has no effe...

Page 925: ...o Bitstream DAC is not ready to receive a new data in SDR UNDERRUN Underrun Interrupt Status This bit is set when at least one Audio Bitstream DAC Underrun has occurred since the last time this bit wa...

Page 926: ...fic instructions The Service Access Bus uses 36 address bits to address memory or registers in any of the slaves on the bus The bus supports sized accesses of bytes 8 bits halfwords 16 bits or words 3...

Page 927: ...t set Programming and debugging not possible very restricted access User code programming FLASHC UPROT security bit set Restricts all access except parts of the flash and the flash controller for prog...

Page 928: ...AUX port is primarily used for trace functions and a JTAG based debugger is sufficient for basic debugging The debug system is based on the Nexus 2 0 standard class 2 which includes Basic run time co...

Page 929: ...on output on the AUX port allowing a JTAG based debugger to be used A JTAG based debugger should connect to the device through a standard 10 pin IDC connector as described in the AVR32UC Technical Ref...

Page 930: ...onditional breakpoints are set by writing OCD registers by JTAG halting the CPU immediately Program breakpoints halt the CPU when a specific address in the program is executed Data breakpoints halt th...

Page 931: ...con trolled through a dedicated set of registers addressed through the MEMORY_SERVICE JTAG command 35 3 5 1 Cyclic Redundancy Check CRC The MSU can be used to automatically calculate the CRC of a bloc...

Page 932: ...by writing OCD registers by JTAG The OCD extracts the trace infor mation from the CPU compresses this information and formats it into variable length messages according to the Nexus standard The messa...

Page 933: ...register which produces an Ownership Trace Message allowing the debug ger to switch context for the subsequent program and data trace messages As the use of this feature depends on the software runni...

Page 934: ...identified and optimized Program trace must be used to accomplish these tasks without instrumenting altering the code to be examined However traditional program trace cannot reconstruct the current PC...

Page 935: ...ter or one of several Data Registers as the scan chain shift register between the TDI input and TDO output The Instruction Register holds JTAG instructions controlling the behavior of a Data Register...

Page 936: ...k frequency Input TMS Test Mode Select sampled on rising TCK Input TDI Test Data In sampled on rising TCK Input TDO Test Data Out driven on falling TCK Output 32 bit AVR device JTAG data registers TAP...

Page 937: ...ble 35 6 on page 936 The TMS control line navigates the TAP controller as shown in Figure 35 5 on page 938 The TAP controller manages the serial access to the JTAG Instruction and Data registers Data...

Page 938: ...ller State Diagram Test Logic Reset Run Test Idle Select DR Scan Select IR Scan Capture DR Capture IR Shift DR Shift IR Exit1 DR Exit1 IR Pause DR Pause IR Exit2 DR Exit2 IR Update DR Update IR 0 1 1...

Page 939: ...description of these The TMS input must be held low during input of the 4 LSBs in order to remain in the Shift IR state The JTAG Instruction selects a particular Data Register as path between TDI and...

Page 940: ...nal software may be in an undetermined state when exiting the test mode If needed the BYPASS instruction can be issued to make the shortest possible scan chain through the device The device can be set...

Page 941: ...SAB access JTAG instructions can return a busy indicator This indicates whether a delay needs to be inserted or an operation needs to be repeated in order to be suc cessful If a new access is requeste...

Page 942: ...peration failed The new data is accepted and a write operation started This should only occur during block writes or stream writes No error can occur between scanning a write address and the following...

Page 943: ...ct boundary scan chain as data register for testing circuitry external to the device 0x04 INTEST Select boundary scan chain for internal testing of the device 0x06 CLAMP Bypass device through Bypass r...

Page 944: ...ays reads as one a An address bit always scanned with the least significant bit first b A busy bit Reads as one if the SAB was busy or zero if it was not See Section 35 4 10 4 for details on how the b...

Page 945: ...t Idle 35 5 2 2 SAMPLE_PRELOAD This instruction takes a snap shot of the input output pins without affecting the system operation and pre loading the scan chain without updating the DR latch The bound...

Page 946: ...lue is latched into the shift register 3 In Shift IR The instruction register is shifted by the TCK input 4 In Update IR The data from the boundary scan chain is applied to the output pins 5 Return to...

Page 947: ...ed by the TCK input 9 In Update DR The data from the boundary scan chain is applied to internal logic inputs 10 Return to Run Test Idle 35 5 2 5 CLAMP This instruction selects the Bypass register as D...

Page 948: ...h instruction is briefly described in text with details following in table form 35 5 3 1 NEXUS_ACCESS This instruction allows Nexus compliant access to the On Chip Debug registers through the SAB The...

Page 949: ...is accessed through the JTAG port The data register is alternately interpreted by the SAB as an address register and a data regis ter The SAB starts in address mode after the MEMORY_SERVICE instructio...

Page 950: ...mapped on the SAB bus may support all sizes of accesses e g some may only support word accesses The data register is alternately interpreted by the SAB as an address register and a data regis ter The...

Page 951: ...defined For read operations shifting may be termi nated once the required number of bits have been acquired Table 35 18 Size Field Semantics Size field value Access size Data alignment 00 Byte 8 bits...

Page 952: ...turn to Run Test Idle 5 Select the DR Scan path 6 In Shift DR Scan in the direction bit 1 read 0 write and the 34 bit address of the data to access 7 Go to Update DR and re enter Select DR Scan 8 In S...

Page 953: ...put value is latched into the shift register 5 In Shift IR The instruction register is shifted by the TCK input 6 Return to Run Test Idle 7 Select the DR Scan path The address will now have incremente...

Page 954: ...is latched into the shift register 3 In Shift IR The instruction register is shifted by the TCK input 4 Return to Run Test Idle 35 5 3 7 SYNC This instruction allows external debuggers and testers to...

Page 955: ...leases the reset for that domain The AVR_RESET instruction can be used in the following way 1 Select the IR Scan path 2 In Capture IR The IR output value is latched into the shift register 3 In Shift...

Page 956: ...t was set goto 2 6 Return to Run Test Idle 35 5 3 10 HALT This instruction allows a programmer to easily stop the CPU to ensure that it does not execute invalid code during programming This instructio...

Page 957: ...Shift DR Scan in the value 1 to halt the CPU 0 to start CPU execution 7 Return to Run Test Idle Table 35 26 HALT Details Instructions Details IR input value 11100 0x1C IR output value p0001 DR Size 1...

Page 958: ...27 Note that if the flash controller is statically reset the ID code will be undefined MSB LSB Bit 31 28 27 12 11 1 0 Device ID Revision Part Number Manufacturer ID 1 4 bits 16 bits 11 bits 1 bit Revi...

Page 959: ...1 or 0x00000 to these bits to ensure no unintended side effects occur 35 5 4 3 Boundary Scan Chain The Boundary Scan Chain has the capability of driving and observing the logic levels on the dig ital...

Page 960: ...of the device at these or other conditions beyond those indicated in the operational sections of this specification is not implied Exposure to absolute maximum rating conditions for extended periods...

Page 961: ...x0 7 VVDDIO 0 5 V RESET_N TCK TDI 0 8V V VIH Input High level Voltage All I O pins except TWCK TWD 2 0 3 6 V TWCK TWD V VOL Output Low level Voltage IOL 2mA for Pin drive x1 IOL 4mA for Pin drive x2 I...

Page 962: ...I O Pin drive x2 Output High Level Voltage VOH vs Source Current 36 3 I O pin Characteristics These parameters are given in the following conditions VDDCORE 1 8V VDDIO 3 3V Ambient Temperature 25 C Vd...

Page 963: ...me 10pf 3 2 1 7 0 9 ns 30pf 8 6 4 3 2 26 ns 60pf 16 5 8 3 4 3 ns Table 36 3 Electrical Characteristics Symbol Parameter Conditions Min Typ Max Unit VVDDIN Supply voltage input 3 0 3 3 3 6 V VVDDCORE S...

Page 964: ...3 0 3 6 V Table 36 6 Decoupling Requirements Symbol Parameter Conditions Typ Technology Unit CVDDANA Power Supply Capacitor 100 NPO nF Table 36 7 1 8V BOD Level Values Symbol Parameter Value Conditio...

Page 965: ...voltage voltage up to which device is kept under reset by POR on rising VDDIN Rising VDDIN VRESTART VPOR 2 7 V VPOR Falling threshold voltage voltage when POR resets device on falling VDDIN Falling VD...

Page 966: ...ernally Driven Figure 36 5 MCU Hot Start Up VBOD33LEVEL VDDIN VDDIO Internal MCU Reset TSSU1 Internal BOD33 Reset RESET_N VRESTART VBOD33LEVEL VBOD33LEVEL VDDIN VDDIO Internal MCU Reset TSSU1 Internal...

Page 967: ...967 32072H AVR32 10 2012 AT32UC3A3 36 5 4 RESET_N Characteristics Table 36 11 RESET_N Waveform Parameters Symbol Parameter Conditions Min Typ Max Unit tRESET RESET_N minimum pulse width 10 ns...

Page 968: ...asured values of power con sumption with operating conditions as follows VDDIO 3 3V TA 25 C I Os are configured in input pull up enabled Figure 36 6 Measurement Setup These figures represent the power...

Page 969: ...Flash High Speed mode enable 66 f 84 MHz 0 670xf MHz 2 257 mA MHz Same conditions with Flash High Speed mode disable at 60 MHz 40 mA Idle See Active mode conditions 0 349xf MHz 0 968 mA MHz Same condi...

Page 970: ...able 36 13 Typical Cuurent Consumption by Peripheral Peripheral Typ Unit ADC 7 A MHz AES 80 ABDAC 10 DMACA 70 EBI 23 EIC 0 5 GPIO 37 INTC 3 MCI 40 MSI 10 PDCA 20 SDRAM 5 SMC 9 SPI 6 SSC 10 RTC 5 TC 8...

Page 971: ...equency 40 C Ambient Temperature 70 C 84 MHz 1 tCPCPU CPU Clock Frequency 40 C Ambient Temperature 85 C 66 MHz Table 36 15 PBA Clock Waveform Parameters Symbol Parameter Conditions Min Typ Max Unit 1...

Page 972: ...RC RC Oscillator Frequency Calibration point TA 85 C 115 2 116 KHz TA 25 C 112 KHz TA 40 C 105 108 KHz Table 36 18 32 KHz Oscillator Characteristics Symbol Parameter Conditions Min Typ Max Unit 1 tCP3...

Page 973: ...4 tCP 0 6 tCP CIN XIN Input Capacitance 7 pF IOSC Current Consumption Active mode at 400 KHz Gain G0 Active mode at 8 MHz Gain G1 Active mode at 16 MHz Gain G2 Active mode at 20 MHz Gain G3 30 45 95...

Page 974: ...time and 10 clock cycles for conversion kSPS Table 36 23 ADC Power Consumption Parameter Conditions Min Typ Max Unit Current Consumption on VDDANA 1 1 Including internal reference input current On 13...

Page 975: ...x Unit REXT Recommended External USB Series Resistor In series with each USB pin with 5 39 RBIAS VBIAS External Resistor 1 1 The USB on chip buffers comply with the Universal Serial Bus USB v2 0 stand...

Page 976: ...ble 1 4 6 mA FS HS Transceiver current consumption FS transmission 5m cable 26 30 mA FS HS Transceiver current consumption FS reception 3 4 5 mA 1 Including 1 mA due to Pull up Pull down current consu...

Page 977: ...to NBS0 A0 Change 1 nrd hold length tCPSMC 1 3 ns SMC4 NRD High to NBS1 Change 1 nrd hold length tCPSMC 1 3 ns SMC5 NRD High to NBS2 A1 Change 1 nrd hold length tCPSMC 1 3 ns SMC7 NRD High to A2 A23...

Page 978: ...ld length tCPSMC 1 9 ns SMC26 NWE High to NBS1 Change 1 nwe hold length tCPSMC 1 9 ns SMC29 NWE High to A1 Change 1 nwe hold length tCPSMC 1 9 ns SMC31 NWE High to A2 A23 Change 1 nwe hold length tCPS...

Page 979: ...id after NWE Rising 5 ns SMC45 NWE Pulse Width nwe pulse length tCPSMC 0 9 ns Table 36 34 SMC Write Signals with No Hold Settings NWE Controlled only Symbol Parameter Min Unit NRD NCS D0 D15 NWE A2 A2...

Page 980: ...ol Parameter Conditions Min Max 1 Unit 1 tCPSDCK SDRAM Controller Clock Frequency 1 tcpcpu MHz Table 36 36 SDRAM Clock Signal Symbol Parameter Conditions Min Max Unit SDRAMC1 SDCKE High before SDCK Ri...

Page 981: ...DCK Rising Edge 6 4 ns SDRAMC18 DQM Change after SDCK Rising Edge 2 2 ns SDRAMC19 D0 D15 in Setup before SDCK Rising Edge 9 ns SDRAMC20 D0 D15 in Hold after SDCK Rising Edge 0 ns SDRAMC23 SDWE Low bef...

Page 982: ...S SDRAMC5 SDRAMC6 SDRAMC5 SDRAMC6 SDRAMC5 SDRAMC6 SDRAMC7 SDRAMC8 CAS SDRAMC15 SDRAMC16 SDRAMC15 SDRAMC16 SDWE SDRAMC23 SDRAMC24 SDRAMC9 SDRAMC10 SDRAMC9 SDRAMC10 SDRAMC9 SDRAMC10 SDRAMC11 SDRAMC12 SD...

Page 983: ...mum external capacitor 40pF Min Max Unit JTAG0 TCK Low Half period 6 ns JTAG1 TCK High Half period 3 ns JTAG2 TCK Period 9 ns JTAG3 TDI TMS Setup before TCK High 1 ns JTAG4 TDI TMS Hold after TCK High...

Page 984: ...G Interface Signals 36 13 SPI Characteristics Figure 36 11 SPI Master mode with CPOL NCPHA 0 or CPOL NCPHA 1 TCK JTAG9 TMS TDI TDO Device Outputs JTAG5 JTAG4 JTAG3 JTAG 0 JTAG1 JTAG2 JTAG10 Device Inp...

Page 985: ...CPOL 0 and NCPHA 1 or CPOL 1 and NCPHA 0 Figure 36 13 SPI Slave mode with CPOL 0 and NCPHA 1 or CPOL 1 and NCPHA 0 Figure 36 14 SPI Slave mode with CPOL NCPHA 0 or CPOL NCPHA 1 SPCK MISO MOSI SPI5 SPI...

Page 986: ...time after SPCK rises master 3 3V domain 0 ns SPI2 SPCK rising to MOSI Delay master 3 3V domain 7 ns SPI3 MISO Setup time before SPCK falls master 3 3V domain 22 tCPMCK 2 3 3 tCPMCK Master Clock perio...

Page 987: ...Read Mode Disable 40 C Ambient Temperature 85 C 36 MHz FWS 1 High Speed Read Mode Disable 40 C Ambient Temperature 85 C 66 MHz FWS 0 High Speed Read Mode Enable 40 C Ambient Temperature 70 C 42 MHz FW...

Page 988: ...ed in the section Regulator characteristics on page 963 TA ambient temperature C From the first equation the user can derive the estimated lifetime of the chip and decide if a cooling device is necess...

Page 989: ...989 32072H AVR32 10 2012 AT32UC3A3 37 2 Package Drawings Figure 37 1 TFBGA 144 package drawing...

Page 990: ...ure 37 2 LQFP 144 package drawing Table 37 2 Device and Package Maximum Weight 1300 mg Table 37 3 Package Characteristics Moisture Sensitivity Level MSL3 Table 37 4 Package Reference JEDEC Drawing Ref...

Page 991: ...991 32072H AVR32 10 2012 AT32UC3A3 Figure 37 3 VFBGA 100 package drawing...

Page 992: ...um of three reflow passes is allowed per component Table 37 5 Soldering Profile Profile Feature Green Package Average Ramp up Rate 217 C to Peak 3 C Second max Preheat Temperature 175 C 25 C 150 200 C...

Page 993: ...rial 40 C to 85 C AT32UC3A364S AT32UC3A364S ALUT 144 lead LQFP Tray Industrial 40 C to 85 C AT32UC3A364S ALUR 144 lead LQFP Reels Industrial 40 C to 85 C AT32UC3A364S CTUT 144 ball TFBGA Tray Industri...

Page 994: ...ng of R12 Fix Workaround None Hardware breakpoints may corrupt MAC results Hardware breakpoints on MAC instructions may corrupt the destination register of the MAC instruction Fix Workaround Place bre...

Page 995: ...the transfer whenever the PDCA transfer is ready The LINID interrupt is only available for the header reception and not available for the header transmission Fix Workaround None USART LIN mode is not...

Page 996: ...C32CTRL MODE 0 is not affected Fix Workaround None Clock sources will not be stopped in STATIC sleep mode if the difference between CPU and PBx division factor is too high If the division factor betwe...

Page 997: ...the TWIM there must be a software delay of at least two TWCK periods between the detection of SR IDLE 1 and the disabling of the TWIM TWIM TWALM polarity is wrong The TWALM signal in the TWIM is acti...

Page 998: ...ase operation enable the flash high speed mode FLASHC HSEN command The flash fuse write or erase operations FLASHC LP UP WGPB EGPB SSB PGPFB EAGPF commands must be issued from RAM or through the EBI A...

Page 999: ...MAC results Hardware breakpoints on MAC instructions may corrupt the destination register of the MAC instruction Fix Workaround Place breakpoints on earlier or later instructions When the main clock i...

Page 1000: ...PDCA if PDCM bit in LINMR register is set to 1 If a PDCA transfer is initiated in USART LIN mode with PDCM bit set to 1 the transfer never starts Fix Workaround Only use PDCM 0 configuration with the...

Page 1001: ...mand is filtered when SPI is disabled Writing to TDR when SPI is disabled will not clear SR TDRE If SPI is disabled during a PDCA transfer the PDCA will continue to write data to TDR until its buffer...

Page 1002: ...39 2 6 TWIM TWIM SR IDLE goes high immediately when NAK is received When a NAK is received and there is a non zero number of bytes to be transmitted SR IDLE goes high immediately and does not wait fo...

Page 1003: ...R1b for the com mands CMD12 Fix Workaround The card busy line should be polled through the GPIO Input Value register IVR for com mands CMD12 SSC Frame Synchro and Frame Synchro Data are delayed by one...

Page 1004: ...in the register list and without increments Rp For LDM with PC in the register list the instruction behaves as if the field is always set ie the pointer is always updated This happens even if the fiel...

Page 1005: ...Multiply instructions do not work on RevD All the multiply instructions do not work Fix Workaround Do not use the multiply instructions MPU Privilege violation when using interrupts in application mo...

Page 1006: ...ut should go high but it will stay low Fix Workaround Do not use the hardware handshaking mode of the USART If it is necessary to drive the RTS output high when the Peripheral DMA receive buffer becom...

Page 1007: ...present on XIN32 XOUT32 pins OSC32RDY bit may still set even if the CLK32 is not active External clock mode OSC32CTRL MODE 0 is not affected Fix Workaround None Clock sources will not be stopped in S...

Page 1008: ...and then immediately disables the TWIM by writing a one to CR MDIS Disabling the TWIM causes the TWCK and TWD pins to go high immediately so the STOP condition will not be transmitted correctly Fix Wo...

Page 1009: ...en after fuses write or erase operations FLASHC LP UP WGPB EGPB SSB PGPFB EAGPF commands After a flash fuse write or erase operation FLASHC LP UP WGPB EGPB SSB PGPFB EAGPF commands reading data read o...

Page 1010: ...s accordingly to new max frequency 4 Fixed wrong description of PLLOPT 0 in PM chapter 5 Updated Errata section according to new maximum frequency 6 Added USB hi speed PLL electrical characteristics 7...

Page 1011: ...1011 32072H AVR32 10 2012 AT32UC3A3 40 7 Rev B 08 09 40 8 Rev A 03 09 1 Updated the datasheet with new device AT32UC3A4 1 Initial revision...

Page 1012: ...re 21 4 1 Features 21 4 2 AVR32 Architecture 21 4 3 The AVR32UC CPU 22 4 4 Programming Model 26 4 5 Exceptions and Interrupts 30 4 6 Module Configuration 34 5 Memories 35 5 1 Embedded Memories 35 5 2...

Page 1013: ...0 Interrupt Controller INTC 96 10 1 Features 96 10 2 Overview 96 10 3 Block Diagram 96 10 4 Product Dependencies 97 10 5 Functional Description 97 10 6 User Interface 100 10 7 Interrupt Request Signal...

Page 1014: ...cription 149 13 5 User Interface 153 13 6 Bus Matrix Connections 161 14 External Bus Interface EBI 163 14 1 Features 163 14 2 Overview 163 14 3 Block Diagram 164 14 4 I O Lines Description 165 14 5 Pr...

Page 1015: ...troller PDCA 281 18 1 Features 281 18 2 Overview 281 18 3 Block Diagram 282 18 4 Product Dependencies 282 18 5 Functional Description 283 18 6 Performance Monitors 285 18 7 User Interface 286 18 8 Mod...

Page 1016: ...Diagram 405 21 4 Application Block Diagram 405 21 5 I O Lines Description 406 21 6 Product Dependencies 406 21 7 Functional Description 406 21 8 User Interface 417 21 9 Module Configuration 443 22 Two...

Page 1017: ...on 510 24 6 Product Dependencies 510 24 7 Functional Description 510 24 8 SSC Application Examples 522 24 9 User Interface 524 25 Universal Synchronous Asynchronous Receiver Transmitter USART 546 25 1...

Page 1018: ...790 29 1 Features 790 29 2 Overview 790 29 3 Block Diagram 791 29 4 I O Lines Description 791 29 5 Product Dependencies 791 29 6 Functional Description 792 29 7 User Interface 797 29 8 Module Configu...

Page 1019: ...890 33 2 Overview 890 33 3 Product Dependencies 890 33 4 Functional Description 891 33 5 User Interface 897 33 6 Module Configuration 912 34 Audio Bitstream DAC ABDAC 913 34 1 Features 913 34 2 Overvi...

Page 1020: ...Timings 977 36 12 JTAG Characteristics 983 36 13 SPI Characteristics 984 36 14 MCI 986 36 15 Flash Memory Characteristics 987 37 Mechanical Characteristics 988 37 1 Thermal Considerations 988 37 2 Pac...

Page 1021: ...SET FORTH IN THE ATMEL TERMS AND CONDITIONS OF SALES LOCATED ON THE ATMEL WEBSITE ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCT...

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