510
32072H–AVR32–10/2012
AT32UC3A3
24.5
I/O Lines Description
24.6
Product Dependencies
In order to use this module, other parts of the system must be configured correctly, as described
below.
24.6.1
I/O Lines
The pins used for interfacing the compliant external devices may be multiplexed with I/O lines.
Before using the SSC receiver, the I/O Controller must be configured to dedicate the SSC
receiver I/O lines to the SSC peripheral mode.
Before using the SSC transmitter, the I/O Controller must be configured to dedicate the SSC
transmitter I/O lines to the SSC peripheral mode.
24.6.2
Clocks
The clock for the SSC bus interface (CLK_SSC) is generated by the Power Manager. This clock
is enabled at reset, and can be disabled in the Power Manager. It is recommended to disable the
SSC before disabling the clock, to avoid freezing the SSC in an undefined state.
24.6.3
Interrupts
The SSC interrupt request line is connected to the interrupt controller. Using the SSC interrupt
requires the interrupt controller to be programmed first.
24.7
Functional Description
This chapter contains the functional description of the following: SSC functional block, clock
management, data framing format, start, transmitter, receiver, and frame sync.
The receiver and the transmitter operate separately. However, they can work synchronously by
programming the receiver to use the transmit clock and/or to start a data transfer when transmis-
sion starts. Alternatively, this can be done by programming the transmitter to use the receive
clock and/or to start a data transfer when reception starts. The transmitter and the receiver can
be programmed to operate with the clock signals provided on either the TX_CLOCK or
RX_CLOCK pins. This allows the SSC to support many slave-mode data transfers. The maxi-
mum clock speed allowed on the TX_CLOCK and RX_CLOCK pins is CLK_SSC divided by two.
Table 24-1.
I/O Lines Description
Pin Name
Pin Description
Type
RX_FRAME_SYNC
Receiver Frame Synchro
Input/Output
RX_CLOCK
Receiver Clock
Input/Output
RX_DATA
Receiver Data
Input
TX_FRAME_SYNC
Transmitter Frame Synchro
Input/Output
TX_CLOCK
Transmitter Clock
Input/Output
TX_DATA
Transmitter Data
Output
Summary of Contents for AT32UC3A3128
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Page 989: ...989 32072H AVR32 10 2012 AT32UC3A3 37 2 Package Drawings Figure 37 1 TFBGA 144 package drawing...
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