Atmel AT32UC3A3128, Manual

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32072H–AVR32–10/2012
AT32UC3A3
35.3 On-Chip Debug (OCD)
Rev: 1.4.2.1
35.3.1 Features
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Debug interface in compliance with IEEE-ISTO 5001-2003 (Nexus 2.0) Class 2+
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JTAG access to all on-chip debug functions
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Advanced program, data, ownership, and watchpoint trace supported
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NanoTrace JTAG-based trace access
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Auxiliary port for high-speed trace information
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Hardware support for 6 program and 2 data breakpoints
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Unlimited number of software breakpoints supported
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Automatic CRC check of memory regions
35.3.2 Overview
Debugging on the AT32UC3A3 is facilitated by a powerful On-Chip Debug (OCD) system. The
user accesses this through an external debug tool which connects to the JTAG port and the Aux-
iliary (AUX) port. The AUX port is primarily used for trace functions, and a JTAG-based
debugger is sufficient for basic debugging.
The debug system is based on the Nexus 2.0 standard, class 2+, which includes:
• Basic run-time control
• Program breakpoints
• Data breakpoints
• Program trace
• Ownership trace
• Data trace
In addition to the mandatory Nexus debug features, the AT32UC3A3 implements several useful
OCD features, such as:
• Debug Communication Channel between CPU and JTAG
• Run-time PC monitoring
• CRC checking
• NanoTrace
• Software Quality Assurance (SQA) support
The OCD features are controlled by OCD registers, which can be accessed by JTAG when the
NEXUS_ACCESS JTAG instruction is loaded. The CPU can also access OCD registers directly
using mtdr/mfdr instructions in any privileged mode. The OCD registers are implemented based
on the recommendations in the Nexus 2.0 standard, and are detailed in the AVR32UC Technical
Reference Manual.