Atmel AT32UC3A3128, Manual

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873
32072H–AVR32–10/2012
AT32UC3A3
32.6 Functional Description
32.6.1 Reset Operation
An internal reset (initialization of the internal registers and operating sequence) is performed
when PB reset is active or by setting SYS.RST=1. RST bit is cleared to 0 after the internal reset
is completed.
The protocol currently being executed stops, and the internal operating sequence is initialized.
In addition, the FIFO is set to the empty state (SR.EMP=1, SR.FUL=0).
However, when the host controller is reset during communication with the Memory Stick, the
resulting bus state may differ from the Memory Stick. Therefore, when reset is performed during
communication, also power-on-reset the Memory Stick.
Internal registers are initialized to their initial value. However, some bits in following registers are
not affected by RST bit :
• SYS : CLKDIV[7:0],
• ISR : all bits but DRQ,
• SR : ISTA,
• IMR : all bits.
32.6.2 Communication with the Memory Stick
An example of communication with the Memory Stick is shown below. This example shows the
case when Transfer Protocol Command (TPC) SET_CMD is executed.
– Enable PEND and MSINT interrupt requests (write PEND=1, MSINT=1 in IER).
– Set FIFO direction to “CPU to MS” (write FDIR=1 in SYS).
– Write the command data to the FIFO (write DAT).
– Write the TPC and the data transfer size to the command register to start the
protocol (write CMD).
– After the protocol ends, an interrupt request is output from the host controller
(PEND=1 in ISR). To acknowledge this interrupt request, CPU must clear the source
of interrupt by writing PEND=1 in ISCR.
– Some TPC commands require additional time to be executed by Memory Stick
therefore INT can appear later after protocol end. After INT generation, an interrupt
request is output from the host controller (MSINT=1 in ISR). To acknowledge this
interrupt request, CPU must clear the source of interrupt by writing MSINT=1 in
ISCR.
When the command register is written, the communication protocol with the Memory Stick starts
and data transmit/receive is performed.
The data transfer direction is determined from TPC[3]. When TPC[3]=0, the read protocol is per-
formed, and when TPC[3]=1, the write protocole is performed. When TPC[3] and FDIR bit differ,
the TPC[3] value is reflected to system register bit FDIR when the protocol starts.
FIFO can be written after protocol start therefore data must be written each time ISR.DRQ=1.
Even when the data is less than 8 bytes, always read and write 8 bytes of data. All interrupt