183
32072H–AVR32–10/2012
AT32UC3A3
Figure 15-6. Connection of two 8-bit Devices on a 16-bit Bus: Byte Write Option
•Signal multiplexing
Depending on the MODE.BAT bit, only the write signals or the byte select signals are used. To
save I/Os at the external bus interface, control signals at the SMC interface are multiplexed.
For 16-bit devices, bit A0 of address is unused. When byte select option is selected, NWR1 is
unused. When byte write option is selected, NBS0 to NBS1 are unused.
Table 15-3.
SMC Multiplexed Signal Translation
15.6.4
Standard Read and Write Protocols
In the following sections, the byte access type is not considered. Byte select lines (NBS0 to
NBS1) always have the same timing as the address bus (A). NWE represents either the NWE
signal in byte select access type or one of the byte write lines (NWR0 to NWR1) in byte write
SMC
A1
NWR0
NRD
NCS[3]
Write Enable
Read Enable
Memory Enable
NWR1
Write Enable
Read Enable
Memory Enable
D[7:0]
D[7:0]
D[15:8]
D[15:8]
A[24:2]
A[23:1]
A[23:1]
A[0]
A[0]
Signal Name
16-bit Bus
8-bit Bus
Device Type
1 x 16-bit
2 x 8-bit
1 x 8-bit
Byte Access Type (BAT)
Byte Select
Byte Write
NBS0_A0
NBS0
A0
NWE_NWR0
NWE
NWR0
NWE
NBS1_NWR1
NBS1
NWR1
NBS2_NWR2_A1
A1
A1
A1
Summary of Contents for AT32UC3A3128
Page 61: ...61 32072H AVR32 10 2012 AT32UC3A3 PLLEN PLL Enable 0 PLL is disabled 1 PLL is enabled...
Page 592: ...592 32072H AVR32 10 2012 AT32UC3A3 Manchester Configuration Register on page 614...
Page 989: ...989 32072H AVR32 10 2012 AT32UC3A3 37 2 Package Drawings Figure 37 1 TFBGA 144 package drawing...
Page 991: ...991 32072H AVR32 10 2012 AT32UC3A3 Figure 37 3 VFBGA 100 package drawing...