247
32072H–AVR32–10/2012
AT32UC3A3
17.3
Block Diagram
Figure 17-1. ECCHRS Block Diagram
17.4
Product Dependencies
In order to use this module, other parts of the system must be configured correctly, as described
below.
17.4.1
I/O Lines
The ECCHRS signals pass through the External Bus Interface module (EBI) where they are
multiplexed.
The programmer must first configure the I/O Controller to assign the EBI pins corresponding to
the Static Memory Controller (SMC)
signals to their peripheral function. If I/O lines of the EBI corre-
sponding to
SMC
signals are not used by the application, they can be used for other purposes by
the I/O Controller.
17.4.2
Power Management
If the CPU enters a sleep mode that disables clocks used by the ECCHRS, the ECCHRS will
stop functioning and resume operation after the system wakes up from sleep mode.
17.4.3
Clocks
The clock for the ECCHRS bus interface (CLK_ECCHRS) is generated by the Power Manager.
This clock is enabled at reset, and can be disabled in the Power Manager. It is recommended to
disable the ECCHRS before disabling the clock, to avoid freezing the ECCHRS in an undefined
state.
17.4.4
Interrupts
The ECCHRS interrupt request line is connected to the interrupt controller. Using the ECCHRS
interrupt requires the interrupt controller to be programmed first.
Encoder RS4
Polynomial
process
Partial Syndrome
Chien Search
Error Evaluator
Ctrl/ECC 1bit Algorithm
HECC
User Interface
NAND Flash
SmartMedia
Logic
Static
Memory
Controller
ECC Controller
Peripheral Bus
Rom 1024x10
GF(2 )
10
Summary of Contents for AT32UC3A3128
Page 61: ...61 32072H AVR32 10 2012 AT32UC3A3 PLLEN PLL Enable 0 PLL is disabled 1 PLL is enabled...
Page 592: ...592 32072H AVR32 10 2012 AT32UC3A3 Manchester Configuration Register on page 614...
Page 989: ...989 32072H AVR32 10 2012 AT32UC3A3 37 2 Package Drawings Figure 37 1 TFBGA 144 package drawing...
Page 991: ...991 32072H AVR32 10 2012 AT32UC3A3 Figure 37 3 VFBGA 100 package drawing...
