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ADSP-BF50x Blackfin Processor Hardware Reference

2-5

Memory

Processor-Specific MMRs

The complete set of memory-related MMRs is described in the

Blackfin

Processor Programming Reference

. Several MMRs have bit definitions spe-

cific to the processors described in this manual. These registers are
described in the following sections.

DMEM_CONTROL Register

The data memory control register (

DMEM_CONTROL

), shown in

Figure 2-2

,

contains control bits for the L1 data memory.



Note that both DAG 0 and 1 use Port-A for non-cacheable fetches.

Figure 2-2. L1 Data Memory Control Register

0

31 30

29 28

27 26

25 24

23 22

21 20

19

18 17 16

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

1

0

0

0

0

0

0

0

0

15 14

13 12

11 10

9

8

7

6

5

4

3

2

1

0

0

0

0

Reset = 0x0000 1001

ENDCPLB (Data Cacheability
Protection Lookaside Buffer
Enable)

0 - CPLBs disabled. Minimal

address checking only

1 - CPLBs enabled

DMC (L1 Data Memory
Configure)

DCBS (L1 Data Cache Bank Select)

Valid only when DMC = 1. Determines whether
Address bit A[14] or A[23] is used to select the L1
data cache bank.
0 - Address bit 14 is used to select Bank A

for cache access. If bit 14 of address is 1,
select L1 Data Memory Data Bank A; if bit 14
of address is 0, no bank selected.

1 - Address bit 23 is used to select Bank A for

cache access. If bit 23 of address is 1, select
L1 Data Memory Data Bank A; if bit 23 of
address is 0, no bank selected.

0xFFE0 0004

For ADSP-BF50x:
0 - Data Bank A is SRAM,

also invalidates all
cache lines if previously
configured as cache

1 - Data Bank A is lower

16K byte SRAM, upper
16K byte cache

Data Memory Control Register (DMEM_CONTROL)

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Summary of Contents for EZ-KIT Lite ADSP-BF506F

Page 1: ...a ADSP BF50x Blackfin Processor Hardware Reference Revision 1 2 February 2013 Part Number 82 100101 01 Analog Devices Inc One Technology Way Norwood Mass 02062 9106 ...

Page 2: ... be accurate and reliable However no responsibility is assumed by Analog Devices for its use nor for any infringement of patents or other rights of third parties which may result from its use No license is granted by impli cation or otherwise under the patent rights of Analog Devices Inc Trademark and Service Mark Notice The Analog Devices logo Blackfin CrossCore EngineerZone EZ KIT Lite and Visua...

Page 3: ...i What s New in This Manual lv Technical Support lvi Supported Processors lviiii Product Information lviiii Analog Devices Web Site lviiii EngineerZone lix Notation Conventions lx Register Diagram Conventions lxi INTRODUCTION General Description of Processor 1 1 Portable Low Power Architecture 1 3 System Integration 1 3 Peripherals 1 4 ...

Page 4: ...1 12 3 Phase PWM Unit 1 13 Parallel Peripheral Interface 1 14 SPORT Controllers 1 16 Serial Peripheral Interface SPI Ports 1 18 Timers 1 18 UART Ports 1 19 Controller Area Network CAN Interface 1 21 ACM Interface 1 22 Internal ADC 1 22 Watchdog Timer 1 23 Clock Signals 1 23 Dynamic Power Management 1 24 Full On Operating Mode Maximum Performance 1 24 Active Operating Mode Moderate Dynamic Power Sa...

Page 5: ...1 28 MEMORY Memory Architecture 2 1 L1 Instruction SRAM 2 2 L1 Data SRAM 2 3 L1 Data Cache 2 4 Boot ROM 2 4 External Memory 2 4 Processor Specific MMRs 2 5 DMEM_CONTROL Register 2 5 DTEST_COMMAND Register 2 6 CHIP BUS HIERARCHY Chip Bus Hierarchy Overview 3 1 Interface Overview 3 2 Internal Clocks 3 2 Core Bus Overview 3 4 Peripheral Access Bus PAB 3 5 PAB Arbitration 3 6 PAB Agents Masters Slaves...

Page 6: ...TEM INTERRUPTS Specific Information for the ADSP BF50x 4 1 Overview 4 1 Features 4 2 Description of Operation 4 2 Events and Sequencing 4 2 System Peripheral Interrupts 4 4 Programming Model 4 7 System Interrupt Initialization 4 8 System Interrupt Processing Summary 4 8 System Interrupt Controller Registers 4 10 System Interrupt Assignment SIC_IAR Register 4 11 System Interrupt Mask SIC_IMASK Regi...

Page 7: ...NTERFACE UNIT EBIU Overview 5 1 Block Diagram 5 3 Internal Memory Interfaces 5 4 Registers 5 4 Error Detection 5 5 AMC Overview and Features 5 5 Features 5 6 Asynchronous Memory Interface 5 6 Asynchronous Memory Address Decode 5 6 AMC Description of Operation 5 6 Avoiding Bus Contention 5 6 AMC Programming Model 5 7 EBIU Registers 5 9 EBIU_AMGCTL Register 5 10 EBIU_AMBCTL Register 5 11 EBIU_MODECT...

Page 8: ...mand 6 9 Clear Status Register Command 6 9 Block Erase Command 6 10 Program Command 6 11 Program Erase Suspend Command 6 11 Program Erase Resume Command 6 12 Protection Register Program Command 6 13 The Set Configuration Register Command 6 14 Block Lock Command 6 14 Block Unlock Command 6 15 Block Lock Down Command 6 15 Status Register 6 18 Program Erase Controller Status Bit SR7 6 19 Erase Suspen...

Page 9: ...y Bits CR13 CR11 6 25 Wait Polarity Bit CR10 6 25 Data Output Configuration Bit CR9 6 26 Wait Configuration Bit CR8 6 27 Burst Type Bit CR7 6 27 Valid Clock Edge Bit CR6 6 27 Wrap Burst Bit CR3 6 27 Burst Length Bits CR2 CR0 6 27 Read Modes 6 33 Asynchronous Read Mode 6 33 Synchronous Burst Read Mode 6 33 Synchronous Burst Read Suspend 6 35 Single Synchronous Read Mode 6 36 Dual Operations and Mul...

Page 10: ...ogramming Guidelines 6 77 Bringing Internal Flash Memory Out of Reset 6 78 Timing Configurations for Setting the Internal Flash Memory in Asynchronous Read Mode 6 79 Timing Configurations for Setting the Internal Flash Memory for Write Accesses 6 80 Enabling the Program or Erasure of Internal Flash Memory Blocks 6 82 Configuring Internal Flash Memory for Synchronous Burst Read Mode 6 83 Supported ...

Page 11: ... 6 91 DIRECT MEMORY ACCESS Specific Information for the ADSP BF50x 7 1 Overview and Features 7 2 DMA Controller Overview 7 4 External Interfaces 7 4 Internal Interfaces 7 4 Peripheral DMA 7 5 Memory DMA 7 6 Handshaked Memory DMA HMDMA Mode 7 8 Modes of Operation 7 9 Register Based DMA Operation 7 9 Stop Mode 7 11 Autobuffer Mode 7 11 Two Dimensional DMA Operation 7 11 Examples of Two Dimensional D...

Page 12: ... 7 17 DMA Startup 7 17 DMA Refresh 7 23 Work Unit Transitions 7 25 DMA Transmit and MDMA Source 7 26 DMA Receive 7 27 Stopping DMA Transfers 7 29 DMA Errors Aborts 7 30 DMA Control Commands 7 32 Restrictions 7 35 Transmit Restart or Finish 7 35 Receive Restart or Finish 7 36 Handshaked Memory DMA Operation 7 37 Pipelining DMA Requests 7 38 HMDMA Interrupts 7 40 ...

Page 13: ...ffer DMA Transfers 7 53 Continuous Transfers Using Autobuffering 7 54 Descriptor Structures 7 56 Descriptor Queue Management 7 57 Descriptor Queue Using Interrupts on Every Descriptor 7 58 Descriptor Queue Using Minimal Interrupts 7 59 Software Triggered Descriptor Fetches 7 61 DMA Registers 7 63 DMA Channel Registers 7 64 DMA Peripheral Map Registers DMAx_PERIPHERAL_MAP MDMA_yy_PERIPHERAL_MAP 7 6...

Page 14: ...Registers DMAx_X_MODIFY MDMA_yy_X_MODIFY 7 78 DMA Outer Loop Count Registers DMAx_Y_COUNT MDMA_yy_Y_COUNT 7 79 DMA Current Outer Loop Count Registers DMAx_CURR_Y_COUNT MDMA_yy_CURR_Y_COUNT 7 80 DMA Outer Loop Address Increment Registers DMAx_Y_MODIFY MDMA_yy_Y_MODIFY 7 80 DMA Next Descriptor Pointer Registers DMAx_NEXT_DESC_PTR MDMA_yy_NEXT_DESC_PTR 7 81 DMA Current Descriptor Pointer Registers DM...

Page 15: ...rs HMDMAx_ECOVERFLOW 7 89 DMA Traffic Control Registers DMA_TC_PER and DMA_TC_CNT 7 89 DMA_TC_PER Register 7 90 DMA_TC_CNT Register 7 90 Programming Examples 7 92 Register Based 2 D Memory DMA 7 92 Initializing Descriptors in Memory 7 95 Software Triggered Descriptor Fetch Example 7 98 Handshaked Memory DMA Example 7 101 Unique Information for the ADSP BF50x Processor 7 103 Static Channel Prioriti...

Page 16: ...8 11 Programming Operating Mode Transitions 8 14 Dynamic Supply Voltage Control 8 16 Power Supply Management 8 16 Changing Voltage 8 16 Powering Down the Core Hibernate State 8 18 PLL and VR Registers 8 19 PLL_DIV Register 8 20 PLL_CTL Register 8 21 PLL_STAT Register 8 21 PLL_LOCKCNT Register 8 22 VR_CTL Register 8 22 System Control ROM Function 8 23 Programming Model 8 25 Accessing the System Con...

Page 17: ...System Reset or Soft Reset 8 36 In Full on Mode Change VCO Frequency Core Clock Frequency and System Clock Frequency 8 37 Changing Voltage Levels 8 39 GENERAL PURPOSE PORTS Overview 9 1 Features 9 1 Interface Overview 9 3 External Interface 9 3 Port F Structure 9 3 Port G Structure 9 5 Port H Structure 9 6 Input Tap Considerations 9 6 PWM Unit Considerations 9 8 RSI Considerations 9 8 GP Counter C...

Page 18: ...tion 9 12 General Purpose I O Modules 9 13 GPIO Interrupt Processing 9 16 Programming Model 9 22 Hysteresis Control 9 24 PORTx Hysteresis PORTx_HYSTERESIS Register 9 24 Drive Strength Control 9 26 Memory Mapped GPIO Registers 9 27 Port Multiplexer Control Registers PORTx_MUX 9 27 Function Enable Registers PORTx_FER 9 30 GPIO Direction Registers PORTxIO_DIR 9 30 GPIO Input Enable Registers PORTxIO_...

Page 19: ...GPIO Mask Interrupt Set Registers PORTxIO_MASKA B_SET 9 36 GPIO Mask Interrupt Clear Registers PORTxIO_MASKA B_CLEAR 9 38 GPIO Mask Interrupt Toggle Registers PORTxIO_MASKA B_TOGGLE 9 40 Programming Examples 9 41 GENERAL PURPOSE TIMERS Specific Information for the ADSP BF50x 10 1 Overview 10 2 External Interface 10 3 Internal Interface 10 4 Description of Operation 10 4 Interrupt Processing 10 5 I...

Page 20: ...Mode 10 33 Programming Model 10 34 Timer Registers 10 35 Timer Enable Register TIMER_ENABLE 10 36 Timer Disable Register TIMER_DISABLE 10 37 Timer Status Register TIMER_STATUS 10 39 Timer Configuration Register TIMER_CONFIG 10 41 Timer Counter Register TIMER_COUNTER 10 42 Timer Period TIMER_PERIOD and Timer Width TIMER_WIDTH Registers 10 43 Summary 10 46 Programming Examples 10 49 Unique Informati...

Page 21: ...er TCOUNT 11 5 Core Timer Period Register TPERIOD 11 6 Core Timer Scale Register TSCALE 11 7 Programming Examples 11 7 Unique Information for the ADSP BF50x Processor 11 9 WATCHDOG TIMER Specific Information for the ADSP BF50x 12 1 Overview and Features 12 1 Interface Overview 12 3 External Interface 12 3 Internal Interface 12 3 Description of Operation 12 4 Register Definitions 12 5 Watchdog Coun...

Page 22: ...eration 13 4 Quadrature Encoder Mode 13 4 Binary Encoder Mode 13 5 Up Down Counter Mode 13 6 Direction Counter Mode 13 6 Timed Direction Mode 13 7 Functional Description 13 7 Input Noise Filtering Debouncing 13 7 Zero Marker Push Button Operation 13 9 Boundary Comparison Modes 13 10 Control and Signaling Events 13 11 Illegal Gray Binary Code Events 13 12 Up Down Count Events 13 12 Zero Count Event...

Page 23: ...Mask Register CNT_IMASK 13 20 Counter Status Register CNT_STATUS 13 20 Counter Command Register CNT_COMMAND 13 21 Counter Debounce Register CNT_DEBOUNCE 13 23 Counter Count Value Register CNT_COUNTER 13 24 Counter Boundary Registers CNT_MIN and CNT_MAX 13 25 Programming Examples 13 27 Unique Information for the ADSP BF50x Processor 13 37 PWM CONTROLLER Specific Information for the ADSP BF50x 14 1 ...

Page 24: ... Effective PWM Accuracy 14 24 Switched Reluctance Mode 14 25 Output Control Unit 14 25 Crossover Feature 14 25 Mode Bits POLARITY and SRMODE 14 26 Output Enable Function 14 26 Brushless DC Motor Electronically Commutated Motor Control 14 27 Gate Drive Unit 14 29 High Frequency Chopping 14 29 PWM Polarity Control 14 30 Output Control Feature Precedence 14 31 Switched Reluctance SR Mode 14 31 PWM Sy...

Page 25: ...PWM Crossover and Output Enable PWM_SEG Register 14 45 PWM Sync Pulse Width Control PWM_SYNCWT Register 14 47 PWM Channel AL BL CL Duty Control PWM_CHAL PWM_CHBL PWM_CHCL Registers 14 47 PWM Low Side Invert PWM_LSI Register 14 49 PWM Simulation Status PWM_STAT2 Register 14 49 Unique Information for the ADSP BF50x Processor 14 50 UART PORT CONTROLLERS Overview 15 1 Features 15 2 Interface Overview ...

Page 26: ...5 20 Programming Model 15 22 Non DMA Mode 15 22 DMA Mode 15 24 Mixing Modes 15 25 UART Registers 15 26 UARTx_LCR Registers 15 28 UARTx_MCR Registers 15 31 UARTx_LSR Registers 15 33 UARTx_MSR Registers 15 36 UARTx_THR Registers 15 37 UARTx_RBR Registers 15 38 UARTx_DLL and UARTx_DLH Registers 15 43 UARTx_SCR Registers 15 44 UARTx_GCTL Registers 15 45 Programming Examples 15 46 TWO WIRE INTERFACE CO...

Page 27: ...on 16 6 TWI Transfer Protocols 16 6 Clock Generation and Synchronization 16 7 Bus Arbitration 16 8 Start and Stop Conditions 16 8 General Call Support 16 10 Fast Mode 16 10 Functional Description 16 11 General Setup 16 11 Slave Mode 16 11 Master Mode Clock Setup 16 12 Master Mode Transmit 16 13 Master Mode Receive 16 14 Repeated Start Condition 16 15 Transmit Receive Repeated Start Sequence 16 15 ...

Page 28: ...L 16 27 TWI Slave Mode Address Register TWI_SLAVE_ADDR 16 29 TWI Slave Mode Status Register TWI_SLAVE_STAT 16 29 TWI Master Mode Control Register TWI_MASTER_CTL 16 31 TWI Master Mode Address Register TWI_MASTER_ADDR 16 34 TWI Master Mode Status Register TWI_MASTER_STAT 16 35 TWI FIFO Control Register TWI_FIFO_CTL 16 38 TWI FIFO Status Register TWI_FIFO_STAT 16 40 TWI FIFO Status 16 40 TWI Interrup...

Page 29: ...xamples 16 50 Master Mode Setup 16 50 Slave Mode Setup 16 55 Electrical Specifications 16 61 Unique Information for the ADSP BF50x Processor 16 61 CAN MODULE Overview 17 1 Interface Overview 17 2 CAN Mailbox Area 17 4 CAN Mailbox Control 17 6 CAN Protocol Basics 17 7 CAN Operation 17 9 Bit Timing 17 10 Transmit Operation 17 12 Retransmission 17 13 Single Shot Transmission 17 14 Auto Transmission 1...

Page 30: ...s 17 21 Functional Operation 17 22 CAN Interrupts 17 22 Mailbox Interrupts 17 23 Global CAN Status Interrupt 17 23 Event Counter 17 26 CAN Warnings and Errors 17 27 Programmable Warning Limits 17 28 CAN Error Handling 17 28 Error Frames 17 29 Error Levels 17 31 Debug and Test Modes 17 33 Low Power Features 17 37 CAN Built In Suspend Mode 17 37 CAN Built In Sleep Mode 17 38 CAN Wakeup From Hibernat...

Page 31: ...N_INTR Register 17 46 CAN_GIM Register 17 47 CAN_GIS Register 17 47 CAN_GIF Register 17 48 Mailbox Mask Registers 17 48 CAN_AMxx Registers 17 48 CAN_MBxx_ID1 Registers 17 52 CAN_MBxx_ID0 Registers 17 54 CAN_MBxx_TIMESTAMP Registers 17 56 CAN_MBxx_LENGTH Registers 17 58 CAN_MBxx_DATAx Registers 17 59 Mailbox Control Registers 17 68 CAN_MCx Registers 17 68 CAN_MDx Registers 17 69 CAN_RMPx Register 1...

Page 32: ...AN_MBRIFx Registers 17 80 Universal Counter Registers 17 82 CAN_UCCNF Register 17 82 CAN_UCCNT Register 17 83 CAN_UCRC Register 17 83 Error Registers 17 84 CAN_CEC Register 17 84 CAN_ESR Register 17 84 CAN_EWR Register 17 84 Programming Examples 17 85 CAN Setup Code 17 85 Initializing and Enabling CAN Mailboxes 17 86 Initiating CAN Transfers and Processing Interrupts 17 88 SPI COMPATIBLE PORT CONT...

Page 33: ...ct Enable Output Signals 18 7 Slave Select Inputs 18 8 Use of FLS Bits in SPI_FLG for Multiple Slave SPI Systems 18 8 Internal Interfaces 18 11 DMA Functionality 18 11 Description of Operation 18 12 SPI Transfer Protocols 18 12 SPI General Operation 18 15 Clock Signals 18 16 Interrupt Output 18 17 Functional Description 18 17 Master Mode Operation Non DMA 18 18 Transfer Initiation From Master Tran...

Page 34: ...I Flag SPI_FLG Register 18 38 SPI Status SPI_STAT Register 18 40 Mode Fault Error MODF 18 41 Transmission Error TXE 18 42 Reception Error RBSY 18 42 Transmit Collision Error TXCOL 18 42 SPI Transmit Data Buffer SPI_TDBR Register 18 42 SPI Receive Data Buffer SPI_RDBR Register 18 43 SPI RDBR Shadow SPI_SHADOW Register 18 44 Programming Examples 18 45 Core Generated Transfer 18 45 Initialization Seq...

Page 35: ...ER Specific Information for the ADSP BF50x 19 1 Overview 19 2 Features 19 2 Interface Overview 19 4 SPORT Pin Line Terminations 19 9 Description of Operation 19 10 SPORT Disable 19 10 Setting SPORT Modes 19 11 Stereo Serial Operation 19 11 Multichannel Operation 19 15 Multichannel Enable 19 18 Frame Syncs in Multichannel Mode 19 19 The Multichannel Frame 19 20 Multichannel Frame Delay 19 21 Window...

Page 36: ...ength 19 28 Bit Order 19 28 Data Type 19 28 Companding 19 29 Clock Signal Options 19 30 Frame Sync Options 19 31 Framed Versus Unframed 19 31 Internal Versus External Frame Syncs 19 32 Active Low Versus Active High Frame Syncs 19 33 Sampling Edge for Data and Frame Syncs 19 33 Early Versus Late Frame Syncs Normal Versus Alternate Timing 19 35 Data Independent Transmit Frame Sync 19 37 Moving Data ...

Page 37: ... Register 19 62 SPORT Transmit and Receive Serial Clock Divider SPORT_TCLKDIV and SPORT_RCLKDIV Registers 19 63 SPORT Transmit and Receive Frame Sync Divider SPORT_TFSDIV and SPORT_RFSDIV Registers 19 64 SPORT Multichannel Configuration SPORT_MCMC1 and SPORT_MCMC2 Registers 19 65 SPORT Current Channel SPORT_CHNL Register 19 66 SPORT Multichannel Receive Selection SPORT_MRCSn Registers 19 67 SPORT ...

Page 38: ...20 3 Description of Operation 20 4 Functional Description 20 5 ITU R 656 Modes 20 5 ITU R 656 Background 20 5 ITU R 656 Input Modes 20 9 Entire Field 20 9 Active Video Only 20 10 Vertical Blanking Interval VBI Only 20 10 ITU R 656 Output Mode 20 11 Frame Synchronization in ITU R 656 Modes 20 11 General Purpose PPI Modes 20 12 Data Input RX Modes 20 14 No Frame Syncs 20 15 1 2 or 3 External Frame S...

Page 39: ...0 22 DMA Operation 20 22 PPI Registers 20 25 PPI Control Register PPI_CONTROL 20 25 PPI Status Register PPI_STATUS 20 29 PPI Delay Count Register PPI_DELAY 20 32 PPI Transfer Count Register PPI_COUNT 20 32 PPI Lines Per Frame Register PPI_FRAME 20 33 Programming Examples 20 34 Unique Information for the ADSP BF50x Processor 20 37 REMOVABLE STORAGE INTERFACE Overview 21 1 Interface Overview 21 2 De...

Page 40: ...1 21 CEATA_INT_WAIT State 21 22 CEATA_INT_DIS State 21 22 RSI Command Path CRC 21 23 RSI Data 21 23 RSI Data Transmit Path 21 26 RSI Data Receive Path 21 27 RSI Data Path CRC 21 29 RSI Data FIFO 21 29 SDIO Interrupt and Read Wait Support 21 31 Programming Model 21 32 Card Identification 21 32 SD Card Identification Procedure 21 32 MMC Identification Procedure 21 34 Single Block Write Operations 21...

Page 41: ...egister RSI_CLK_CONTROL 21 55 RSI Argument Register RSI_ARGUMENT 21 57 RSI Command Register RSI_COMMAND 21 57 RSI Response Command Register RSI_RESP_CMD 21 59 RSI Response Registers RSI_RESPONSEx 21 60 RSI Data Timer Register RSI_DATA_TIMER 21 61 RSI Data Length Register RSI_DATA_LGTH 21 62 RSI Data Control Register RSI_DATA_CONTROL 21 62 RSI Data Counter Register RSI_DATA_CNT 21 64 RSI Status Reg...

Page 42: ...21 78 RSI Read Wait Enable Register RSI_RD_WAIT_EN 21 80 RSI Peripheral ID Registers RSI_PIDx 21 81 ADC CONTROL MODULE ACM Interface Overview 22 3 Events 22 6 Timers 22 6 External Triggers 22 7 Event Register Pairs 22 9 Event Comparators 22 9 Timing Generation Unit 22 9 Interrupts 22 10 Description of Operation 22 10 ADC Power Down 22 11 Single Shot Sequencing Mode Emulation 22 11 Continuous Seque...

Page 43: ... 1 22 26 ACM Timing Specifications 22 26 Programming Model 22 27 ACM Registers 22 31 ACM Control ACM_CTL Register 22 32 ACM Status ACM_STAT Register 22 33 ACM Event Status ACM_ES Register 22 34 ACM Event Interrupt Mask ACM_IMSK Register 22 35 ACM Missed Event Status ACM_MS Register 22 36 ACM Event Missed Interrupt Mask ACM_EMSK Register 22 37 ACM Event Control ACM_ERx Registers 22 38 ACM Event Tim...

Page 44: ...TMR Pins 23 6 SYSTEM RESET AND BOOTING Overview 24 1 Reset and Power up 24 3 Hardware Reset 24 5 Software Resets 24 5 Servicing Reset Interrupts 24 8 Basic Booting Process 24 9 Block Headers 24 11 Block Code 24 13 DMA Code Field 24 13 Block Flags Field 24 15 Header Checksum Field 24 16 Header Sign Field 24 17 Target Address 24 17 Byte Count 24 18 Argument 24 18 Boot Host Wait HWAIT Feedback Strobe...

Page 45: ...ror Handler 24 32 CRC Checksum Calculation 24 33 Load Functions 24 33 Calling the Boot Kernel at Runtime 24 34 Debugging the Boot Process 24 35 Boot Management 24 37 Booting a Different Application 24 38 Multi DXE Boot Streams 24 39 Determining Boot Stream Start Addresses 24 43 Initialization Hook Routine 24 43 Specific Boot Modes 24 44 No Boot Mode 24 45 Flash Boot Modes 24 45 SPI Master Boot Mod...

Page 46: ...t Code Revision Control BK_REVISION 24 63 Boot Code Date Code BK_DATECODE 24 64 Zero Word BK_ZEROS 24 65 Ones Word BK_ONES 24 66 Data Structures 24 66 ADI_BOOT_HEADER 24 67 ADI_BOOT_BUFFER 24 67 ADI_BOOT_DATA 24 67 dFlags Word 24 72 Callable ROM Functions for Booting 24 73 BFROM_FINALINIT 24 73 BFROM_PDMA 24 74 BFROM_MDMA 24 74 BFROM_MEMBOOT 24 75 BFROM_SPIBOOT 24 77 BFROM_BOOTKERNEL 24 79 BFROM_C...

Page 47: ...th Initcode 24 84 Example XOR Checksum 24 86 Example Direct Code Execution 24 88 SYSTEM DESIGN Pin Descriptions 25 1 Managing Clocks 25 1 Managing Core and System Clocks 25 2 Configuring and Servicing Interrupts 25 2 Semaphores 25 2 Example Code for Query Semaphore 25 3 Data Delays Latencies and Throughput 25 4 Bus Priorities 25 4 High Frequency Design Considerations 25 5 Signal Integrity 25 5 Dec...

Page 48: ...NMENTS Processor Specific Memory Registers A 2 Core Timer Registers A 3 System Reset and Interrupt Control Registers A 4 DMA Memory DMA Control Registers A 5 Ports Registers A 8 Timer Registers A 11 Watchdog Timer Registers A 15 GP Counter Registers A 15 Dynamic Power Management Registers A 17 PPI Registers A 17 SPI Controller Registers A 18 SPORT Controller Registers A 19 UART Controller Register...

Page 49: ...SI Registers A 46 ACM Registers A 47 TEST FEATURES JTAG Standard B 1 Boundary Scan Architecture B 2 Instruction Register B 4 Public Instructions B 6 EXTEST Binary Code 00000 B 6 SAMPLE PRELOAD Binary Code 10000 B 6 BYPASS Binary Code 11111 B 6 Boundary Scan Register B 7 INDEX ...

Page 50: ...Contents l ADSP BF50x Blackfin Processor Hardware Reference ...

Page 51: ...eatures and processes that they support For programming information see Blackfin Processor Programming Reference For timing electrical and package specifications see ADSP BF504 ADSP BF504F ADSP BF506F Embedded Processor Data Sheet Intended Audience The primary audience for this manual is a programmer who is familiar with Analog Devices processors The manual assumes the audience has a working knowl...

Page 52: ...moves through the system Chapter 4 System Interrupts Describes the system peripheral interrupts including setup and clearing of interrupt requests Chapter 5 External Bus Interface Unit Describes the external bus interface unit of the processor and mem ory interface Chapter 6 Internal Flash Memory Describes the internal flash memory and programmable features Chapter 7 Direct Memory Access Describes...

Page 53: ...supports industrial or motor control type of wheels Chapter 14 PWM Controller Describes the The PWM controller a flexible programmable three phase PWM waveform generator that can be programmed to generate the required switching patterns to drive a three phase volt age source inverter for ac induction motor ACIM or permanent magnet synchronous motor PMSM control Chapter 15 UART Port Controllers Des...

Page 54: ...ating up to 16 bits of data and is used for digital video and data converter applications Chapter 21 Removable Storage Interface Describes the RSI interface for multimedia cards MMC secure digital memory cards SD secure digital input output cards SDIO and consumer electronic ATA devices CE ATA Chapter 22 ADC Control Module ACM Describes the ADC control module ACM which provides an interface to syn...

Page 55: ... Features Describes test features for the processor discusses the JTAG stan dard boundary scan architecture instruction and boundary registers and public instructions This hardware reference is a companion document to Blackfin Pro cessor Programming Reference What s New in This Manual This is Revision 1 2 of ADSP BF50x Blackfin Processor Hardware Refer ence This revision corrects minor typographic...

Page 56: ...atible Port Controller Receiver and transmitter enable bit names standardized on RSPEN and TSPEN in Chapter 19 SPORT Controller ACM programming model updated in Chapter 22 ADC Control Module ACM SYSCR register functionality target address setting by the elfloader utility and MOSI pin latching information in Chapter 24 System Reset and Booting Technical Support You can reach Analog Devices processo...

Page 57: ...edded Studio or VisualDSP version infor mation and license dat file E mail your questions about processors and processor applications to processor support analog com or processor china analog com Greater China support In the USA only call 1 800 ANALOGD 1 800 262 5643 Contact your Analog Devices sales office or authorized distributor Locate one at www analog com adi sales Send questions by mail to ...

Page 58: ...alog com processors technical_library The manuals selection opens a list of current manuals related to the product as well as a link to the previous revisions of the manuals When locating your manual title note a possible errata check mark next to the title that leads to the current correction report against the manual Also note myAnalog is a free feature of the Analog Devices Web site that allows...

Page 59: ...chnical support engineers You can search FAQs and technical information to get quick answers to your embedded processing and DSP design questions Use EngineerZone to connect with other DSP developers who face similar design challenges You can also use this open forum to share knowledge and collaborate with the ADI support team and your peers Visit http ez analog com to sign up ...

Page 60: ...nated with an ellipsis read the example as an optional comma separated list of this SECTION Commands directives keywords and feature names are in text with letter gothic font filename Non keyword placeholders appear in text with italic style format Note For correct operation A Note provides supplementary information on a related topic In the online version of this book the word Note appears instea...

Page 61: ...ister do not follow the overall read write con vention this is noted in the bit description after the bit name If a bit has a short name the short name appears first in the bit description followed by the long name in parentheses The reset value appears in binary in the individual bits and in hexa decimal to the right of the register Bits marked x have an unknown reset value Consequently the reset...

Page 62: ...e state of PULSE_HI alternates each period 00 No error 01 Counter overflow error 10 Period register programming error 11 Pulse width register programming error 00 Reset state unused 01 PWM_OUT mode 10 WDTH_CAP mode 11 EXT_CLK mode PULSE_HI CLK_SEL Timer Clock Select TOGGLE_HI PWM_OUT PULSE_HI Toggle Mode ERR_TYP 1 0 Error Type RO PERIOD_CNT Period Count 0 Interrupt request disable 1 Interrupt requ...

Page 63: ...or Programming Reference General Description of Processor The ADSP BF50x processor is a member of the Blackfin family of prod ucts incorporating the Analog Devices Intel Micro Signal Architecture MSA Blackfin processors combine a dual MAC state of the art signal processing engine the advantages of a clean orthogonal RISC like micro processor instruction set and single instruction multiple data SIM...

Page 64: ...ckage Table 1 1 Processor Comparison Feature ADSP BF504 ADSP BF504F ADSP BF506F Up Down Rotary Counters 2 2 2 Timer Counters with PWM 8 8 8 3 Phase PWM Units 2 2 2 SPORTs 2 2 2 SPIs 2 2 2 UARTs 2 2 2 Parallel Peripheral Interface 1 1 1 Removable Storage Interface 1 1 1 CAN 1 1 1 TWI 1 1 1 Internal 32M Bit Flash 1 1 ADC Control Module ACM 1 1 1 Internal ADC 1 GPIOs 35 35 35 Memory bytes L1 Instruct...

Page 65: ...ons for the next generation of embedded industrial instrumentation and power motion control applications By combining industry standard interfaces with a high performance signal processing core cost effective applications can be developed quickly without the need for costly external components The system peripherals include a watchdog timer two 32 bit up down counters with rotary support eight 32 ...

Page 66: ... when there is also activity on all of the on chip and external peripherals Memory Architecture The Blackfin processor architecture structures memory as a single unified 4G byte address space using 32 bit addresses All resources including internal memory external memory and I O control registers occupy sep arate sections of this common address space The memory portions of this Figure 1 1 ADSP BF50...

Page 67: ...avail able to the core The off chip memory system accessed through the external bus interface unit EBIU provides expansion with flash memory on the ADSP BF504F and ADSP BF506F processors The memory DMA controller provides high bandwidth data movement capability It can perform block transfers of code or data between the internal memory and the external memory spaces Table 1 2 Memory Configurations ...

Page 68: ...he L1 mem ories but is only accessible as data SRAM and cannot be configured as cache memory External Memory External memory is accessed via the EBIU memory port This 16 bit interface provides a glue less connection to the internal flash memory and boot ROM The EBIU on the processor interfaces with an internal flash memory on the ADSP BF504F and ADSP BF506F devices The internal chip flash memory i...

Page 69: ...k 0 of the flash memory parameter bank ships from the factory in an unknown state An erase operation should be per formed prior to programming this block I O Memory Space Blackfin processors do not define a separate I O space All resources are mapped through the flat 32 bit address space Control registers for on chip I O devices are mapped into memory mapped registers MMRs at addresses near the to...

Page 70: ...nd two dimensional 2 D DMA transfers DMA transfer initialization can be implemented from registers or from sets of parameters called descriptor blocks The 2 D DMA capability supports arbitrary row and column sizes up to 64K elements by 64K elements and arbitrary row and column step sizes up to 32K elements Furthermore the column step size can be less than the row step size allowing implementation ...

Page 71: ...ate GPIO modules PORTFIO PORTGIO and PORTHIO associated with Port F Port G and Port H respectively Each GPIO capable pin shares functionality with other processor periph erals via a multiplexing scheme however the GPIO functionality is the default state of the device upon power up Neither GPIO output nor input drivers are active by default Each general purpose port pin can be individually controll...

Page 72: ... generate hardware interrupts while output pins can be triggered by software interrupts GPIO interrupt sensitivity registers The two GPIO interrupt sen sitivity registers specify whether individual pins are level or edge sensitive and specify if edge sensitive whether just the ris ing edge or both the rising and falling edges of the signal are significant One register selects the type of sensitivi...

Page 73: ...nd data rates General call address support Master clock synchronization and support for clock low extension Separate multiple byte receive and transmit FIFOs Low interrupt rate Individual override control of data and clock lines in the event of bus lock up Input filter for spike suppression Serial camera control bus support as specified in OmniVision Serial Camera Control Bus SCCB Functional Speci...

Page 74: ...ition and disable General Purpose GP Counter Two 32 bit GP counters are provided that can sense 2 bit quadrature or binary codes as typically emitted by industrial drives or manual thumb wheels Each counter can also operate in general purpose up down count modes Then count direction is either controlled by a level sensitive input signal or by two edge detectors A third input can provide flexible z...

Page 75: ...ectronically commutated motor ECM or brushless dc motor BDCM Software can enable a special mode for switched reluc tance motors SRM Features of each 3 phase PWM generation unit are 16 bit center based PWM generation unit Programmable PWM pulse width Single double update modes Programmable dead time and switching frequency Twos complement implementation which permits smooth transi tion to full ON a...

Page 76: ...mmetrical about the midpoint of the PWM period In the double update mode a second updating of the PWM registers is implemented at the midpoint of the PWM period In this mode it is possible to produce asymmetrical PWM patterns that produce lower harmonic distortion in 3 phase PWM inverters Parallel Peripheral Interface The processor provides a Parallel Peripheral Interface PPI that can con nect dir...

Page 77: ...zontal and vertical blanking intervals Though not explicitly supported ITU R 656 output functionality can be achieved by setting up the entire frame structure including active video blanking and control information in memory and streaming the data out the PPI in a frame sync less mode The processor s 2 D DMA features facilitate this transfer by allowing the static frame buffer blanking and control...

Page 78: ...cations The SPORTs support these features Bidirectional I2 S capable operation Each SPORT has two sets of independent transmit and receive pins which enable eight channels of I2 S stereo audio Buffered eight deep transmit and receive ports Each port has a data register for transferring data words to and from other processor components and shift registers for shifting data in and out of the data re...

Page 79: ...n be selected on the transmit and or receive channel of the SPORT without addi tional latencies DMA operations with single cycle overhead Each SPORT can automatically receive and transmit multiple buf fers of memory data The processor can link or chain sequences of DMA transfers between a SPORT and memory Interrupts Each transmit and receive port generates an interrupt upon com pleting the transfe...

Page 80: ...an integrated DMA controller configurable to support either transmit or receive data streams The SPI s DMA controller can only ser vice unidirectional accesses at any given time During transfers the SPI port simultaneously transmits and receives by serially shifting data in and out of its two serial data lines The serial clock line synchronizes the shifting and sampling of data on the two serial d...

Page 81: ...e to other peripherals or hosts enabling full duplex DMA supported asynchronous transfers of serial data A UART port includes support for five to eight data bits one or two stop bits and none even or odd parity Each UART port supports two modes of operation PIO programmed I O The processor sends or receives data by writing or reading I O mapped UART registers The data is dou ble buffered on both t...

Page 82: ...Tx_DLL register least significant eight bits and the EDBO is a bit in the UARTx_GCTL register In conjunction with the general purpose timer functions autobaud detec tion is supported The UARTs feature a pair of UAx_RTS request to send and UAx_CTS clear to send signals for hardware flow purposes The transmitter hardware is automatically prevented from sending further data when the UAx_CTS input is ...

Page 83: ...message identifier a time stamp a byte count up to 8 bytes of data and several control bits Each node monitors the mes sages being passed on the network If the identifier in the transmitted message matches an identifier in one of its mailboxes the module knows that the message was meant for it passes the data into its appropriate mailbox and signals the processor of message arrival with an interru...

Page 84: ...for flexible scheduling of sampling instants and provides precise sampling signals to the ADC The ACM synchronizes the ADC conversion process generating the ADC controls the ADC conversion start signal and other signals The actual data acquisition from the ADC is done by SPORT peripherals Internal ADC The ADSP BF506F processor includes an ADC All internal ADC signals are connected out to package p...

Page 85: ...g due to an external noise condition or software error If configured to generate a hardware reset the watchdog timer resets both the CPU and the peripherals After a reset software can determine if the watchdog was the source of the hardware reset by interrogating a status bit in the watchdog control register The timer is clocked by the system clock SCLK at a maximum frequency of fSCLK Clock Signal...

Page 86: ...essor core supply volt age further reducing power dissipation When configured for a 0 volt core supply voltage the processor enters the hibernate state Control of clock ing to each of the processor peripherals also reduces power consumption See Table 1 3 for a summary of the power settings for each mode Full On Operating Mode Maximum Performance In the full on mode the PLL is enabled and is not by...

Page 87: ...o the processor core CCLK The PLL and system clock SCLK how ever continue to operate in this mode Typically an external event wakes up the processor When in the sleep mode asserting a wakeup enabled in the SIC_IWRx registers causes the processor to sense the value of the BYPASS bit in the PLL control register PLL_CTL If BYPASS is disabled the proces sor transitions to the full on mode If BYPASS is...

Page 88: ...ll on mode Hibernate State Maximum Static Power Savings The hibernate state maximizes static power savings by disabling the volt age and clocks to the processor core CCLK and to all of the peripherals SCLK This setting sets the internal power supply voltage VDDINT to 0 V to provide the lowest static power dissipation Any critical informa tion stored internally for example memory contents register ...

Page 89: ...y size The instruction set also provides fully featured multifunction instructions that allow the programmer to use many of the processor core resources in a single instruction Coupled with many features more often seen on microcontrollers this instruction set is very efficient when compiling C and C source code In addition the architecture supports both user algorithm application code and supervi...

Page 90: ...ding Analog Devices emulators and the Cross Core Embedded Studio or VisualDSP development environment The emulator hardware that supports other Analog Devices processors also emulates the processor The development environments support advanced application code devel opment and debug with features such as Create compile assemble and link application programs written in C C and assembly Load run ste...

Page 91: ...ftware tools also include Board Support Packages BSPs Hardware tools also include standalone evaluation systems boards and extenders In addition to the software and hardware development tools available from Analog Devices third parties provide a wide range of tools supporting the Blackfin processors Third party software tools include DSP libraries real time operating systems and block diagram desi...

Page 92: ...Development Tools 1 30 ADSP BF50x Blackfin Processor Hardware Reference ...

Page 93: ... memory map For a detailed discussion of how to use them see Blackfin Processor Programming Reference Note the architecture does not define a separate I O space All resources are mapped through the flat 32 bit address space The memory is byte addressable The upper portion of internal memory space is allocated to the core and system MMRs Accesses to this area are allowed only when the processor is ...

Page 94: ...ry Map INTERNAL CORE ACCESSIBLE MEMORY MAP EXTERNAL INTERFACE ACCESSIBLE MEMORY MAP 0x0000 0000 0x2000 0000 0x2040 0000 0xEF00 0000 0xEF00 1000 0xFF80 0000 0xFF80 4000 0xFF80 8000 0xFFA0 0000 0xFFA0 4000 0xFFA0 8000 0xFFA1 4000 0xFFB0 0000 0xFFB0 1000 0xFFC0 0000 0xFFE0 0000 0xFFFF FFFF SYNC FLASH 32M BITS RESERVED RESERVED BOOT ROM 4K BYTES L1 DATA BANK A SRAM 16K BYTES RESERVED L1 DATA BANK A SR...

Page 95: ...ADSP BF50x Processors 0 0xFFA0 0000 1 0xFFA0 1000 2 0xFFA0 2000 3 0xFFA0 3000 4 0xFFA0 4000 5 0xFFA0 5000 6 0xFFA0 6000 7 0xFFA0 7000 Table 2 2 L1 Data Memory SRAM Subbank Start Addresses Memory Bank and Subbank ADSP BF50x Processors Data Bank A Subbank 0 0xFF80 0000 Data Bank A Subbank 1 0xFF80 1000 Data Bank A Subbank 2 0xFF80 2000 Data Bank A Subbank 3 0xFF80 3000 Data Bank A Subbank 4 0xFF80 4...

Page 96: ...d by CPLB blocks like external mem ory The boot ROM not only contains boot strap loader code it also provides some subfunctions that are user callable at runtime For more information see System Reset and Booting in Chapter 24 System Reset and Booting External Memory External memory shown in Figure 2 1 is accessed via the EBIU memory port This 16 bit interface provides a glue less connection to the...

Page 97: ... 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 Reset 0x0000 1001 ENDCPLB Data Cacheability Protection Lookaside Buffer Enable 0 CPLBs disabled Minimal address checking only 1 CPLBs enabled DMC L1 Data Memory Configure DCBS L1 Data Cache Bank Select Valid only when DMC 1 Determines whether Address bit A 14 or A 23 is used to select the L1 data cache bank 0 Address bit 14 is used to select Bank A for cache acc...

Page 98: ... 24 23 22 21 20 19 18 17 16 X X X X X X X X X X X X X X X Data Test Command Register DTEST_COMMAND 00 Access subbank 0 01 Access subbank 1 10 Access subbank 2 11 Access subbank 3 Subbank Access 1 0 SRAM ADDR 13 12 Reset Undefined Read Write Access Access Way Instruction Address Bit 11 0 Access Way0 Instruction bit 11 0 1 Access Way1 Instruction bit 11 1 Data Instruction Access 0 Access Data 1 Acce...

Page 99: ...tem interconnects and associated system buses This chapter provides Chip Bus Hierarchy Overview Interface Overview on page 3 2 Chip Bus Hierarchy Overview ADSP BF50x Blackfin processors feature a powerful chip bus hierarchy on which all data movement between the processor core internal memory external memory and its rich set of peripherals occurs The chip bus hier archy includes the controllers fo...

Page 100: ...MA controller The interfaces between these the system and the optional external off chip resources The following sections describe the on chip interfaces between the system and the peripherals via the Peripheral Access Bus PAB DMA Access Bus DAB DMA Core Bus DCB DMA External Bus DEB Interface Overview Figure 3 1 shows the core processor and system boundaries as well as the interfaces between them ...

Page 101: ... RSI ACM PPI TWI COUNTER1 0 VOLTAGE REGULATOR I F UART1 0 PORT H PORT G PORT F GPIO JTAG TEST AND EMULATION PERIPHERAL ACCESS BUS WATCHDOG TIMER BOOT ROM DMA ACCESS BUS IRQ CTRL DMA CTRL L1 DATA MEMORY L1 INSTR MEMORY 16 DCB EAB MEMORY PORT FLASH CONTROL B DEB 32M BIT FLASH ADC TIMER7 0 CORE CLOCK CCLK DOMAIN SYSTEM CLOCK SCLK DOMAIN ...

Page 102: ... Core Bus Overview For the purposes of this discussion level 1 memories L1 are included in the description of the core they have full bandwidth access from the pro cessor core with a 64 bit instruction bus and two 32 bit data buses Figure 3 2 shows the core processor and its interfaces to the peripherals and external memory resources The core can generate up to three simultaneous off core accesses...

Page 103: ...es accessed through the PAB are mapped into the system MMR space of the processor memory map The core accesses system MMR space through the PAB bus Figure 3 2 Core Block Diagram INT RESET VECTOR ACK CORE TIMER CORE EVENT CONTROLLER DEBUG AND JTAG INTERFACE JTAG DSP ID 8 BITS SYSTEM CLOCK AND POWER MANAGEMENT POWER AND CLOCK CONTROLLER PERFORMANCE MONITOR MEMORY MANAGEMENT UNIT L1 DATA L1 INSTRUCTI...

Page 104: ...tration is necessary PAB Agents Masters Slaves The processor core can master bus operations on the PAB All peripherals have a peripheral bus slave interface which allows the core to access con trol and status state These registers are mapped into the system MMR space of the memory map For the register addresses see System MMR Assignments on page A 1 The slaves on the PAB bus are System event contr...

Page 105: ...es take four core clocks CCLK of latency The PAB has a maximum frequency of SCLK DMA Access Bus DAB DMA Core Bus DCB DMA External Bus DEB The DAB DCB and DEB buses provide a means for DMA capable peripherals to gain access to on chip and off chip memory with little or no degradation in core bandwidth to memory DAB DCB and DEB Arbitration Sixteen DMA channels and bus masters support the DMA capable...

Page 106: ...DEB transactions to the EPB have priority over core accesses to external memory Use of this bit is application dependent For example if you are polling a peripheral mapped to asynchronous memory with long access times by default the core will win over DMA requests By setting the CDPRIO bit the core would be held off until DMA requests were serviced Table 3 1 DAB DCB and DEB Arbitration Priority DA...

Page 107: ...cified in the pro cessor data sheet The DAB has a dedicated port into L1 memory No stalls occur as long as the core access and the DMA access are not to the same memory bank 4K byte size for L1 If there is a conflict when accessing data memory DMA is the highest priority requester followed by the core If the conflict occurs when accessing instruction memory the core is the highest priority request...

Page 108: ...to carefully analyze your specific traffic patterns Make sure that isochronous peripher als targeting internal memory have enough allocated bandwidth and the appropriate maximum arbitration latencies External Access Bus EAB The EAB provides a way for the processor core to directly access off chip memory Arbitration of the External Bus Arbitration for use of external port bus interface resources is...

Page 109: ... many types of 16 bit memory DMA transfers In the table it is assumed that no other DMA activity is conflicting with ongoing operations The numbers in the table are theoretical values These values may be higher when they are measured on actual hardware due to a variety of reasons relating to the device that is connected to the EBIU Table 3 2 Performance of DMA Access to External Memory Source Dest...

Page 110: ...Interface Overview 3 12 ADSP BF50x Blackfin Processor Hardware Reference ...

Page 111: ...ADSP BF504 ADSP BF504F ADSP BF506F Embedded Processor Data Sheet To determine how each of the system interrupts is multiplexed with other functional pins refer to Table 9 1 on page 9 4 through Table 9 3 on page 9 6 in Chapter 9 General Purpose Ports For a list of MMR addresses for each DMA refer to Chapter A System MMR Assignments System interrupt behavior for the ADSP BF50x that differs from the ...

Page 112: ... masks groups and prioritizes interrupt requests sig nalled by on chip or off chip peripherals and forwards them to the CEC Description of Operation The following sections describe the operation of the system interrupts Events and Sequencing The processor employs a two level event control mechanism The proces sor SIC works with the CEC to prioritize and control all system interrupts The SIC provid...

Page 113: ...Consequently several service routines may be active at any time and a low priority event may be pre empted by one of higher priority The CEC supports nine general purpose interrupts IVG7 IVG15 in addition to the dedicated interrupt and exception events that are described in Table 4 1 It is common for applications to reserve the lowest or the two lowest priority interrupts IVG14 and IVG15 for softw...

Page 114: ...programs their priority by assigning them to individual IVG chan nels However the relative priority of peripheral interrupts can be set by mapping the peripheral interrupt to the appropriate general purpose inter rupt level in the core The mapping is controlled by the SIC_IAR register settings shown in Figure 4 2 on page 4 11 and the tables in Chapter A System MMR Assignments If more than one inte...

Page 115: ...tects the interrupt the bit is asserted When the SIC detects that the peripheral interrupt input has been deas serted the respective bit in the system interrupt status register is cleared Note for some peripherals such as general purpose I O asynchronous input interrupts many cycles of latency may pass from the time an inter rupt service routine initiates the clearing of the interrupt usually by w...

Page 116: ...page 4 11 show the default DMA assignment Once a peripheral has been assigned to any other DMA chan nel it uses the new DMA channel s interrupt ID regardless of whether DMA is enabled or not Therefore clean DMA_PERIPHERAL_MAP manage ment is required even if the DMA is not used The default setup should be the best choice for all non DMA applications For dynamic power management any of the periphera...

Page 117: ... interrupt source is enabled in the SIC_IWR but masked off in the SIC_IMASK register the core wakes up if it is idled but it does not generate an interrupt The peripheral interrupt structure of the processor is flexible Upon reset multiple peripheral interrupts share a single general purpose interrupt in the core by default as shown in Table 4 2 on page 4 11 An interrupt service routine that suppo...

Page 118: ...nterrupt interrupt A is generated by an interrupt enabled peripheral 1 SIC_ISR logs the request and keeps track of system interrupts that are asserted but not yet serviced that is an interrupt service rou tine hasn t yet cleared the interrupt 2 SIC_IWR checks to see if it should wake up the core from an idled state based on this interrupt request 3 SIC_IMASK masks off or enables interrupts from pe...

Page 119: ...r interrupt A has been executed the RTI instruction clears the appropriate IPEND bit However the relevant SIC_ISR bit is not cleared unless the inter rupt service routine clears the mechanism that generated interrupt A or if the process of servicing the interrupt clears this bit It should be noted that emulation reset NMI and exception events as well as hardware error IVHW and core timer IVTMR int...

Page 120: ...t spurious or lost interrupt activity these registers should be written to only when all peripheral interrupts are disabled Figure 4 1 Interrupt Processing Block Diagram INTERRUPT A SYSTEM INTERRUPT MASK SIC_IMASK ASSIGN SYSTEM PRIORITY SIC_IAR CORE EVENT CONTROLLER SYSTEM INTERRUPT CONTROLLER NOTE NAMES IN PARENTHESES ARE MEMORY MAPPED REGISTERS EMU RESET NMI EVX IVTMR IVHW PERIPHERAL INTERRUPT R...

Page 121: ...a peripheral interrupt ID for a particular IVG prior ity Refer to Table 4 1 on page 4 3 for information on SIC_IAR mappings for this specific processor Figure 4 2 System Interrupt Assignment Register Table 4 2 IVG Select Definitions General Purpose Interrupt Value in SIC_IAR IVG7 0 IVG8 1 IVG9 2 IVG10 3 IVG11 4 IVG12 5 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 System In...

Page 122: ...t are asserted but not yet serviced A 0 in a bit position indicates that a particular inter rupt is deasserted A 1 indicates that it is asserted Refer to Table 4 1 on page 4 3 and Table 4 2 for information on how peripheral interrupt IDs are mapped to the SIC_ISR register s for this particular processor System Interrupt Wakeup Enable SIC_IWR Register The SIC_IWR register allows an interrupt reques...

Page 123: ... sensitive request until it is explicitly instructed by software If however the peripheral keeps requesting the respective ILAT bit is set again immediately and the service routine is invoked again as soon as its first run terminates by an RTI instruction Every software routine that services peripheral interrupts must clear the signalling interrupt request in the respective peripheral The individu...

Page 124: ...tem pop registers and exit ssync r7 7 p5 5 sp rti _portg_a_isr end The W1C instruction shown in this example may require several SCLK cycles to complete depending on system load and instruction history The program sequencer does not wait until the instruction completes and con tinues program execution immediately The SSYNC instruction ensures that the W1C command indeed cleared the request in the ...

Page 125: ...source If multiple peripherals are requesting interrupts at the same time it is up to the service routine to either service all requests in a single pass or to service them one by one If only one request is serviced and the respective request is cleared by soft ware before the RTI instruction executes the same service routine is invoked another time because the second request is still pending Whil...

Page 126: ...7 PLL WAKEUP INTERRUPT DMA0 PPI RX or TX DMA1 RSI RX or TX WAKE UP CORE TIMER HARDWARE ERROR EXCEPTIONS NMI SIC_IAR3 SIC_IAR2 SIC_IAR1 SIC_IAR0 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 SIC_ISR0 SIC_IWR0 SIC_IMASK0 RESET EMULATION IMASK IPEND ILAT IVG15 IVG14 IVG13 IVG12 IVG11 IVG10 IVG9 IVG8 IVG7 IVG6 IVG5 IVG3 IVG2 IVG1 IVG0 DMA6 SPI0 RX or TX TWI PORT F INTERRUPT A R...

Page 127: ...SET EMULATION IMASK IPEND ILAT IVG15 IVG14 IVG13 IVG12 IVG11 IVG10 IVG9 IVG8 IVG7 IVG6 IVG5 IVG3 IVG2 IVG1 IVG0 ACM STATUS INTERRUPT RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED TIMER0 TIMER1 TIMER2 TIMER3 TIMER4 TIMER5 TIMER6 TIMER7 MDMA STREAM 0 MDMA STREAM 1 PORT G INTERRUPT A PORT G INTERRUPT B PORT H INTERRUPT A PORT H INTERRUPT B SOFTWARE WATCHDOG TIMER PW...

Page 128: ... the default values at reset and can be changed by software Where there is more than one DMA interrupt source for a given interrupt ID number the default DMA source mapping is listed first in parentheses The peripheral interrupt structure of the processor is flexible Upon reset multiple peripheral interrupts share a single general purpose interrupt in the core by default as shown in Table 4 3 and ...

Page 129: ...C_IAR3 3 0 DMA10 UART1 RX IVG10 23 Bit 23 SIC_IAR2 31 28 DMA9 UART0 TX IVG10 22 Bit 22 SIC_IAR2 27 24 DMA8 UART0 RX IVG10 21 Bit 21 SIC_IAR2 23 20 DMA7 SPI1 RX or TX IVG10 20 Bit 20 SIC_IAR2 19 16 DMA6 SPI0 RX or TX IVG10 19 Bit 19 SIC_IAR2 15 12 DMA5 SPORT1 TX IVG9 18 Bit 18 SIC_IAR2 11 8 DMA4 SPORT1 RX IVG9 17 Bit 17 SIC_IAR2 7 4 DMA3 SPORT0 TX IVG9 16 Bit 16 SIC_IAR2 3 0 DMA2 SPORT0 RX IVG9 15 ...

Page 130: ...Position for SIC_ISR1 SIC_IMASK1 SIC_IWR1 SIC_IAR7 4 Interrupt Source Default Mapping 63 Bit 31 SIC_IAR7 31 28 Reserved IVG7 62 Bit 30 SIC_IAR7 27 24 Reserved IVG7 61 Bit 29 SIC_IAR7 23 20 Reserved IVG7 60 Bit 28 SIC_IAR7 19 16 Reserved IVG7 59 Bit 27 SIC_IAR7 15 12 Reserved IVG7 58 Bit 26 SIC_IAR7 11 8 Reserved IVG7 57 Bit 25 SIC_IAR7 7 4 Reserved IVG7 56 Bit 24 SIC_IAR7 3 0 Reserved IVG7 55 Bit ...

Page 131: ...ftware Watchdog Timer IVG13 43 Bit 11 SIC_IAR5 15 12 MDMA Stream 1 IVG13 42 Bit 10 SIC_IAR5 11 8 MDMA Stream 0 IVG13 41 Bit 9 SIC_IAR5 7 4 Port G Interrupt B IVG12 40 Bit 8 SIC_IAR5 3 0 Port G Interrupt A IVG12 39 Bit 7 SIC_IAR4 31 28 Timer 7 IVG12 38 Bit 6 SIC_IAR4 27 24 Timer 6 IVG12 37 Bit 5 SIC_IAR4 23 20 Timer 5 IVG12 36 Bit 4 SIC_IAR4 19 16 Timer 4 IVG12 35 Bit 3 SIC_IAR4 15 12 Timer 3 IVG12...

Page 132: ...Unique Information for the ADSP BF50x Processor 4 22 ADSP BF50x Blackfin Processor Hardware Reference ...

Page 133: ...e external in its name the EBIU does not provide access to off chip memories EBIU Overview The EBIU services requests for the optional parallel internal flash memory and boot ROM memories from the core or from a DMA channel The pri ority of the requests is determined by the external bus controller The DMA controller provides high bandwidth data movement capability The Memory DMA MDMA channels can ...

Page 134: ... Ratio Control on page 8 5 The external memory space is shown in Figure 5 1 Figure 5 1 ADSP BF50x External Memory Map 0x0000 0000 SYNCHRONOUS FLASH MEMORY 4 MBYTES 0x2000 0000 EXTERNAL MEMORY MAP 0x2040 0000 0xEEFF FFFF THE SYNCHRONOUS FLASH MEMORY IS AVAILABLE ONLY ON THE ADSP BF504F AND ADSP BF506F PROCESSORS RESERVED RESERVED ...

Page 135: ...generate external bus transactions Writes have no effect on external memory values and reads return undefined values The EBIU generates an error response on the internal bus which will generate a hardware exception for a core access or will optionally generate an interrupt from a DMA channel Block Diagram Figure 5 2 is a conceptual block diagram of the EBIU and its interfaces The external bus inte...

Page 136: ...ts from the core These are synchronous interfaces clocked by SCLK as is the EBIU The EAB provides access to external memory The peripheral access bus PAB is used only to access the mem ory mapped control and status registers of the EBIU It does not need to arbitrate with nor take access cycles from the EAB bus The External Bus Controller EBC logic must arbitrate access requests for external memory...

Page 137: ...es as speci fied by the bus master and by asserting the bus error signal for the error condition If the core requested the faulting bus operation the bus error response from the EBIU is gated into the hardware error interrupt IVHW internal to the core this interrupt can be masked off in the core If a DMA master requested the faulting bus operation then the bus error is captured in that controller ...

Page 138: ...s interface to internal flash memory Asynchronous Memory Address Decode The address range allocated per bank is fixed at 4M bytes Accesses to unpopulated memory or partially populated AMC banks do not result in a bus error and will alias to valid AMC addresses AMC Description of Operation The following sections describe the operation of the AMC Avoiding Bus Contention Be careful to avoid contentio...

Page 139: ...ntrol register EBIU_AMGCTL config ures global aspects of the controller It contains bank enables and other information as described in this section This register should not be programmed while the AMC is in use The EBIU_AMGCTL register should be the last control register written to when configuring the processor to access external memory mapped asynchronous devices The AMC interface is used to acc...

Page 140: ...serted Core DMA priority CDPRIO This bit configures the AMC to control the priority over requests that occur simultaneously to the EBIU from either processor core or the DMA controller When this bit is set to 0 a request from the core has priority over a request from the DMA controller to the AMC unless the DMA is urgent When the CDPRIO bit is set all requests from the DMA controller including the...

Page 141: ... enable assertion ARE low and deassertion ARE high Write access the time between write enable assertion AWE low and deassertion AWE high Hold the time between read enable deassertion ARE high or write enable deassertion AWE high and the end of the memory cycle AMS high Each of these parameters can be programmed in terms of EBIU clock cycles In addition there are minimum values for these parameters...

Page 142: ...ster EBIU_AMGCTL AMBEN AMCKEN 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 0 0 0 0 0 0 1 1 1 1 0 1 0 Disable CLKOUT for asynchronous memory region accesses 1 Enable CLKOUT for asynchronous memory region accesses Enable Flash memory bank 0 Flash bank disabled 1 Flash bank enabled Reset 0x00F3 0xFFC0 0A00 CDPRIO 0 Core has priority over DMA for external accesses 1 DMA has priority over core for external ...

Page 143: ...held asserted 0000 Not supported 0001 to 1111 1 to 15 cycles Bank 0 hold time number of cycles between AWE or ARE deasserted and AOE deasserted 00 0 cycles 01 1 cycle 10 2 cycles 11 3 cycles Bank 0 setup time number of cycles after AOE asserted before AWE or ARE asserted 00 4 cycles 01 1 cycle 10 2 cycles 11 3 cycles Bank 0 memory transition time number of cycles inserted after a read access to th...

Page 144: ...rnal Flash Memory Parameter Control Reg ister Asynchronous Memory Mode Control Register EBIU_MODECTL Reset 0x0001 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 B0MODE 1 0 Flash memory access mode 00 Reserved 01 Asynchronous flash mode 10 Reserved 11 Synchronous burst flash mode 0xFFC0 0A20 Asynchronous Flash Memory Parameter Control Register EBIU_FCTL Reset 0x0002 15 14 13 ...

Page 145: ...of 32K words and one parameter bank containing 8 parameter blocks of 4K words and 7 main blocks of 32K words The AMC interface is used to access the internal flash memory on ADSP BF50x processors containing a flash For more information see External Bus Interface Unit on page 5 1 Overview The internal flash memory related pins are shown in Table 6 1 Use this information when referring to the read a...

Page 146: ...he input output pins Figure 6 1 and Table 6 2 show the internal connections to the flash memory Table 6 1 EBIU Internal Flash Memory Internal Pin Connections EBIU Pins Stacked Flash Pins Comment A21 A1 A20 A0 Address pins D15 D0 D15 D0 Data AMS0 E Chip enable ARE G Output enable ADV L Latch enable address valid NOR_CLK K Burst clock ARDY WAIT Wait AWE W Write enable WP Write protect tied low RP1 R...

Page 147: ...s Signal Name Function Direction A0 A20 Address inputs Inputs D0 D15 Data input outputs command inputs I O E Chip Enable Input G Output Enable Input W Write Enable Input RP Reset Input WP Write Protect Input K Clock Input L Latch Enable Input WAIT Wait Output VDD Supply voltage Input WAIT A0 A20 K RP WP G E L INTERNAL FLASH MEMORY W V SS VDD VDDQ VPP DQ0 DQ15 16 ...

Page 148: ...lowed to be in program or erase mode It is possible to perform burst reads that cross bank boundaries The bank architectures are summarized in Table 6 3 VDDFLASH Supply voltage for input output buffers Input VPP Global program erase protect Input VSS Ground Table 6 3 Internal Flash Memory Bank Architecture Number Bank Size Parameter Blocks Main Blocks Parameter bank 4M bit 8 blocks of 4K word 7 bl...

Page 149: ...y array at power up the device is configured for asynchronous read In synchronous burst mode data is output on each clock cycle at frequencies of up to 50 MHz The synchronous burst read operation can be suspended and resumed The device features an automatic standby mode When the bus is inactive during asynchronous read operations the device automatically switches to the automatic standby mode In t...

Page 150: ... Commands consist of one or more sequential bus write operations An internal program erase controller manages all timings and verifies the correct execution of the program and erase commands The program erase controller provides a status register whose output may be read at any time to monitor the progress or the result of the operation The command interface is reset to read mode when power is fir...

Page 151: ...ions read the addressed location and output the data A read array command can be issued in one bank while programming or erasing in another bank However if a read array command is issued to a bank currently executing a program or erase operation the command is executed but the output data is not guaranteed 0x40 Program Setup 0x50 Clear Status Register 0x60 Block Lock Setup Block Unlock Setup Block...

Page 152: ...c Signature Command The read electronic signature command reads the manufacturer and device codes the block locking status the protection register and the configura tion register The read electronic signature command consists of one write cycle to an address within one of the banks A subsequent read operation in the same bank outputs the manufacturer code the device code the protection sta tus of ...

Page 153: ...tatus of the other banks is not affected by the command see Table 6 12 on page 6 37 After issuing a read CFI query command a read array command should be issued to the addressed bank to return the bank to read array mode Dual operations between the parameter bank and the CFI internal flash memory space are not allowed see Table 6 14 on page 6 38 for details See Common Flash Interface on page 6 45 ...

Page 154: ...set is asserted RP driven low As data integrity cannot be guaranteed when the erase operation is aborted the block must be erased again Once the command is issued the device outputs the status register data when any address within the bank is read At the end of the operation the bank remains in read status register mode until a read array read CFI query or read electronic signature command is issu...

Page 155: ...ontent During program operations the bank being programmed only accepts the read array read status register read electronic signature read CFI query and the program erase suspend commands Refer to Dual Operations and Multiple Bank Architecture on page 6 36 for detailed information about simultaneous operations allowed in banks not being programmed Typical program times are given in the ADSP BF504 ...

Page 156: ...d may be protected by issuing the block lock or block lock down commands Only the blocks not being erased may be read or programmed correctly When the program erase resume command is issued the operation completes Refer to Dual Operations and Multiple Bank Architecture on page 6 36 for detailed information about simultaneous operations allowed during program erase suspend During a program erase su...

Page 157: ...page 6 62 and Listing 6 4 on page 6 63 for flowcharts that illustrate usage of the pro gram erase suspend command Protection Register Program Command The protection register program command programs the 128 bit user OTP segment of the protection register and the protection register lock The segment is programmed 16 bits at a time When shipped all bits in the segment are set to 1 The user can only ...

Page 158: ...ssue the set configuration register command The first cycle writes the setup command and the address corre sponding to the configuration register content The second cycle writes the configuration register data and the confirm command Read operations output the internal flash memory device array content after the set configuration register command is issued The value for the configuration register ...

Page 159: ... are required to issue the block unlock command The first bus cycle sets up the block unlock command The second bus write cycle latches the block address The lock status can be monitored for each block using the read electronic signature command Table 16 shows the protection status after issuing a block unlock command Refer to Block Locking on page 6 38 for a detailed explanation and Figure 6 9 on...

Page 160: ...page 6 38 for a detailed explanation and Figure 6 9 on page 6 64 and Listing 6 5 on page 6 64 for a flowchart and pseudo code for using the lock down command Table 6 5 Standard Commands Commands Cycles Bus Operations1 1st Cycle 2nd Cycle Op Add Data Op Add Data Read Array 1 Write BKA 0xFF Read WA RD Read Status Register 1 Write BKA 0x70 Read BKA2 SRD Read Electronic Signature 1 Write BKA 0x90 Read...

Page 161: ...ress PRD Protection Register Da ta CRD Configuration Register Data 2 Must be same bank as in the first cycle The signature addresses are listed in Table 6 6 3 Any address within the bank can be used Table 6 6 Electronic Signature Codes Code Address h Data h Manufacturer Code Bank address 00 0020 Device Code Top Bank address 01 8866 Block Protection Locked Block address 02 0001 Unlocked 0000 Locked...

Page 162: ...ed and updated on the falling edge of the chip enable or output enable signals and can be read until chip enable or output enable are Protection Register Lock Factory default Bank address 80 0002 OTP area perma nently locked 0000 Protection Register Bank address 81 Bank address 84 Unique device number Bank address 85 Bank address 8C OTP Area 1 CR Configuration Register Figure 6 2 Protection Regist...

Page 163: ...hile SR0 refers to the status of the addressed bank The bits in the status register are summarized in Table 6 7 on page 6 23 Refer to Table 6 7 in conjunction with the descriptions in the following sections Program Erase Controller Status Bit SR7 The program erase controller status bit indicates whether the pro gram erase controller is active or inactive in any bank When the program erase controll...

Page 164: ...n the erase suspend latency time of the program erase suspend command being issued therefore the internal flash memory may still complete the operation rather than entering the suspend mode When a program erase resume command is issued the erase suspend status bit returns low Erase Status Bit SR5 The erase status bit identifies if the internal flash memory has failed to verify that the block has e...

Page 165: ...herwise the new command appears to fail VPP Status Bit SR3 The VPP status bit identifies an invalid voltage on the VPP pin during pro gram and erase operations The VPP pin is only sampled at the beginning of a program or erase operation Indeterminate results can occur if VPP becomes invalid during an operation When the VPP status bit is low set to 0 the voltage on the VPP pin was sampled at a vali...

Page 166: ...peration rather than entering the suspend mode When a program erase resume command is issued the program suspend status bit returns low Block Protection Status Bit SR1 The block protection status bit can be used to identify if a program or block erase operation has tried to modify the contents of a locked or locked down block When the block protection status bit is high set to 1 a program or erase...

Page 167: ...ssed Refer to Flowcharts and Pseudo Codes on page 6 56 for status register usage Table 6 7 Status Register Bits Bit Name Type Logic level1 Definition SR7 P EC status Status 1 Ready 0 Busy SR6 Erase suspend status Status 1 Erase suspended 0 Erase in progress or completed SR5 Erase status Error 1 Erase error 0 Erase success SR4 Program status Error 1 Program error 0 Program success SR3 VPP status Er...

Page 168: ...rnal flash device in ADSP BF50xF processors can only be connected to the external bus interface unit EBIU some combinations of the flash configurations are not supported Limitation on supported combinations are described in the section Supported Configuration Reg ister Combinations in ADSP BF50xF Processors on page 6 84 Read Select Bit CR15 The read select bit CR15 switches between asynchronous an...

Page 169: ...st data becoming available For correct operation the X latency bits can only assume the values in Table 6 9 on page 6 28 Table 6 8 shows how to set the X latency parameter taking into account the frequency used to read the internal flash memory in synchronous mode Wait Polarity Bit CR10 In synchronous burst mode the WAIT signal indicates whether the output data are valid or a wait state must be in...

Page 170: ... output configuration depends on the condition where tK is the clock period tQVK_CPU is the data setup time required by the system that is accessing the flash for example the processor and tKQV is the clock to data valid time If this condition is not satisfied the data output configuration bit should be set to 1 two clock cycles Refer to Figure 6 3 Figure 6 3 X Latency and Data Output Configuratio...

Page 171: ...equential addresses See Table 6 10 on page 6 30 and Table 6 11 on page 6 32 for the sequence of addresses output from a given starting address in each mode Valid Clock Edge Bit CR6 The valid clock edge bit CR6 configures the active edge of the clock K during synchronous burst read operations When the valid clock edge bit is 0 the falling edge of the clock is the active edge When the valid clock ed...

Page 172: ...t asserted If the starting address is shifted by 1 2 or 3 positions from the 4 word boundary WAIT is asserted for 1 2 or 3 clock cycles when the burst sequence crosses the first 16 word boundary to indicate that the device needs an internal delay to read the successive words in the array WAIT is asserted only once during a continuous burst access See also Table 6 10 on page 6 30 and Table 6 11 on ...

Page 173: ...nfiguration 0 WAIT is active during wait state 1 WAIT is active one data cycle before wait state default CR7 Burst Type 0 Interleaved 1 Sequential default CR6 Valid Clock Edge 0 Falling clock edge 1 Rising clock edge default CR5 CR4 Reserved CR3 Wrap Burst 0 Wrap 1 No wrap default CR2 CR0 Burst Length 001 4 words 010 8 words 011 16 words 111 Continuous CR7 must be set to 1 default Table 6 9 Config...

Page 174: ...1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 1 1 2 3 0 1 0 3 2 1 2 3 4 5 6 7 0 1 0 3 2 5 4 7 6 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 0 3 2 5 4 7 6 9 8 11 10 13 12 15 14 1 2 3 4 5 6 7 15 WAIT 16 17 18 2 2 3 0 1 2 3 0 1 2 3 4 5 6 7 0 1 2 3 0 1 6 7 4 5 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 0 1 6 7 4 5 10 11 8 9 14 15 12 13 2 3 4 5 6 7 15 WAIT WAIT 16 1...

Page 175: ...4 5 6 7 6 5 4 7 0 1 2 3 4 5 6 7 6 5 4 3 2 1 0 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 8 9 10 11 12 13 14 15 WAIT WAIT WAIT 16 17 12 12 13 14 15 16 17 18 13 13 14 15 WAIT 16 17 18 14 14 15 WAIT WAIT 16 17 18 15 15 WAIT WAIT WAIT 16 17 18 Table 6 10 Burst Type Definition Wrap Mode Cont d Start Add 4 Words 8 Words 16 Words Continuous Burst Sequential Interleaved ...

Page 176: ... 4 5 6 7 8 9 10 11 12 13 14 15 WAIT WAIT 16 17 3 3 4 5 6 3 4 5 6 7 8 9 10 3 4 5 6 7 8 9 10 11 12 13 14 15 WAITWAIT WAIT 16 17 18 7 7 8 9 10 7 8 9 10 11 12 13 14 7 8 9 10 11 12 13 14 15 WAIT WAIT WAIT 16 17 18 19 20 21 22 12 12 13 14 15 12 13 14 15 16 17 18 19 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 13 13 14 15 WAIT 16 13 14 15 WAIT 16 17 18 19 20 13 14 15 WAIT 16 17 18 19 20 21 22 23 24 25...

Page 177: ...e Table 6 12 on page 6 37 and Table 6 13 on page 6 37 Asynchronous Read Mode In asynchronous read operations the clock signal is don t care The device outputs the data corresponding to the address latched that is the internal flash memory array status register common flash interface or electronic signature depending on the command issued CR15 in the con figuration register must be set to 1 for asy...

Page 178: ...an be configured as 4 8 16 words or continuous burst length bits CR2 CR0 The data can be configured to remain valid for one or two clock cycles data output configuration bit CR9 The order of the data output can be modified through the burst type and the wrap burst bits in the configuration register The burst sequence may be configured to be sequential or interleaved CR7 The burst reads can be conf...

Page 179: ...e has output data When the synchronous burst read operation is suspended internal array sensing continues and any previously latched internal data is retained A burst sequence can be suspended and resumed as often as required as long as the operating conditions of the device are met A synchronous burst read operation is suspended when E is low and the current address has been latched on a latch en...

Page 180: ...uted from one bank while another bank is being programmed or erased The dual operations feature means that while programming or erasing in one bank read operations are possible in another bank with zero latency only one bank at a time is allowed to be in program or erase mode If a read operation is required in a bank that is programming or erasing the program or erase operation can be suspended Al...

Page 181: ...es Yes Programming Yes Yes Yes Yes Yes Erasing Yes Yes Yes Yes Yes Program suspended Yes Yes Yes Yes Yes Erase suspended Yes Yes Yes Yes Yes Yes Table 6 13 Dual Operations Allowed in Same Bank Status of Bank Commands Allowed in Same Bank Read Array Read Status Register Read CFI Query Read Electronic Signature Program Block Erase Program Erase Suspend Program Erase Resume Idle Yes Yes Yes Yes Yes Y...

Page 182: ...r the third level offers a complete hard ware protection against program and erase on all blocks The protection status of each block can be set to locked unlocked and lock down Table 6 15 on page 6 41 defines all of the possible protection states WP D1 D0 and Figure 6 9 on page 6 64 shows a flowchart for the locking operations Table 6 14 Dual Operation Limitations Current Status Commands Allowed R...

Page 183: ...et or power down The following sections explain the operation of the locking system Locked State The default status of all blocks on power up or after a hardware reset is locked states 0 0 1 or 1 0 1 Locked blocks are fully protected from any program or erase Any program or erase operations attempted on a locked block returns an error in the status register The status of a locked block can be chan...

Page 184: ...as its WP signal connected to logic low the lock down function is always enabled Locking Operations During Erase Suspend Changes to block lock status can be performed during an erase suspend by using the standard locking command sequences to unlock lock or lock down a block This is useful in the case when another block needs to be updated while an erase operation is in progress To change block loc...

Page 185: ...he lock status is defined by the write protect pin and by D1 1 for a locked down block and D0 1 for a locked block as read in the read electronic signature command with A1 VIH and A0 VIL Next Protection Status1 D1 D0 Current State Program Erase Allowed After Block Lock Command After Block Unlock Command After Block Lock Down Command 0 0 yes 0 1 0 0 1 1 0 12 2 All blocks are locked at power up so t...

Page 186: ...ameter Bank 0 4 0x203FE000 0x203FFFFE 1 4 0x203FC000 0x203FDFFE 2 4 0x203FA000 0x203FBFFE 3 4 0x203F8000 0x203F9FFE 4 4 0x203F6000 0x203F7FFE 5 4 0x203F4000 0x203F5FFE 6 4 0x203F2000 0x203F3FFE 7 4 0x203F0000 0x203F1FFE 8 32 0x203E0000 0x203EFFFE 9 32 0x203D0000 0x203DFFFE 10 32 0x203C0000 0x203CFFFE 11 32 0x203B0000 0x203BFFFE 12 32 0x203A0000 0x203AFFFE 13 32 0x20390000 0x2039FFFE 14 32 0x203800...

Page 187: ...x202F0000 0x202FFFFE 24 32 0x202E0000 0x202EFFFE 25 32 0x202D0000 0x202DFFFE 26 32 0x202C0000 0x202CFFFE 27 32 0x202B0000 0x202BFFFE 28 32 0x202A0000 0x202AFFFE 29 32 0x20290000 0x2029FFFE 30 32 0x20280000 0x2028FFFE Bank 3 31 32 0x20270000 0x2027FFFE 32 32 0x20260000 0x2026FFFE 33 32 0x20250000 0x2025FFFE 34 32 0x20240000 0x2024FFFE 35 32 0x20230000 0x2023FFFE 36 32 0x20220000 0x2022FFFE 37 32 0x...

Page 188: ...20170000 0x2017FFFE 48 32 0x20160000 0x2016FFFE 49 32 0x20150000 0x2015FFFE 50 32 0x20140000 0x2014FFFE 51 32 0x20130000 0x2013FFFE 52 32 0x20120000 0x2012FFFE 53 32 0x20110000 0x2011FFFE 54 32 0x20100000 0x2010FFFE Bank 6 55 32 0x200F0000 0x200FFFFE 56 32 0x200E0000 0x200EFFFE 57 32 0x200D0000 0x200DFFFE 58 32 0x200C0000 0x200CFFFE 59 32 0x200B0000 0x200BFFFE 60 32 0x200A0000 0x200AFFFE 61 32 0x2...

Page 189: ... Table 6 26 show the addresses used to retrieve the data The query data is always presented on the lowest order data outputs D0 D7 the other out puts D8 D15 are set to 0 The CFI data structure also contains a security area where a 64 bit unique security number is written see Figure 6 2 on page 6 18 This area can be Bank 7 63 32 0x20070000 0x2007FFFE 64 32 0x20060000 0x2006FFFE 65 32 0x20050000 0x2...

Page 190: ...c information 0x10 CFI Query Identification String Command set ID and algorithm data offset 0x1B System Interface Information Device timing and voltage information 0x27 Device Geometry Definition Flash device layout P Primary Algorithm Specific Extended Query table Additional information specific to the primary algorithm optional A Alternate Algorithm Specific Extended Query Table Additional infor...

Page 191: ...erase or write voltage bit 7 to 4 BCD value in volts bit 3 to 0 BCD value in 100 millivolts 1 7 V 0x1C 0x0020 VDD logic supply maximum program erase or write voltage bit 7 to 4 BCD value in volts bit 3 to 0 BCD value in 100 millivolts 2 V 0x1D 0x0085 VPP programming supply minimum program erase voltage bit 7 to 4 HEX value in volts bit 3 to 0 BCD value in 100 millivolts 8 5 V 0x1E 0x0095 VPP progr...

Page 192: ...ytes in multi byte program or page 2n N A 0x2C 0x0002 Number of identical sized erase block regions within the device bit 7 to 0 x number of erase block regions 2 Top Devices 0x2D 0x2E 0x003E 0x0000 Internal flash region 1 information Number of identical size erase blocks 0x003E 1 63 0x007E 0x0000 Internal flash region 1 information Number of identical size erase blocks 0x007E 1 127 0x2F 0x30 0x00...

Page 193: ... Yes 0 No No Bit 2 program suspend supported 1 Yes 0 No Yes Bit 3 legacy lock unlock supported 1 Yes 0 No Yes Bit 4 queued erase supported 1 Yes 0 No No Bit 5 instant individual block locking supported 1 Yes 0 No No 0x P 8 0x41 0x0000 Bit 6 protection bits supported 1 Yes 0 No Yes Bit 7 page mode read supported 1 Yes 0 No Yes Bit 8 synchronous read supported 1 Yes 0 No Yes Bit 9 simultaneous opera...

Page 194: ...it 7 to 4 HEX value in volts 9 V Bit 3 to 0 BCD value in 100 mV 1 The variable P is a pointer that is defined at CFI offset 0x15 Table 6 22 Protection Register Information1 Offset Data Description Value 0x P E 0x47 0x0001 Number of protection register fields in JEDEC ID space 0x0000 indicates that 256 fields are available 1 0x P F 0x48 0x0080 Protection Field 1 protection description Bits 0 7 lowe...

Page 195: ...continuous linear bursts that will output data until the internal burst counter reaches the end of the device s burstable address space This field s 3 bit value can be written directly to the read configuration register bit 0 2 if the device is config ured for its maximum word width See offset 0x28 for word width to determine the burst data output width 4 0x P 16 0x4F 0x0002 Synchronous mode read ...

Page 196: ...rogram operations Bits 4 7 number of simultaneous erase operations 0x P 1E 0x57 0x00 Number of program or erase operations allowed in other banks while a bank in this region is erasing Bits 0 3 number of simultaneous program operations Bits 4 7 number of simultaneous erase operations 0x P 1F 0x58 0x01 Types of erase block regions in bank region 1 n number of erase block regions with contiguous sam...

Page 197: ...ion1 Internal Flash Region 2 Description Offset Data 0x P 28 0x61 0x01 Number of identical banks within bank region 2 0x P 29 0x62 0x00 0x P 2A 0x63 0x11 Number of program or erase operations allowed in bank region 2 Bits 0 3 number of simultaneous program operations Bits 4 7 number of simultaneous erase operations 0x P 2B 0x64 0x00 Number of program or erase operations allowed in other banks whil...

Page 198: ...2 erase block type 1 bits per cell internal ECC Bits 0 3 bits per cell in erase region Bit 4 reserved for internal ECC used Bits 5 7 reserved 0x P 35 0x6E 0x03 Bank region 2 erase block type 1 page mode and synchronous mode capabilities defined in Table 6 23 on page 6 51 Bit 0 page mode reads permitted Bit 1 synchronous reads permitted Bit 2 synchronous writes permitted Bits 3 7 reserved 0x P 36 0...

Page 199: ...age mode and synchronous mode capabilities defined in Table 6 23 on page 6 51 Bit 0 page mode reads permitted Bit 1 synchronous reads permitted Bit 2 synchronous writes permitted Bits 3 7 reserved 0x P 3E 0x77 Feature space definitions 0x P 3F 0x78 Reserved 1 The variable P is a pointer which is defined at CFI offset 0x15 2 Bank regions There are two bank regions see Table 6 16 on page 6 42 Table ...

Page 200: ...can be made after each program operation or after a sequence 2 If an error is found the status register must be cleared before further program erase controller oper ations 3 Any address within the bank can equally be used START YES WRITE 0x40 or 0x103 WRITE ADDRESS AND DATA READ STATUS REGISTER3 SR7 1 SR3 0 SR4 0 SR1 0 YES YES YES VPP INVALID ERROR1 2 PROGRAM ERROR1 2 PROGRAM TO PROTECTED BLOCK ER...

Page 201: ...Program 0x10 see note 3 writeToFlash addressToProgram dataToProgram Memory enters read status state after the Program Command do status_register readFlash addressToProgram see note 3 E or G must be toggled while status_register SR7 0 if status_register SR3 1 VPP invalid error error_handler if status_register SR4 1 program error error_handler if status_register SR1 1 program to protect block error ...

Page 202: ...ad status register command write 0x70 can be issued just before or just after the program re sume command START YES WRITE 0xB0 READ STATUS REGISTER SR7 1 SR2 1 YES PROGRAM COMPLETE PROGRAM CONTINUES WITH BANK IN READ STATUS REGISTER MODE NO WRITE 0x70 WRITE 0xFF NO READ DATA WRITE 0xFF WRITE 0xD0 READ DATA FROM ANOTHER ADDRESS WRITE 0x701 ...

Page 203: ... do status_register readFlash bank_address E or G must be toggled while status_register SR7 0 if status_register SR2 0 program completed writeToFlash bank_address 0xFF read_data The device returns to Read Array as if program erase suspend was not issued else writeToFlash bank_address 0xFF read_data read data from another address writeToFlash any_address 0xD0 write 0xD0 to resume program writeToFla...

Page 204: ...tatus register must be cleared before further program erase operations 2 Any address within the bank can be used also START YES WRITE 0x202 WRITE BLOCK ADDRESS AND 0xD0 READ STATUS REGISTER2 SR7 1 SR3 0 SR4 SR5 1 SR5 0 YES YES YES VPP INVALID ERROR1 COMMAND SEQUENCE ERROR1 ERASE ERROR 1 NO NO NO END NO SR1 0 ERASE TO PROTECTED BLOCK ERROR1 NO YES ...

Page 205: ...ignificant Memory enters read status state after the Erase Command do status_register readFlash blockToErase see note 2 E or G must be toggled while status_register SR7 0 if status_register SR3 1 VPP invalid error error_handler if status_register SR4 1 status_register SR5 1 command sequence error error_handler if status_register SR5 1 erase error error_handler if status_register SR1 1 program to p...

Page 206: ...ite 0x70 can be issued just before or just after the erase resume command START YES WRITE 0xB0 READ STATUS REGISTER SR7 1 SR6 1 YES ERASE CONTINUES WITH BANK IN READ STATUS REGISTER MODE NO WRITE 0x70 WRITE 0xFF ERASE COMPLETE NO READ DATA WRITE 0xFF WRITE 0xD0 WRITE 0x701 Read data from another block Program Set Configuration Register or Block Lock Unlock Lock Down ...

Page 207: ... already completed do status_register readFlash bank_address E or G must be toggled while status_register SR7 0 if status_register SR6 0 erase completed writeToFlash bank_address 0xFF read_data The device returns to Read Array as if program erase suspend was not issued else writeToFlash bank_address 0xFF read_program_data read or program data from another block writeToFlash bank_address 0xD0 write...

Page 208: ...cking Operations Pseudo Code locking_operation_command address lock_operation writeToFlash address 0x60 configuration setup see note 1 Figure 6 9 Locking Operations Flowchart1 1 Any address within the bank can equally be used START WRITE 0x601 WRITE 0x01 0xD0 or 0x2F LOCKING CHANGE CONFIRMED YES END NO WRITE 0x901 READ BLOCK LOCK STATES WRITE 0xFF1 ...

Page 209: ...ck_operation UNLOCK to unprotect the block writeToFlash address 0xD0 else if lock_operation LOCK DOWN to lock the block writeToFlash address 0x2F writeToFlash address 0x90 see note 1 if readFlash address locking_state_expected error_handler Check the locking state see Read Block Signature table writeToFlash address 0xFF Reset to Read Array mode see note 1 ...

Page 210: ...can be made after each program operation or after a sequence 2 If an error is found the status register must be cleared before further program erase controller oper ations 3 Any address within the bank can equally be used START YES WRITE 0xC0 3 WRITE ADDRESS AND DATA READ STATUS REGISTER3 SR7 1 SR3 0 SR4 0 YES YES VPP INVALID ERROR1 2 PROGRAM ERROR1 2 NO NO END NO SR1 0 PROGRAM TO PROTECTED BLOCK ...

Page 211: ...sToProgram 0xC0 see note 3 writeToFlash addressToProgram dataToProgram Memory enters read status state after the Program Command do status_register readFlash addressToProgram see note 3 E or G must be toggled while status_register SR7 0 if status_register SR3 1 VPP invalid error error_handler if status_register SR4 1 program error error_handler if status_register SR1 1 program to protect block err...

Page 212: ...irm 0xD0 Program Erase Suspend 0xB0 Read Status Register 0x70 Clear Status Register 5 0x50 Read Electronic Signature Read CFI Query 0x90 0x98 Ready Ready Program Setup Erase Setup Ready Lock CR Setup Ready Lock Error Ready Ready Lock Error OTP Setup OTP Busy Busy OTP Busy IS in OTP Busy OTP Busy IS in OTP Busy OTP Busy Prog Setup Program Busy Busy Prog Busy IS in Program Busy Prog Busy PS Program ...

Page 213: ...g in ES IS in Erase Sus pend Erase Busy Erase Suspend IS in ES Erase Suspend Table 6 27 Command Interface States Modify Table Next State Cont d Current CI State1 Command Input Read Array 2 0xFF WP setup 3 4 10 0x40 Block Erase Setup 3 4 0x20 Erase Confirm P E Resume Block Unlock Confirm 0xD0 Program Erase Suspend 0xB0 Read Status Register 0x70 Clear Status Register 5 0x50 Read Electronic Signature...

Page 214: ... erase controller PS program suspend ES erase suspend IS illegal state 2 At power up all banks are in read array mode A read array command issued to a busy bank results in undetermined data output 3 The two cycle command should be issued to the same bank address 4 If the P EC is active both cycles are ignored 5 The clear status register command clears the status register error bits except when the...

Page 215: ...d Input Read Array 3 0xFF Block Erase Setup 4 5 0x20 Erase Confirm P E Resume Block Unlock Confirm 0xD0 Program Erase Suspend 0xB0 Read Status Register 0x70 Clear Status Register 6 0x50 Read Electronic Signature Read CFI Query 0x90 0x98 Program Setup Status Register Erase Setup OTP Setup Program Setup in Erase Suspend Lock CR Setup Lock CR Setup in Erase Suspend ...

Page 216: ...nd address A bank can be placed in read array read status register read electronic signature or read CFI query mode depending on the command issued Each bank remains in its last output state until a new command is issued The next state does not depend on the bank s out put state 3 At power up all banks are in read array mode A read array command issued to a busy bank results in undetermined data o...

Page 217: ...t CR Confirm 0x03 Illegal Command3 P E C Operation Completed Ready Lock CR Setup OTP Setup Ready N A Lock CR Setup Ready Lock error Ready Ready Lock error N A OTP Setup OTP Busy Busy IS in OTP busy OTP Busy Ready IS in OTP busy OTP Busy IS Ready Program Setup Program Busy N A Busy IS in Program busy Program Busy Ready IS in Program busy Program busy IS Ready Suspend IS in PS Program Suspend N A IS...

Page 218: ...n ES Erase Suspend Lock error Erase Suspend Erase Suspend Lock error N A 1 CI command interface CR configuration register enhanced factory program P E C program erase controller IS illegal state ES erase suspend PS program suspend 2 If the P EC is active both cycles are ignored 3 Illegal commands are those not defined in the command set Table 6 29 Command Interface States Lock Table Next State Con...

Page 219: ...p2 0x60 OTP Setup2 0xC0 Block Lock Confirm 0x01 Block Lock Down Confirm 0x2F Set CR Confirm 0x03 Illegal Command3 P E C Operation Completed Program Setup Status Register Output Unchanged Erase Setup OTP Setup Program Setup in Erase Suspend EFP Setup EFP Busy EFP Verify Quad EFP Setup Quad EFP Busy Lock CR Setup Status Register Array Status Register Lock CR Setup in Erase Suspend ...

Page 220: ...e Output Unchanged 1 CI command interface CR configuration register P E C program erase controller 2 If the P EC is active both cycles are ignored 3 Illegal commands are those not defined in the command set Table 6 30 Command Interface States Lock Table Next Output Cont d Current CI State1 Command Input Lock CR Setup2 0x60 OTP Setup2 0xC0 Block Lock Confirm 0x01 Block Lock Down Confirm 0x2F Set CR...

Page 221: ...e Program or Erasure of Internal Flash Memory Blocks on page 6 82 Configuring Internal Flash Memory for Synchronous Burst Read Mode on page 6 83 Configuring the EBIU for Synchronous Read Mode on page 6 85 Unsupported Programming Practices in Flash on page 6 87 In these sections references are made to the following parameters that describe the timing characteristics of the EBIU Setup ST the time be...

Page 222: ... cycle RAT 1 cycle WAT 1 cycle HT 0 cycle TT 1 cycle Bringing Internal Flash Memory Out of Reset The RP pin of the internal flash memory device is controlled by bit 0 of the FLASH_CONTROL register Setting bit 0 of the FLASH_CONTROL register to 1 enables the flash by bringing it out of reset Refer to ADSP BF504 ADSP BF504F ADSP BF506F Embedded Proces sor Data Sheet for the timing requirements neede...

Page 223: ...ET FLASH_ENABLE asm ssync nop nop nop nop nop nop nop Timing Configurations for Setting the Internal Flash Memory in Asynchronous Read Mode Once out of reset the internal flash memory is configured in asynchro nous mode Therefore the EBIU should be configured in asynchronous mode as well by programming the B0MODE field in the EBIU_MODECTL regis ter to the value b 01 The internal flash device s WAI...

Page 224: ...refore if the flash access pattern is such that only read accesses are per formed with no write accesses performed then B0HT may be programmed to the value b 00 However if there were any write accesses interspersed with the read accesses then the B0HT field should be programmed according to the recommendation for write accesses See Timing Configurations for Setting the Internal Flash Memory for Wr...

Page 225: ...figuration Register command System designers should take this into account and may insert software NOP instructions to delay the first read in the same bank after issuing any command and to delay the first read to any address after issu ing a Set Configuration Register command If the first read after the command is a read array operation in a different bank and no changes to the configuration regi...

Page 226: ...1 Doing so disables the hardware flash protection mechanism by driving the flash s VPP signal with logic high In addition since the default status of all blocks on flash power up or after a flash hardware reset is locked further block unlock commands are neces sary in order to allow for software programming or erasure of flash Refer to Block Locking on page 6 38 for further details on block lockin...

Page 227: ...rs as shown in section Configuring the EBIU for Syn chronous Read Mode on page 6 85 As shown in Table 6 5 Standard Commands two write cycles are required to issue the Set Configuration Register command The first cycle writes the setup command to the address corresponding to the value that is to be programmed into the configuration register The second cycle writes the confirm command to the address...

Page 228: ...0xF Processors Since the internal flash device in ADSP BF50xF processors can only be connected to the external bus interface unit EBIU some combinations of the flash configurations are not supported Some of the restrictions on the values to be programmed in the flash configuration register are as follows The programming of bit CR10 determines the programming of bit 1 B0RDYPOL of the EBIU_AMBCTL0 r...

Page 229: ... by program ming the B0MODE field in the EBIU_MODECTL register to the value b 11 selecting the appropriate NOR_CLK frequency in the BCLK bit field of the EBIU_FCTL register and configuring the EBIU_AMBCTL register as follows B0RDYEN must be programmed to 1 for synchronous burst read mode B0RDYPOL must be set to 1 if bit 10 of the flash configuration regis ter CR10 is programmed to 0 and programmed...

Page 230: ...med depending on the NOR_CLK frequency selected in the EBIU_FCTL register and on the X latency setting selected in the flash configuration register CR13 CR11 according to the following table Example synchronous read and write waveforms using the internal flash memory pins from Table 6 1 on page 6 2 appear in Figure 6 12 SCLK NOR_CLK Min Setup Time B0ST Values Supported B0ST Value Recommended 2 1 2...

Page 231: ...only be performed when the flash is configured in asynchronous mode The flash is only addressable and programmed at 2 bytes granular ity Therefore any byte write instructions with the destination address residing in flash shall be avoided Figure 6 12 Example Sync Read and Write Waveforms SETUP 2 CYCLES X LATENCY 3 BURST CLOCK CYCLES HOLD 0 CYCLE CLKOUT ADDR 21 1 L E G W WAIT DQ 15 0 HIGH Z HIGH Z ...

Page 232: ...on the FLUSH and FLUSHINV data cache flush instructions cannot be used when the flash mem ory is the destination of the data in cache Internal Flash Memory Control Registers In addition to the EBIU registers see EBIU Registers on page 5 9 the internal flash memory usage is controlled by the following registers Internal Flash Memory Control FLASH_CONTROL Register Internal Flash Memory Control Set F...

Page 233: ...t the boot firmware brings the flash out of reset state by programming the FLASH_ENABLE bit to 1 Table 6 32 Internal Flash Memory Control Register FLASH_CONTROL Register Field Name Offset Access Description FLASH_ENABLE 0 RO Enable internal flash memory for read write 0 internal flash memory is in reset state 1 internal flash memory is out of reset state RESERVED 7 1 RO FLASH_UNPROTECT 8 RO 0 Prot...

Page 234: ...y can only be cleared programmed to 0 This UNLOCK_HIBYTE feature may be used to provide a level of protection against inadvertent programming erasure of the flash Since the reset value of the FLASH_UNPROTECT bit bit 8 in the FLASH_CONTROL register is 0 the internal flash memory device is protected by default against programming and erasure If the user chose to ensure the continued protection of fl...

Page 235: ...eturn the internal flash memory control register value Internal Flash Memory Control Clear FLASH_CONTROL_CLEAR Register Writing to a bit in the FLASH_CONTROL_CLEAR register clears the corre sponding bit in the internal flash memory control register Reads return the internal flash memory control register value Address Register Name Size Reset Value 0xFFC0 3290 FLASH_CONTROL_SET 16 0x8000 Address Re...

Page 236: ...Internal Flash Memory Control Registers 6 92 ADSP BF50x Blackfin Processor Hardware Reference ...

Page 237: ...he appropriate peripheral chapter for additional information Perfor mance and bus arbitration for DMA operations can be found in Chapter 3 Chip Bus Hierarchy Specific Information for the ADSP BF50x For details regarding the number of DMA controllers for the ADSP BF50x product refer to ADSP BF504 ADSP BF504F ADSP BF506F Embedded Processor Data Sheet For DMA interrupt vector assignments refer to Tab...

Page 238: ...can perform several types of data transfers Peripheral DMA transfers data between memory and on chip peripherals Memory DMA MDMA transfers data between memory and memory The processor has two MDMA modules each consisting of independent memory read and memory write channels Handshaking memory DMA HMDMA transfers data between off chip peripherals and memory This enhancement of the MDMA channels enab...

Page 239: ... transfer allows the chaining together of multiple DMA sequences In descriptor based DMA operations a DMA channel can be programmed to automatically set up and start another DMA transfer after the current sequence completes Examples of DMA styles supported by flex descriptors include A single linear buffer that stops on completion FLOW stop mode A linear buffer with byte strides of any integer val...

Page 240: ... EBIU can also be accessed by peripheral DMA or mem ory DMA operation This is typically flash memory SRAM SDRAM FIFOs or memory mapped peripheral devices For products with handshaking MDMA HMDMA the operation is sup ported by two MDMA request input pins DMAR0 and DMAR1 The DMAR0 pin controls transfer timing on the MDMA0 destination channel The DMAR1 pin controls the destination channel of MDMA1 Wi...

Page 241: ...ernal memories and devices It operates at SCLK frequency Transferred data can be 8 16 or 32 bits wide The DMA controller however connects only to 16 bit buses Memory DMA can pass data every SCLK cycle between L1 memory and the EBIU Transfers from L1 memory to L1 memory require two cycles as the DCB bus is used for both source and destination transfers Similarly transfers between two off chip devic...

Page 242: ...annel is disabled DMA requests are ignored and no DMA grants are issued The DMA requests are also not forwarded from the peripheral to the interrupt controller All peripheral DMA channels work completely independently from each other The transfer timing is controlled by the mapped peripheral Every DMA channel features its own 4 deep FIFO that decouples DAB activity from DCB and DEB availability DM...

Page 243: ...iorities 12 through 15 Priority 12 MDMA0 destination Priority 13 MDMA0 source Priority 14 MDMA1 destination Priority 15 MDMA1 source MDMA0 takes precedence over MDMA1 unless round robin scheduling is used or priorities become urgent as programmed by the DRQ bit field in the HMDMA_CONTROL register It is illegal to program a source channel for memory write or a des tination channel for memory read T...

Page 244: ...eral DMA The DMAx_CONFIG register for the source channel must be written before the DMAx_CONFIG register for the destination channel Handshaked Memory DMA HMDMA Mode This feature is not available for all products Refer to Unique Informa tion for the ADSP BF50x Processor on page 7 103 to determine whether it applies to this product Handshaked operation applies only to memory DMA channels Normally m...

Page 245: ... For best throughput DMA requests can be pipelined The HMDMA controllers feature a request counter to decouple request timing from the data transfers See Handshaked Memory DMA Operation on page 7 37 for a func tional description Modes of Operation The following sections describe the DMA operation Register Based DMA Operation Register based DMA is the traditional kind of DMA operation Software conf...

Page 246: ... DMAs and destination channel MDMAs set this bit because they write to memory The WDSIZE bit controls the data word width for the trans fer It can be 8 16 or 32 bits wide The DI_EN bit enables an interrupt when the DMA opera tion has finished Set the FLOW field to 0x0 for stop mode or 0x1 for autobuffer mode Once the DMAEN bit is set the DMA channel starts its operation While running the DMAx_CURR...

Page 247: ...ription of the SYNC bit in the DMAx_CONFIG register for details Autobuffer Mode In autobuffer mode the DMA operates repeatedly in a circular manner If all data words have been transferred the address pointer DMAx_CURR_ADDR is reloaded automatically by the DMAx_START_ADDR value An interrupt may also be generated Autobuffer mode is entered if the FLOW field in the DMAx_CONFIG register is 1 The NDSIZ...

Page 248: ...nd DMAx_CURR_X_COUNT decrements from 1 to 0 The DMAx_Y_MODIFY value is the byte address increment that is applied after each decrement of the DMAx_CURR_Y_COUNT register However the DMAx_Y_MODIFY value is not applied to the last item in the array on which the outer loop count DMAx_CURR_Y_COUNT also expires by decrementing from 1 to 0 After the last transfer completes DMAx_CURR_Y_COUNT 1 DMAx_CURR_X...

Page 249: ...he end of one row to the start of another DMAx_Y_COUNT 8 This produces the following address offsets from the start address 0 1 2 15 N N 1 N 15 2N 2N 1 2N 15 7N 7N 1 7N 15 Example 2 Receive a video datastream of bytes R G B pixels N M image size DMAx_X_MODIFY N M DMAx_X_COUNT 3 DMAx_Y_MODIFY 1 2 N M negative DMAx_Y_COUNT N M This produces the following address offsets from the start address 0 N M ...

Page 250: ...one descriptor is called a work unit Optionally an interrupt can be requested at the end of any work unit by setting the DI_EN bit in the configuration word of the respective descriptor A DMA channel is started in descriptor based mode by first writing the 32 bit address of the first descriptor into the DMAx_NEXT_DESC_PTR register or the DMAx_CURR_DESC_PTR in case of descriptor array mode and then...

Page 251: ... upper 16 bits of the DMAx_NEXT_DESC_PTR register are not updated Descriptor list modes are started by writing first to the DMAx_NEXT_DESC_PTR register and then to the DMAx_CONFIG register Descriptor Array Mode Descriptor array mode is selected by setting the FLOW bit field in the DMA channel s DMAx_CONFIG register to 0x4 In this mode the descriptors do not contain further descriptor pointers The ...

Page 252: ...ain their prior val ues although the DMAx_CURR_ADDR DMAx_CURR_X_COUNT and DMAx_CURR_Y_COUNT registers are reloaded between the descriptor fetch and the start of DMA operation Table 7 1 shows the offsets for descriptor elements in the three modes described above Note the names in the table describe the descriptor ele ments in memory not the actual MMRs into which they are eventually loaded For more...

Page 253: ... is required to stop after a certain descriptor has been processed the last descriptor is typically pro cessed in stop mode That is its FLOW and NDSIZE fields are 0 but its DMAEN bit is still set Functional Description The following sections provide a functional description of DMA DMA Operation Flow Figure 7 1 and Figure 7 2 describe the DMA flow DMA Startup This section discusses starting DMA fro...

Page 254: ...e user may wish to write other DMA registers that might be static dur ing DMA activity for example DMAx_X_MODIFY DMAx_Y_MODIFY The contents of NDSIZE and FLOW in DMAx_CONFIG indicate which registers if any are fetched from descriptor elements in memory After the descriptor fetch if any is completed DMA operation begins initiated by writing DMAx_CONFIG with DMAEN 1 ...

Page 255: ...H COUNTERS B COPY NEXT DESCRIPTOR POINTER TO CURRENT DESCRIPTOR POINTER USER WRITES SOME OR ALL DMA PARAMETER REGISTERS AND THEN WRITES DMA_CONFIG SET DFETCH IN IRQ_STATUS SET DMA_RUN IN IRQ_STATUS BAD DMA_CONFIG TEST DMAEN TEST FLOW TEST FLOW Y N DMA ERROR DMAEN 1 DMAEN 0 FLOW 4 6 OR 7 DMA STOPPED CLEAR DMA_RUN IN IRQ_STATUS FLOW 0 OR 1 A C DI_EN 0 OR DI_EN 1 AND DMA_DONE_IRQ 1 FLOW 4 FLOW 6 OR 7...

Page 256: ... COUNTS EXPIRE TEST DI_EN TEST FLOW TEST SYNC WNR DMA STOPPED CLEAR DMA_RUN IN IRQ_STATUS MEMORY WRITE DESTINATION SYNC 0 MEMORY READ FLOW 0 DI_EN 0 DI_EN 1 SIGNAL AN INTERRUPT TO THE CORE SET DMA_DONE IN IRQ_STATUS TRANSFER DATA FROM FIFO TO PERIPHERAL UNTIL EMPTY MAX SIZE DEPENDS ON FLOW IF FLOW 4 MAX_SIZE 7 IF FLOW 6 MAX_SIZE 8 IF FLOW 7 MAX_SIZE 9 NDSIZE 0 OR NDSIZE MAX_SIZE NDSIZE 0 AND NDSIZ...

Page 257: ...n memory while the NDSIZE bits detail how many descriptor elements to fetch before starting DMA DMA registers not included in the descriptor are not modified from their prior values If the FLOW value specifies small or large descriptor list modes the DMAx_NEXT_DESC_PTR is copied into DMAx_CURR_DESC_PTR Then fetches of new descriptor elements from memory are performed indexed by DMAx_CURR_DESC_PTR ...

Page 258: ...attempts to fill its FIFO subject to channel prior ity a memory write RX DMA channel begins accepting data from its peripheral and a memory read TX DMA channel begins memory reads provided the channel wins the grant for bus access When the DMA channel performs its first data memory access its address and count computations take their input operands from the start registers DMAx_START_ADDR DMAx_X_C...

Page 259: ... in FLOW modes 4 6 and 7 the DMA controller sets the DFETCH bit in DMAx_IRQ_STATUS register to 1 At this point the DMA operation depends on whether FLOW 4 6 or 7 as fol lows If FLOW 4 descriptor array the DMA controller loads a new descriptor from memory into the DMA registers using the contents of DMAx_CURR_DESC_PTR and increments DMAx_CURR_DESC_PTR The descriptor size comes from the NDSIZE field...

Page 260: ...RR_DESC_PTR The first descriptor element that is loaded is a new 32 bit value for the full DMAx_NEXT_DESC_PTR fol lowed by the rest of the descriptor elements The high 16 bits of DMAx_NEXT_DESC_PTR may differ from their former value This sup ports a fully flexible descriptor list which can be located anywhere in internal memory or external memory If it is necessary to link from a descriptor chain ...

Page 261: ...at the cost of restrictions on changes of data format or addressed memory space in the two work units These latency gains and data restrictions arise from the way the DMA FIFO pipeline is handled while the next descriptor is fetched In continuous transitions SYNC 0 the DMA FIFO pipeline continues to transfer data to and from the peripheral or destination memory during the descriptor fetch and or w...

Page 262: ...m memory the following operations start in parallel The interrupt if any is signalled The DMA_DONE bit in the DMAx_IRQ_STATUS register is set The next descriptor begins to be fetched The final data items are delivered from the DMA FIFO to the des tination memory or peripheral This allows the DMA to provide data from the FIFO to the peripheral continuously during the descriptor fetch latency period...

Page 263: ...re any interrupt is signalled and before any subsequent descriptor or data is fetched This incurs greater latency but provides direct synchronization between the DMA interrupt and the state of the data at the peripheral For example if SYNC 1 and DI_EN 1 on the last descriptor in a work unit the interrupt occurs when the final data has been transferred to the peripheral allowing the service routine...

Page 264: ...hain must not change from the word size of the previous descriptor chain active before the pause unless the DMA channel is reset between chains by writing the DMAEN bit to 0 and then to 1 again If the SYNC bit is 1 in the new work unit s DMAx_CONFIG value a synchro nized transition is selected In this mode only the data received from the peripheral by the DMA channel after the write to the DMAx_CO...

Page 265: ...he final DMACFG element should have a FLOW 0 setting to gracefully stop the channel In autobuffer FLOW 1 mode or if a list or array of descriptors without DMACFG elements is used then the DMA transfer process must be termi nated by an MMR write to the DMAx_CONFIG register with a value whose DMAEN bit is 0 A write of 0 to the entire register will always terminate DMA gracefully without DMA abort If...

Page 266: ...pt is asserted There is only one DMA_ERROR interrupt for the whole DMA controller which is asserted whenever any of the channels has detected an error condition The DMA_ERROR interrupt handler must Read each channel s DMAx_IRQ_STATUS register to look for a channel with the DMA_ERR bit set bit 1 Clear the problem with that channel for example fix register values Clear the DMA_ERR bit write DMAx_IRQ...

Page 267: ... DMAx_CURR_DESC_PTR register crossed a memory boundary A memory access error occurred Either an access attempt was made to an internal address not populated or defined as cache or an external access caused an error signaled by the external memory interface Some prohibited situations are not detected by the DMA hardware No DMA abort is signaled for these situations DMAx_CONFIG direction bit WNR doe...

Page 268: ...sist of three wires per DMA management capable peripheral The DMA control commands extend the set of operations available to the peripheral beyond the simple request data command used by peripherals in general While these DMA control commands are not visible to or controllable by the user their use by a peripheral has implications for the structure of the DMA transfers which that peripheral can su...

Page 269: ...emory read receives a Restart command the channel momentarily pauses while any pending memory reads initiated prior to the Restart command are completed During this period of time the channel does not grant DMA requests Once all pending reads have been flushed from the chan nel s pipelines the channel resets its counters and FIFO and starts prefetch reads from memory DMA data requests from the Tab...

Page 270: ...ected by the DI_EN bit The peripheral can thus use the Finish command to partition the DMA stream into work units on its own perhaps as a result of parsing the data currently passing though its supported communication channel without direct real time control by the processor If a channel programmed for transmit memory read receives a Finish command the channel momentarily pauses while any pend ing...

Page 271: ...ent capable peripheral might use this command if an internal FIFO is approaching a critical condition Restrictions The proper operation of the 4 location DMA channel FIFO leads to cer tain restrictions in the sequence of DMA control commands Transmit Restart or Finish No Restart or Finish command may be issued by a peripheral to a chan nel configured for memory read unless the peripheral has alrea...

Page 272: ...rmed then at least one data item has been written to memory in the current work unit which implies that the cur rent work unit s descriptor fetch completed before the data grant of the fifth item Otherwise if less than five data items have been transferred it is possible that all of them are still in the DMA FIFO and the previous work unit is still in the process of completion and transition betwe...

Page 273: ...ndshake hardware works com pletely independently from the descriptor and autobuffer capabilities of the MDMA allowing most flexible combinations of logical data organiza tion vs data portioning as required by FIFO depths for example If however the connected device requires certain behavior of the address lines these must be controlled by traditional DMA setup The HMDMA unit controls only the desti...

Page 274: ...register even during normal operation by setting the RBC bit in the HMDMAx_CONTROL register Set RBC when the HMDMA module is already active but only when the MDMA is not enabled Pipelining DMA Requests The device mastering the DMA request lines is allowed to request addi tional transfers even before the former transfer has completed As long as the device can provide or consume sufficient data it i...

Page 275: ...s The Blackfin processor does not evaluate the full flag such FIFOs usually provide because asynchronous polling of that sig nal would reduce the system throughput drastically Moreover the processor first fills the FIFO by initializing the HMDMAx_ECINIT register to 1024 which equals the depth of the FIFO Once enabled the MDMA automatically transmits 1024 data words Afterward it continues to trans ...

Page 276: ...IFO is not half filled On internal system buses memory DMA channels have lower priority than other DMAs In busy systems the memory DMAs may tend to starve As this is not acceptable when transferring data through high speed FIFOs the handshake mode provides a high water functionality to increase the MDMA s priority With the UTE bit in the HMDMAx_CONTROL register set the MDMA gets higher priority as...

Page 277: ...LOW It resets to 0xFFFF and should be written with any positive value by the user before enabling the function by the OIE bit Then the overflow interrupt is issued when the value of the HMDMA_ECOUNT register exceeds the threshold in the HMDMA_ECOVERFLOW register DMA Performance The DMA system is designed to provide maximum throughput per chan nel and maximum utilization of the internal buses while...

Page 278: ...p memory Chapter 3 Chip Bus Hierarchy explains the bus architecture Each peripheral DMA channel has its own data FIFO which lies between the DAB bus and the memory buses These FIFOs automatically prefetch data from memory for transmission and buffer received data for later memory writes This allows the peripheral to be granted a DMA transfer with very low latency compared to the total latency of a...

Page 279: ...elays for example when both the core and the DMA access the same L1 bank when SDRAM pages need to be opened closed or when cache lines are filled Direction changes from RX to TX on the DAB bus impose a one SCLK cycle delay Direction changes on the DCB bus for example write followed by read to the same bank of internal memory can impose delays Direction changes for example read followed by write on...

Page 280: ...ssor s traffic control features described in the next section The MDMA channels are clocked by SCLK If the source and destination are in different memory spaces one internal and one external the inter nal and external memory transfers are typically simultaneous and continuous maintaining 100 bus utilization of the internal and external memory interfaces This performance is affected by core to syst...

Page 281: ...s 8 location FIFO After a latency of two SCLK cycles the destination MDMA channel begins writing data to the destination memory buffer Static Channel Prioritization DMA channels are ordinarily granted service strictly according to their priority The priority of a channel is simply its channel number where lower priority numbers are granted first Thus peripherals with high data rates or low latency...

Page 282: ...e place before the end of the peripheral s regular interval system failure may result To minimize this possibility the DMA unit detects peripherals whose need for data has become urgent and preferentially grants them service at the highest priority A DMA channel s request for memory service is defined as urgent if both The channel s FIFO is not ready for a DAB bus transfer that is a transmit FIFO ...

Page 283: ...rgent request may be accommodated The preferential handling of urgent DMA transfers is completely auto matic No user controls are required for this function to operate Memory DMA Priority and Scheduling All MDMA operations have lower precedence than any peripheral DMA operations MDMA thus makes effective use of any memory bandwidth unused by peripheral DMA traffic By default when more than one MDM...

Page 284: ...dth For example one stream might be programmed for internal to external moves while the other is programmed for exter nal to internal moves and each would be allocated approximately equal data bandwidth In round robin operation the MDMA stream selection at any time is either free or locked Initially the selection is free On any free cycle available to MDMA when no peripheral DMA accesses take prec...

Page 285: ...pherals that are request ing DMA via the DAB bus and whose data FIFOs are ready to handle the transfer compete with each other for DAB bus cycles Similarly but sepa rately channels whose FIFOs need memory service prefetch or post write compete together for access to the memory buses MDMA streams compete for memory access as a unit and source and destination may be granted together if their memory ...

Page 286: ...o the opposite flow direction These directional preferences work as if the priority of the opposite direction channels were decreased by 16 For example if channels 3 and 5 were requesting DAB access but lower priority channel 5 is going with traffic and higher priority channel 3 is going against traffic then channel 3 s effective priority becomes 19 and channel 5 would be granted instead If on the...

Page 287: ...heral can use a linked descriptor list interrupt driven scheme while another peripheral can simultaneously use a demand driven buffer at a time scheme syn chronized by polling of the DMAx_IRQ_STATUS register Synchronization of Software and DMA A critical element of software DMA management is synchronization of DMA buffer completion with the software This can best be done using interrupts polling o...

Page 288: ...slow operation of channel A Software monitoring of channel B based on examination of the DMAx_CURR_ADDR register contents would not safely conclude whether the memory location pointed to by channel B s DMAx_CURR_ADDR register has or has not been written If allowances are made for the lengths of the DMA memory pipeline poll ing of the current address pointer and count registers can permit loose syn...

Page 289: ...her wait for an interrupt or consult the channel s DMAx_IRQ_STATUS register to confirm completion of DMA rather than polling current address pointer count registers When the DMA system issues an interrupt or changes a DMAx_IRQ_STATUS bit it guarantees that the last memory operation of the work unit has been completed and will definitely be visible to processor code For memory read DMA the final me...

Page 290: ...DMA is transferred from or to a memory buffer with a circular addressing scheme using either one or two dimensional indexing with zero proces sor and DMA overhead for looping Synchronization options include 1 D interrupt driven software is interrupted at the conclusion of each buffer The critical design consideration is that the software must deal with the first items in the buffer before the next...

Page 291: ...sub buffers 2 D polled if interrupt overhead is unacceptable but the loose synchronization of address count register polling is acceptable a 2 D multibuffer synchronization scheme may be used For exam ple assume receive data needs to be processed in packets of sixteen 32 bit elements A four part 2 D DMA buffer can be allocated where each of the four sub buffers can hold one packet with these setti...

Page 292: ...he DMA channel may be programmed using 1 D autobuffer mode addressing without any interrupts or polling Descriptor Structures DMA descriptors may be used to transfer data to or from memory data structures that are not simple 1 D or 2 D arrays For example if a packet of data is to be transmitted from several different locations in memory a header from one location a payload from a list of several b...

Page 293: ...s must all agree with the current descriptor The WDSIZE DI_EN DI_SEL SYNC and DMA2D fields will be taken from the DMAx_CONFIG value in the descriptor read from memory The field values initially written to the register are ignored See Initializing Descriptors in Memory on page 7 95 in the Programming Examples section for infor mation on how descriptors can be set up Descriptor Queue Management A sy...

Page 294: ...enabling an interrupt on every descriptor This method should only be used if system design can guarantee that each interrupt event will be serviced separately no interrupt overrun To maintain synchronization of the descriptor queue the non interrupt software maintains a count of descriptors added to the queue while the interrupt handler maintains a count of completed descriptors removed from the q...

Page 295: ... there are no more descriptors to process or because the last descriptor was queued too late the modification of the next to last descriptor s DMAx_CONFIG element occurred after that element was read into the DMA unit In this case the interrupt handler should write the DMAx_CONFIG value appropriate for the last descriptor to the DMA channel s DMAx_CONFIG register increment the completed descriptor...

Page 296: ...ive queue and then issue one interrupt Also this arrange ment makes it easy to start the waiting queue within the interrupt handler with a single DMAx_CONFIG register write After queuing a new waiting descriptor the non interrupt software should leave a message for its interrupt handler in a memory mailbox location containing the desired DMAx_CONFIG value to use to start the first waiting descript...

Page 297: ...NFIG reg ister If the queue is not stopped the non interrupt software must not write to the DMAx_CONFIG register which would cause a DMA error Instead the descriptor should queue to the waiting queue and update its mailbox directed to the interrupt handler Software Triggered Descriptor Fetches If a DMA has been stopped in FLOW 0 mode the DMA_RUN bit in the DMAx_IRQ_STATUS register remains set unti...

Page 298: ... of oper ation the NDSIZE field should at least span up to the DMACFG field to overwrite the configuration register immediately One possible procedure is 1 Write to DMAx_NEXT_DESC_PTR 2 Write to DMAx_CONFIG with FLOW 0x8 NDSIZE 0xA DI_EN 0 DMAEN 1 3 Automatically fetched DMACFG has FLOW 0x0 NDSIZE 0x0 SYNC 1 for transmitting DMAs only DI_EN 1 DMAEN 1 4 In the interrupt routine repeat step 2 The DM...

Page 299: ...s way the whole DMA transaction can be broken into pieces that are individually triggered by software Source and destination channels of a MDMA may differ in descrip tor structure However the total work count must match when the DMA stops Whenever a MDMA is stopped destination and source channels should both provide the same FLOW 0 mode after exactly the same number of words Accordingly both chann...

Page 300: ... Registers MMR Offset Generic MMR Name MMR Description Register Category Name of Corresponding Descriptor Element in Memory 0x00 NEXT_DESC_PTR Link pointer to next descrip tor Parame ter NDPH upper 16 bits NDPL lower 16 bits 0x04 START_ADDR Start address of current buffer Parame ter SAH upper 16 bits SAL lower 16 bits 0x08 CONFIG DMA Configuration register including enable bit Parame ter DMACFG 0x...

Page 301: ...annel is called MDMA_S1_CONFIG 0x28 IRQ_STATUS Interrupt status register con tains completion and DMA error interrupt status and channel state run fetch paused Control Status N A 0x2C PERIPHERAL_MAP Peripheral to DMA channel mapping contains a 4 bit value specifying the periph eral associated with this DMA channel read only for MDMA channels Control Status N A 0x30 CURR_X_COUNT Current count 1 D o...

Page 302: ...s such as DMAx_CURR_ADDR and DMAx_CURR_X_COUNT Control status registers such as DMAx_IRQ_STATUS and DMAx_PERIPHERAL_MAP All DMA registers can be accessed as 16 bit entities However the follow ing registers may also be accessed as 32 bit registers DMAx_NEXT_DESC_PTR DMAx_START_ADDR DMAx_CURR_DESC_PTR DMAx_CURR_ADDR When these four registers are accessed as 16 bit entities only the lower 16 bits can...

Page 303: ...ssume that channels 6 and 7 are involved 1 Make sure DMA is disabled on channels 6 and 7 2 Write DMA6_PERIPHERAL_MAP with 0x7000 and DMA7_PERIPHERAL_MAP with 0x6000 3 Enable DMA on channels 6 and or 7 Figure 7 5 DMA Peripheral Map Registers PMAP 3 0 Peripheral is mapped to this channel X X X X 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 X X X X X X X X X X X X DMA Peripheral Map Registers DMAx_PERIPHERA...

Page 304: ...ptor list small model 0x7 Descriptor list large model DMA Configuration Registers DMAx_CONFIG MDMA_yy_CONFIG NDSIZE 3 0 Flex Descriptor Size Size of next descriptor 0000 Required if in Stop or Autobuffer mode 0001 1001 Descriptor size 1010 1111 Reserved DMAEN DMA Channel Enable 0 Disable DMA channel 1 Enable DMA channel WNR DMA Direction 0 DMA is a memory read source operation 1 DMA is a memory wr...

Page 305: ... in memory are used Instead DMA is performed in a continuous circular buffer fashion based on user programmed DMA MMR settings Upon completion of the work unit the parameter registers are reloaded into the current registers and DMA resumes immediately with zero overhead Autobuffer mode is stopped by a user write of 0 to the DMAEN bit in the DMAx_CONFIG register 0x4 descriptor array mode This mode ...

Page 306: ...ata interrupt timing select This bit specifies the timing of a data interrupt after completing the whole buffer or after completing each row of the inner loop This bit is used only in 2 D DMA operation SYNC work unit transitions This bit specifies whether the DMA channel performs a continuous transition SYNC 0 or a synchro nized transition SYNC 1 between work units For more information see Work Un...

Page 307: ...registers must be a multiple of the transfer unit size one for 8 bit two for 16 bit four for 32 bit Only SPORT DMA and Memory DMA can operate with a transfer size of 32 bits All other peripherals have a maximum DMA trans fer size of 16 bits WNR DMA direction This bit specifies DMA direction mem ory read 0 or memory write 1 DMAEN DMA channel enable This bit specifies whether to enable a given DMA c...

Page 308: ...heral there may be up to four data words in the channel s DMA FIFO when the interrupt occurs At this point it is normal to immediately start the next work unit If however the application needs to know when the final data item is actually transferred to the peripheral the application can test or poll the DMA_RUN bit As long as there is undelivered transmit data in the FIFO the DMA_RUN bit is 1 For ...

Page 309: ...s a flexible interrupt control structure with three interrupt sources Data driven interrupts see Table 7 5 Peripheral error interrupts DMA error interrupts for example bad descriptor or bus error Separate interrupt request IRQ levels are allocated for data peripheral error and DMA error interrupts ...

Page 310: ... DMA channel is disabled or it is enabled but paused FLOW mode 0 1 This DMA channel is enabled and operating either transferring data or fetching a DMA descriptor DMA Interrupt Status Registers DMAx_IRQ_STATUS MDMA_yy_IRQ_STATUS DFETCH DMA Descriptor Fetch RO DMA_RUN DMA Channel Running RO DMA_DONE DMA Comple tion Interrupt Status W1C 0 No interrupt is being asserted for this channel 1 DMA work un...

Page 311: ... no unintended interrupt is generated on the shared DMA interrupt request line DMA Start Address Registers DMAx_START_ADDR MDMA_yy_START_ADDR The DMAx_START_ADDR register shown in Figure 7 8 contains the start address of the data buffer currently targeted for DMA Figure 7 8 DMA Start Address Registers 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 X DMA Start Address 31 16 X X X X X X X X X X X X...

Page 312: ...igure 7 10 contains the inner loop count For 1 D DMA it specifies the number of elements to transfer For details see Two Dimensional DMA Operation on page 7 11 A value of 0 in DMAx_X_COUNT corresponds to 65 536 elements Figure 7 9 DMA Current Address Registers 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 X Current Address 31 16 X X X X X X X X X X X X X X X DMA Current Address Registers DMAx_CU...

Page 313: ...is occurs at the same time that the value in the DMAx_CURR_Y_COUNT register is decremented Otherwise it is decremented each time an element is transferred Expiration of the count in this register signifies that DMA is complete In 2 D DMA the DMAx_CURR_X_COUNT register value is 0 only when the entire transfer is complete Between rows it is equal to the value of the DMAx_X_COUNT register Figure 7 10...

Page 314: ...Y_MODIFY register is applied instead except on the very last transfer of each work unit The DMAx_X_MODIFY register is always applied to the last transfer of a work unit The DMAx_X_MODIFY field may be set to 0 In this case DMA is performed repeatedly to or from the same address This is useful for example in transferring data between a data register and an external memory mapped peripheral Figure 7 ...

Page 315: ...Figure 7 13 DMA Outer Loop Count Registers 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 X X_MODIFY 15 0 Inner Loop Address Increment X X X X X X X X X X X X X X X DMA Inner Loop Address Increment Registers DMAx_X_MODIFY MDMA_yy_X_MODIFY R W prior to enabling channel RO after enabling channel Reset Undefined Stride in bytes to take after each decrement of CURR_X_COUNT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0...

Page 316: ...0 DMA Outer Loop Address Increment Registers DMAx_Y_MODIFY MDMA_yy_Y_MODIFY The DMAx_Y_MODIFY register contains a signed two s complement value See Figure 7 15 This byte address increment is applied after each decre ment of the DMAx_CURR_Y_COUNT register except for the last item in the 2 D array where the DMAx_CURR_Y_COUNT also expires The value is the offset between the last word of one row and t...

Page 317: ...modes this register is copied into the DMAx_CURR_DESC_PTR register Then during the descriptor fetch the DMAx_CURR_DESC_PTR register increments after each element of the descrip tor is read in In small and large descriptor list modes the DMAx_NEXT_DESC_PTR register and not the DMAx_CURR_DESC_PTR register must be pro grammed directly via MMR access before starting DMA operation Figure 7 15 DMA Outer...

Page 318: ...or descriptor list modes FLOW 6 or 7 this register is initialized from the DMAx_NEXT_DESC_PTR register before loading each descriptor Then the address in the DMAx_CURR_DESC_PTR register incre ments as each descriptor element is read in When the entire descriptor has been read the DMAx_CURR_DESC_PTR regis ter contains this value Descriptor Start Address 2x Descriptor Size of elements Figure 7 16 DM...

Page 319: ...ct HMDMA0 is associated with MDMA0 and HMDMA1 is associated with MDMA1 Handshake MDMA Control Registers HMDMAx_CONTROL The HMDMAx_CONTROL register shown in Figure 7 18 is used to set up HMDMA parameters and operating modes Figure 7 17 DMA Current Descriptor Pointer Registers 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 X Next Descriptor Pointer 31 16 X X X X X X X X X X X X X X X DMA Next Descr...

Page 320: ...active Table 7 6 DRQ 1 0 Values DRQ 1 0 Priority Description 00 Disabled The MDMA request is disabled 01 Enabled S Normal MDMA channel priority The channel in this mode is limited to single memory transfers separated by one idle system clock Request sin gle transfer from MDMA channel 10 Enabled M Normal MDMA channel functionality and priority Request multiple transfers from MDMA channel default 11...

Page 321: ...ndshake MDMA Enable 0 Disable handshake Operation 1 Enable handshake Operation REP HMDMA Request Polarity 0 Increment ECOUNT on falling edges of DMARx input 1 Increment ECOUNT on rising edges of DMARx input UTE Urgency Threshold Enable 0 Disable urgency threshold 1 Enable urgency threshold OIE Overflow Interrupt Enable 0 Disable overflow interrupt 1 Enable overflow interrupt Reset 0x0200 BDIE Bloc...

Page 322: ... loaded with BCINIT when ECOUNT is greater than 0 and BCOUNT is expired 0 Also if the RBC bit in the HMDMAx_CONTROL register is written to 1 BCOUNT is loaded with BCINIT The BCOUNT field is decre mented with each MDMA grant It is cleared when HMDMA is disabled A block done interrupt is generated when BCOUNT decrements to 0 If the MBDI bit in the HMDMAx_CONTROL register is set the interrupt is supp...

Page 323: ...nd the resulting number of requests is Number of edges N where N is the number loaded from ECINIT The number N can be posi tive or negative Examples 0x7FFF 32 767 edges remaining 0x0000 0 edges remaining 0x8000 32 768 ignore the next 32 768 edges Each time that BCOUNT expires ECOUNT is decremented and BCOUNT is reloaded from BCINIT When a handshake request edge is detected ECOUNT is incremented Th...

Page 324: ...olds the urgent threshold If the ECOUNT field in the HMDMAx_ECOUNT register is greater than this threshold the MDMA request is urgent and might get higher priority Figure 7 21 Handshake MDMA Current Edge Count Registers Figure 7 22 Handshake MDMA Initial Edge Count Registers 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 Handshake MDMA Current Edge Count Register HMDMAx_ECOU...

Page 325: ...A_TC_PER register see Figure 7 25 and the DMA_TC_CNT register see Figure 7 26 work with other DMA registers to define traffic control Figure 7 23 Handshake MDMA Edge Count Urgent Registers Figure 7 24 Handshake MDMA Edge Count Overflow Interrupt Registers 1 1 1 1 1 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 1 1 1 1 1 1 1 1 1 Handshake MDMA Edge Count Urgent Registers HMDMAx_ECURGENT UTHE 15 0 Urgen...

Page 326: ... DMA and the peripherals MDMA_ROUND_ROBIN_PERIOD 4 0 DCB_TRAFFIC_PERIOD 3 0 DEB_TRAFFIC_PERIOD 3 0 Reset 0x0000 0000 No DCB bus transfer grouping performed Other Preferred length of unidi rectional bursts on the DCB bus between the DMA and internal L1 memory 0000 No DEB bus transfer grouping performed Other Preferred length of unidi rectional bursts on the DEB bus between the DMA and external memo...

Page 327: ...ntially which may result in a direction change When this count is 0 and a DAB bus access occurs the count is reloaded from DAB_TRAFFIC_PERIOD to begin a new burst The DEB_TRAFFIC_COUNT field shows the current cycle count remaining in the DEB traffic period It initializes to DEB_TRAFFIC_PERIOD whenever DMA_TC_PER is written or whenever the DEB bus changes direction or becomes idle It then counts do...

Page 328: ...ister Based 2 D Memory DMA Listing 7 1 shows a register based two dimensional MDMA While the source channel processes linearly the destination channel re sorts ele ments by transposing the two dimensional data array See Figure 7 27 The two arrays reside in two different L1 data memory blocks However the arrays could reside in any internal or external memory including L1 instruction memory and SDRA...

Page 329: ...n L1_code global _main _main p0 l lo MDMA_S0_CONFIG p0 h hi MDMA_S0_CONFIG call memdma_setup call memdma_wait _main forever jump _main forever _main end The setup routine shown in Listing 7 2 initializes either MDMA0 or MDMA1 depending on whether the MMR address of MDMA_S0_CONFIG or MDMA_S1_CONFIG is passed in the P0 register Note that the source channel is enabled before the destination channel A...

Page 330: ...w p0 r7 setup 2D destination DMA for 16 bit transfers r7 l lo aDestination r7 h hi aDestination p0 MDMA_D0_START_ADDR MDMA_S0_CONFIG r7 r7 l 2 Y w p0 MDMA_D0_X_MODIFY MDMA_S0_CONFIG r7 r7 l Y w p0 MDMA_D0_Y_COUNT MDMA_S0_CONFIG r7 r7 l X w p0 MDMA_D0_X_COUNT MDMA_S0_CONFIG r7 r7 l 2 Y X 1 1 w p0 MDMA_D0_Y_MODIFY MDMA_S0_CONFIG r7 r7 l DMA2D DI_EN WDSIZE_16 WNR DMAEN w p0 MDMA_D0_CONFIG MDMA_S0_CON...

Page 331: ... however the descriptors or at least large portions of them can be static and there fore initialized at boot time How to set up descriptors in global memory depends heavily on the programming language and the tool set used The following examples show how this is best performed in assembly language Listing 7 4 uses multiple variables of either 16 bit or 32 bit size to describe DMA descriptors This ...

Page 332: ...descBlock1 end byte2 descBlock2 lo descBlock1 var descBlock2 addr arrBlock2 byte2 descBlock2 cfg FLOW_SMALL NDSIZE_5 DI_EN WDSIZE_16 DMAEN byte2 descBlock2 len length arrBlock2 descBlock2 end Another method takes advantage of C style structures in global header files The header file descriptors h could look like Listing 7 5 Listing 7 5 Header File to Define Descriptor Structures ifndef __INCLUDE_D...

Page 333: ...d thus pointers are always 32 bits wide Therefore the scheme above cannot be used directly for small list mode without giving up pointer syntax The variable definition file is required to import the C style header file and can finally take advantage of the structures See Listing 7 6 Listing 7 6 Using Descriptor Structures include descriptors h import descriptors h section L1_data_a align 4 var arr...

Page 334: ...the proper value into the DMA configuration registers Since these values instruct the DMA controller to fetch descriptors in large list mode the DMA immediately fetches the descriptor thus overwriting the configuration value again with the new settings when it is started Note the requirement that source and destination channels stop after the same number of transfers Between stops the two channels...

Page 335: ...Source3 arrSource2 FLOW_LARGE NDSIZE_7 WDSIZE_16 DMAEN length arrSource2 2 0 0 unused values struct dma_desc_list descSource3 descSource1 arrSource3 WDSIZE_16 DMAEN length arrSource3 2 0 0 unused values struct dma_desc_list descDest1 descDest2 arrDest1 DI_EN WDSIZE_16 WNR DMAEN length arrDest1 2 0 0 unused values struct dma_desc_list descDest2 descDest1 arrDest2 DI_EN WDSIZE_16 WNR DMAEN length ar...

Page 336: ...rk unit r6 l FLOW_LARGE NDSIZE_7 WDSIZE_16 DMAEN w p0 MDMA_S0_CONFIG MDMA_S0_CONFIG r6 r7 l FLOW_LARGE NDSIZE_7 WDSIZE_16 WNR DMAEN w p0 MDMA_D0_CONFIG MDMA_S0_CONFIG r7 wait until destination channel has finished and W1C latch _main wait r0 w p0 MDMA_D0_IRQ_STATUS MDMA_S0_CONFIG z CC bittst r0 bitpos DMA_DONE if CC jump _main wait r0 l DMA_DONE w p0 MDMA_D0_IRQ_STATUS MDMA_S0_CONFIG r0 wait for a...

Page 337: ...e HMDMA module is enabled before the MDMA channels Listing 7 8 enables the HMDMA1 block which is controlled by the DMAR1 pin and is associated with the MDMA1 channel pair Listing 7 8 HMDMA1 Block Enable optionally enable all four bank select strobes p1 l lo EBIU_AMGCTL p1 h hi EBIU_AMGCTL r0 l 0x0009 w p1 r0 function enable for DMAR1 p1 l lo PORTG_FER r0 l PG12 w p1 r0 p1 l lo PORTG_MUX r0 l 0x000...

Page 338: ...it starts filling the DMA FIFO immediately In 16 bit DMA mode this results in eight read strobes on the EBIU even before the first DMAR1 event has been detected In other words the transferred data and the DMAR1 strobes are eight posi tions off The example in Listing 7 9 delays processing until eight DMAR1 requests have been received By doing so the transmitter is required to add eight trailing dum...

Page 339: ... by using the HMDMA overflow feature Temporarily set the HMDMAx_OVERFLOW register to eight Unique Information for the ADSP BF50x Processor Figure 7 28 provides a block diagram of the ADSP BF50x DMA controller The ADSP BF50x processors do not contain an SDRAM interface or an HMDMA controller Therefore any discussion or examples above regarding SDRAM and HMDMA do not apply to the ADSP BF50x processo...

Page 340: ...PMAP FIFO DMA 5 CONTROL PMAP FIFO DMA 6 CONTROL PMAP FIFO DMA 7 CONTROL PMAP FIFO DMA 8 CONTROL PMAP FIFO DMA 9 CONTROL PMAP FIFO DMA 10 CONTROL PMAP FIFO DMA 11 CONTROL PMAP FIFO MDMA 1 DESTINATION CONTROL FIFO MDMA 1 SOURCE CONTROL MDMA 0 DESTINATION CONTROL FIFO MDMA 0 SOURCE CONTROL DMA TRAFFIC CONTROL IRQ 14 IRQ 15 IRQ 16 IRQ 17 IRQ 18 IRQ 19 IRQ 20 IRQ 21 IRQ 22 IRQ 23 IRQ 24 IRQ 25 IRQ 43 I...

Page 341: ...lt Value Peripheral Mapped by Default Highest DMA 0 0x0 PPI receive or transmit DMA 1 0x1 RSI receive or transmit DMA 2 0x2 SPORT0 receive DMA 3 0x3 SPORT0 transmit DMA 4 0x4 SPORT1 receive DMA 5 0x5 SPORT1 transmit DMA 6 0x6 SPI0 receive or transmit DMA 7 0x7 SPI1 receive or transmit DMA 8 0x8 UART0 receive DMA 9 0x9 UART0 transmit DMA 10 0xA UART1 receive DMA 11 0xB UART1 transmit MDMA D0 None M...

Page 342: ...Unique Information for the ADSP BF50x Processor 7 106 ADSP BF50x Blackfin Processor Hardware Reference ...

Page 343: ...mming Examples on page 8 29 Phase Locked Loop and Clock Control The input clock into the processor CLKIN provides the necessary clock frequency duty cycle and stability to allow accurate internal clock multi plication by means of an on chip PLL module During normal operation the user programs the PLL with a multiplication factor for CLKIN The resulting multiplied signal is the voltage controlled o...

Page 344: ...rves a wide range of applications It emphasizes embed ded and portable applications and low cost general purpose processors in which performance flexibility and control of power dissipation are key features This broad range of applications requires a wide range of fre quencies for the clock generation circuitry The input clock may be a crystal a crystal oscillator or a buffered shaped clock derive...

Page 345: ... 64 1 2 4 OR 8 1 15 SSEL 3 0 MSEL 5 0 CSEL 1 0 DF SCLK GATE GATE SCLK CCLK PDWN DEEP SLEEP POWERDOWN CCLK AND SCLK OFF STOPCK SLEEP MODE STOP CLOCK CCLK OFF BYPASS ACTIVE MODE CCLK SCLK CLKIN PHASE LOCKED LOOP fCLKIN fCLKIN fVCO PLL_OFF DISABLE CONTROL INPUT TO PLL CAN ADDITIONALLY BE USED WITH BYPASS CLKIN CLKOUT SCLK XTAL SELECT CLKBUF TO PLL CIRCUITRY FOR OVERTONE OPERATION ONLY NOTE VALUES MAR...

Page 346: ...trols the feedback dividers The reset value of MSEL is 0x6 This value can be reprogrammed at startup in the boot code Table 8 1 illustrates the VCO multiplication factors for the various MSEL and DF settings As shown in the table different combinations of MSEL 5 0 and DF can generate the same VCO frequencies For a given application one combi nation may provide lower power or satisfy the VCO maximu...

Page 347: ...y to the system clock Note the divider ratio must be chosen to limit the SCLK to a frequency specified in the processor data sheet The SCLK drives all synchronous system level logic The divider ratio control bits CSEL and SSEL are in the PLL divide PLL_DIV register For information about this register see PLL_DIV Register on page 8 20 The reset value of CSEL 1 0 is 0x0 and the reset value of SSEL 3...

Page 348: ...ed If changing the clock ratio via writing a new SSEL value into PLL_DIV take care that the enabled peripherals do not suffer data loss due to SCLK frequency changes Table 8 2 Core Clock Ratio Signal Name CSEL 1 0 Divider Ratio VCO CCLK Example Frequency Ratios MHz VCO CCLK 00 1 300 300 01 2 300 150 10 4 400 100 11 8 400 50 Table 8 3 System Clock Ratio Signal Name SSEL 3 0 Divider Ratio VCO SCLK E...

Page 349: ... about PLL stabilization time and programmed values for this register For more information about operating modes see Operating Modes on page 8 8 Dynamic Power Management Controller The Dynamic Power Management Controller DPMC works in conjunc tion with the PLL allowing the user to control the processor s performance characteristics and power dissipation dynamically The DPMC provides these features...

Page 350: ...e If the core is in the IDLE state it can be awakened by several sources see Chapter 4 System Interrupts for details The following sections describe the DPMC PLL states in more detail as they relate to the power management controller functions Full On Mode Full on mode is the maximum performance mode In this mode the PLL is enabled and not bypassed Full on mode is the normal execution state of the...

Page 351: ...the PLL If disabled the PLL must be re enabled before transitioning to full on or sleep modes From active mode the processor can transition directly to full on sleep or deep sleep modes In this mode or in the transition phase to other modes changes to MSEL are not latched by the PLL Sleep Mode Sleep mode significantly reduces power dissipation by idling the processor core The CCLK is disabled in t...

Page 352: ...grammable flag pin including PH0 PF8 or PF9 or by a wakeup event on the programmable flag pin associated with the CAN_RX signal PG1 A hardware reset begins the hardware reset sequence For more information about hardware reset see Chapter 4 System Inter rupts A programmable flag event causes the processor to transition to active mode and execution resumes at the program counter value at which the p...

Page 353: ...ram ellipses represent operating modes and rectangles represent processor states Arrows show the allowed transitions into and out of each mode or state For mode transitions the text next to each transition arrow shows the fields in the PLL control PLL_CTL register that must be changed for the transition to occur For example the transition from full on mode to sleep mode indicates that the STOPCK b...

Page 354: ...Reset WAKEUP BYPASS 0 STOPCK 1 PDWN 0 PDWN 1 PDWN 1 STOPCK 1 PDWN 0 HARDWARE RESET BYPASS 0 PLL_OFF 0 STOPCK 0 PDWN 0 BYPASS 1 STOPCK 0 PDWN 0 WAKEUP BYPASS 1 Hibernate HARDWARE RESET HIBERNATEB 0 HIBERNATEB 0 MSEL new value PLL_OFF 0 BYPASS 0 GPIO ASSERTION GPIO WAKEUP ENABLED CAN RX ACTIVITY CAMWE 1 GPIO ASSERTION GPIO WAKEUP ENABLED CAN RX ACTIVITY CAMWE 1 ...

Page 355: ...he PLL_OFF bit in the PLL_CTL register and then execute the PLL pro gramming sequence PLL enabled When the PLL is disabled it can be re enabled later when additional performance is required The PLL must be re enabled before transitioning to the full on or sleep operating modes To re enable the PLL clear the PLL_OFF bit in the PLL_CTL register and then execute the PLL programming sequence New multi...

Page 356: ...en See System Control ROM Function on page 8 23 for more information If the PLL_CTL register changes include a new CLKIN to VCO multiplier or power is reapplied to the PLL the PLL needs to relock To relock the PLL lock counter is cleared first then starts incrementing once per SCLK cycle After the PLL lock counter reaches the value programmed in the PLL lock count PLL_LOCKCNT register the PLL sets...

Page 357: ...rrent value to the new value before writing the new value When the wake up signal is asserted the code execution continues the instruction after the IDLE instruction causing a transition to Active mode if BYPASS in the PLL_CTL register is set Full on mode if the BYPASS bit is cleared If the PLL_CTL register is programmed to enter the sleep operating mode the processor transitions immediately to sl...

Page 358: ...tails on the allowed voltage ranges for each power domain and power dissipation data Power Supply Management VDDINT is supplied by an external regulator and pin PG is used to accept an active low power good indicator from the regulator Note that the external regulator must comply with the VDDINT specifications defined in the processor data sheet Changing Voltage When changing the voltage using an ...

Page 359: ...ificant changes to the operating voltage level To ensure predictable behavior the recommended procedure is to bring the processor to the sleep operating mode before substantially varying the voltage The user must ensure a stable voltage and give the PLL time to re lock at the new voltage level This can be done by running the core in a loop for a certain amount of time before leaving active mode Af...

Page 360: ...ertion of the RESET pin always exits hibernate state and requires no modification to VR_CTL External GPIO event Set a GPIO wakeup enable control bit PH0WE PF8WE PF9WE to enable wakeup on assertion of a signal on the corresponding pin External CAN RX event Set the CAN RX wakeup enable control CANWE bit to enable wakeup on the occurrence of a CAN RX event Pin EXT_WAKE is provided to indicate the occ...

Page 361: ...he appropriate wakeup enable bit or bits PH0WE PF8WE PF9WE or CANWE are set to 1 3 The bfrom_SysControl routine executes until VDDINT transi tions to 0 V The bfrom_SysControl routine never returns 4 When the processor is woken up the PLL relocks and the boot sequence defined by the BMODE 2 0 pin settings takes effect The WURESET bit in the SYSCTRL register is set and stays set until the next hardw...

Page 362: ...n page 8 20 PLL_STAT PLL status register Monitors active modes of operation Figure 8 5 on page 8 21 PLL_LOCKCNT PLL lock count register Number of SCLKs allowed for PLL to relock Figure 8 6 on page 8 22 VR_CTL Voltage regulator control register Requires PLL repro gramming sequence when written Figure 8 7 on page 8 22 Figure 8 3 PLL Divide Register PLL Divide Register PLL_DIV 15 14 13 12 11 10 9 8 7...

Page 363: ...lier Select DF Divide Frequency 0 Pass CLKIN to PLL 1 Pass CLKIN 2 to PLL PLL_OFF 0 Enable control of PLL 1 Disable control of PLL STOPCK Stop Clock 0 CCLK on 1 CCLK off PDWN Power Down 0 All internal clocks on 1 All internal clocks off Reset 0x0C80 0xFFC0 0000 0 0 0 0 0 0 0 0 0 0 PLL Status Register PLL_STAT Read only Unless otherwise noted 1 Processor operating in this mode For more infor mation...

Page 364: ...1 1 0 0 1 1 Voltage Regulator Control Register VR_CTL 0 0xFFC0 0008 POLARITY 0 Active Low level initiates wakeup 1 Active High Level initiates wakeup EXTCLK_OE 0 disable EXTCLK pin 1 enable EXTCLK pin Reserved HIBERNATEB 0 Deassert EXT_WAKE pin and enter hibernate state 1 Writing 1 has no effect Reset 0x30B0 0 1 0 0 EXTCLK_SEL 0 EXTCLK pin drives CLKBUF signal 1 EXTCLK pin drives CLKOUT signal PH0...

Page 365: ...output enable EXTCLK_OE control bit configures the EXTCLK pin to either enable when set 1 or disable when cleared 0 the output of the clock signal selected by EXTCLK_SEL When EXTCLK_OE is cleared the EXTCLK pin is three stated The POLARITY control bit configure the active level of the wakeup event on the programmable flags Note that the CAN RX wakeup event is always active low and is not affected ...

Page 366: ...TVOLTAGE 0x00000020 define SYSCTRL_PLLCTL 0x00000100 define SYSCTRL_PLLDIV 0x00000200 define SYSCTRL_LOCKCNT 0x00000400 define SYSCTRL_PLLSTAT 0x00000800 With SYSCTRL_READ and SYSCTRL_WRITE a read or a write operation is ini tialized The SYSCTRL_SYSRESET flag performs a system reset while the SYSCTRL_SOFTRESET flag combines a core and system reset The SYSCTRL_EXTVOLTAGE flag indicates that VDDINT ...

Page 367: ...Model The programming model for the system control ROM function in C C and Assembly is described in the following sections Accessing the System Control ROM Function in C C To read the PLL_DIV and PLL_CTL register values for example specify the SYSCTRL_READ instruction flag along with the SYSCTRL_PLLCTL and SYSCTRL_PLLDIV register flags ADI_SYSCTRL_VALUES read bfrom_SysControl SYSCTRL_READ SYSCTRL_...

Page 368: ...RL_WRITE SYSCTRL_PLLCTL SYSCTRL_PLLDIV write NULL Accessing the System Control ROM Function in Assembly The assembler supports C structs which is required to import the file bfrom h include bfrom h IMPORT bfrom h STRUCT ADI_SYSCTRL_VALUES dpm You can pre load the struct STRUCT ADI_SYSCTRL_VALUES dpm 0x70B0 0x1480 0x0004 0x0200 0x00A2 or load the values dynamically inside the code P5 H hi dpm P5 L ...

Page 369: ...t conventions the parameters passed are hold by the data registers R0 R1 and R2 10 sizeof ADI_SYSCTRL_VALUES uimm18m4 18 bit unsigned field that must be a multiple of 4 with a range of 8 through 262 152 bytes 0x00000 through 0x3FFFC link sizeof ADI_SYSCTRL_VALUES 2 SP R7 0 P5 0 Allocate at least 12 bytes on the stack for outgoing argu ments even if the function being called requires less than this...

Page 370: ...nsigned field that must be a multiple of 4 with a range of 8 through 262 152 bytes 0x00000 through 0x3FFFC link sizeof ADI_SYSCTRL_VALUES 2 SP R7 0 P5 0 Allocate at least 12 bytes on the stack for outgoing argu ments even if the function being called requires less than this SP 12 R7 0 R7 L 0x70B0 w FP sizeof ADI_SYSCTRL_VALUES offse tof ADI_SYSCTRL_VALUES uwVrCtl R7 R7 L 0x1480 w FP sizeof ADI_SYS...

Page 371: ...SYSCONTROL P5 L lo BFROM_SYSCONTROL call P5 SP 12 R7 0 P5 0 SP unlink rts Programming Examples The following code examples illustrate how to use the system control ROM function to effect various operating mode transitions The following examples are only meant to demonstrate how to pro gram the PLL registers Do not assume that the voltages and frequencies shown in the examples are supported by your...

Page 372: ...L_LOCKCNT register setting 0x0200 Clock in CLKIN frequency 25 MHz VCO frequency is 125 MHz core clock frequency is 125 MHz and sys tem clock frequency is 31 25 MHz Voltage regulator control VR_CTL register setting 0x70B0 Logical voltage level VDDINT is at 1 20 V For operating mode transition and voltage regulator examples C include blackfin h include bfrom h Assembly include blackfin h include bfr...

Page 373: ...ctive Mode C void active void ADI_SYSCTRL_VALUES active bfrom_SysControl SYSCTRL_READ SYSCTRL_EXTVOLTAGE SYSCTRL_PLLCTL active NULL active uwPllCtl BYPASS PLL_OFF PLL_OFF bit optional bfrom_SysControl SYSCTRL_WRITE SYSCTRL_EXTVOLTAGE SYSCTRL_PLLCTL active NULL return Listing 8 2 Transitioning from Full on Mode to Active Mode ASM __active link sizeof ADI_SYSCTRL_VALUES 2 SP R7 0 P5 0 SP 12 R0 SYSCT...

Page 374: ..._WRITE SYSCTRL_EXTVOLTAGE SYSCTRL_PLLCTL R1 FP R1 sizeof ADI_SYSCTRL_VALUES R2 0 z IMM32 P4 BFROM_SYSCONTROL call P4 SP 12 R7 0 P5 0 SP unlink rts __active end To return from active mode go back to full on mode the BYPASS bit and the PLL_OFF bit must be cleared again respectively Transition to Sleep Mode or Deep Sleep Mode Listing 8 3 and Listing 8 4 provide code for transitioning from the full on...

Page 375: ... PDWN or Deep Sleep Mode bfrom_SysControl SYSCTRL_WRITE SYSCTRL_EXTVOLTAGE SYSCTRL_PLLCTL sleep NULL return Listing 8 4 Transitioning to Sleep Mode or Deep Sleep Mode ASM __sleep link sizeof ADI_SYSCTRL_VALUES 2 SP R7 0 P5 0 SP 12 R0 SYSCTRL_READ SYSCTRL_EXTVOLTAGE SYSCTRL_PLLCTL R1 FP R1 sizeof ADI_SYSCTRL_VALUES R2 0 z IMM32 P4 BFROM_SYSCONTROL call P4 R0 w FP sizeof ADI_SYSCTRL_VALUES offse tof...

Page 376: ...t Wakeup Events and Enter Hibernate State Listing 8 5 and Listing 8 6 provide code for configuring the regulator wakeups PH0 PF8 PF9 and CAN_RX and placing the regulator in the hibernate state in C and Blackfin processor assembly code respectively Listing 8 5 Configuring Regulator Wakeups and Entering Hibernate State C void hibernate void ADI_SYSCTRL_VALUES hibernate hibernate uwVrCtl WAKE_EN0 PH0...

Page 377: ...nterrupts copy IMASK to R6 R0 L WAKE_EN0 PH0 Wake Up Enable WAKE_EN1 PF8 Wake Up Enable WAKE_EN2 PF9 Wake Up Enable CANWE CAN Rx Wake Up Enable HIBERNATE Powerdown w FP sizeof ADI_SYSCTRL_VALUES offsetof ADI_SYSCTRL_VALUES uwVrCtl R0 R0 SYSCTRL_WRITE SYSCTRL_VRCTL SYSCTRL_EXTVOLTAGE R1 FP R1 sizeof ADI_SYSCTRL_VALUES R2 0 z IMM32 P4 BFROM_SYSCONTROL call P4 Hibernate State no code executes until w...

Page 378: ...embly code respectively Listing 8 7 Execute a System Reset or a Soft Reset C void reset void bfrom_SysControl SYSCTRL_SYSRESET NULL NULL either bfrom_SysControl SYSCTRL_SOFTRESET NULL NULL or return Listing 8 8 Execute a System Reset or a Soft Reset ASM __reset link sizeof ADI_SYSCTRL_VALUES 2 SP R7 0 P5 0 SP 12 R0 SYSCTRL_SYSRESET either R0 SYSCTRL_SOFTRESET or R1 0 z R2 0 z IMM32 P4 BFROM_SYSCON...

Page 379: ... 10x to 21x keeping the CSEL divider at 1 and changing the SSEL divider from 5 to 4 in the full on operating mode Listing 8 9 Transition of Frequencies C void frequency void ADI_SYSCTRL_VALUES frequency Set MSEL 5 63 VCO CLKIN MSEL frequency uwPllCtl SET_MSEL 21 Set SSEL 1 15 SCLK VCO SSEL CCLK VCO 1 frequency uwPllDiv SET_SSEL 4 CSEL_DIV1 frequency uwPllLockCnt 0x0200 bfrom_SysControl SYSCTRL_WRI...

Page 380: ...RL_VALUES offsetof ADI_SYSCTRL_VALUES uwPllCtl R0 R0 L SET_SSEL 4 Set SSEL 1 15 SCLK VCO SSEL CSEL_DIV1 CCLK VCO 1 w FP sizeof ADI_SYSCTRL_VALUES offsetof ADI_SYSCTRL_VALUES uwPllDiv R0 R0 L 0x0200 w FP sizeof ADI_SYSCTRL_VALUES offsetof ADI_SYSCTRL_VALUES uwPllLockCnt R0 argument 1 in R0 R0 SYSCTRL_WRITE SYSCTRL_EXTVOLTAGE SYSCTRL_PLLCTL SYSCTRL_PLLDIV argument 2 in R1 structure lays on local sta...

Page 381: ...nging the voltage level dynamically The User must include his own code for accessing the external voltage regulator Listing 8 11 Changing Core Voltage C void voltage void ADI_SYSCTRL_VALUES voltage u32 ulCnt 0 bfrom_SysControl SYSCTRL_EXTVOLTAGE SYSCTRL_PLLCTL SYSCTRL_READ init NULL init uwPllCtl BYPASS init uwPllLockCnt 0x0200 bfrom_SysControl SYSCTRL_WRITE SYSCTRL_PLLCTL SYSCTRL_LOCKCNT SYSCTRL_...

Page 382: ...y the user must ensure timings are kept The compiler no optimization enabled will create a loop that takes about 10 cycles Time base is CLKIN as the PLL is bypassed We need 0x0200 CLKIN cycles that represent PLL_LOCKCNT and addition ally the time required by the circuitry ulCnt 0x0200 0x0200 while ulCnt 0 ulCnt init uwPllCtl BYPASS bfrom_SysControl SYSCTRL_WRITE SYSCTRL_PLLCTL SYSCTRL_EXTVOLTAGE v...

Page 383: ...el consolidated register definitions and programming examples Overview The ADSP BF50x Blackfin processors feature a rich set of peripherals which through a powerful pin multiplexing scheme provides great flexi bility to the external application space Features The peripheral pins are functionally organized into general purpose ports designated port F port G and port H Port F provides 16 pins PPI da...

Page 384: ...onal SPI0 and SPI1 slave selects GPIOs Port G provides 16 pins SPORT1 signals CAN signals ACM signals PPI signals GP Timer signals PWM1 signals CNT1 GP Counter 1 signals SPI1 signals UART0 signals RSI signals GPIOs Port H provides 3 pins SPORT1 signals ACM signals SPI0 and SPI1 slave select signals ...

Page 385: ...TF_FER PORTG_FER and PORTH_FER The competing peripherals on port F port G and port H are controlled by the respective multiplexer control register PORTF_MUX PORTG_MUX PORTH_MUX In this chapter the naming convention for registers and bits uses a lowercase x to represent F G or H For example the name PORTx_FER represents PORTF_FER PORTG_FER and PORTH_FER The bit name Px0 represents PF0 PG0 and PH0 T...

Page 386: ...nction 2nd Function 3rd Function Additional Use GPIO Bit 1 0 TSCLK0 UA0_RX TMR6 RW0_CUD PF0 Bit 3 2 RSCLK0 UA0_TX TMR5 RW0_CGD PF1 Bit 5 4 DT0PRI PWM0_BH PPI_DATA8 RW0_CZM PF2 TFS0 PWM0_BL PPI_DATA9 RW0_CGD PF3 RFS0 PWM0_CH PPI_DATA10 TACLK0 PF4 DR0PRI PWM0_CL PPI_DATA11 TACLK1 PF5 Bit 7 6 UA1_TX PWM0_TRIP PPI_DATA12 PF6 UA1_RX PWM0_SYNC PPI_DATA13 TACI3 PF7 Bit 9 8 UA1_RTS DT0SEC PPI_DATA7 PF8 UA...

Page 387: ...n 2nd Function 3rd Function Additional Use GPIO Bit 1 0 SPI1_SSEL3 TMRCLK PPICLK UA1_RX TACI4 PG0 Bit 3 2 SPI1_SSEL2 PPI_FS3 CAN_RX TACI5 WAKEUP PG1 Bit 5 4 SPI1_SSEL1 TMR4 CAN_TX SPI1_SS PG2 Bit 7 6 SPI1_SCK DT1SEC UA1_TX PG3 HWAIT SPI1_MOSI DR1SEC PWM1_SYNC TACLK6 PG4 SPI1_MISO TMR7 PWM1_TRIP PG5 Bit 9 8 ACM_SE_DIFF SD_DATA3 PWM1_AH PG6 ACM_RANGE SD_DATA2 PWM1_AL PG7 DR1SEC SD_DATA1 PWM1_BH PG8 ...

Page 388: ... Input taps are shown in Table 9 1 Table 9 2 and Table 9 3 under the Additional Use column When input taps as well as GPIO based taps are used with other functionality enabled on the GPIO pins the signals seen by the input tap modules might be different from what is seen on the pins This is because different pin functions have different signal require ments with respect to when the signal is latch...

Page 389: ..._MUX 5 4 b 00 or b 10 TACLK1 if PORTF_FER 5 1 and PORTF_MUX 5 4 b 00 or b 10 TACI3 if PORTF_FER 7 1 and PORTF_MUX 7 6 b 10 CZM0 if PORTF_FER 9 1 and PORTF_MUX 9 8 b 01 or b 10 TACLK2 if PORTF_FER 11 1 and PORTF_MUX 11 10 b 00 or b 10 SPI0_SS if PORTF_FER 13 1 and PORTF_MUX 13 12 b 10 TACI5 if PORTG_FER 1 1 and PORTG_MUX 3 2 b 01 TACLK6 if PORTG_FER 4 1 and PORTG_MUX 7 6 b 00 or b 01 TACI6 if PORTG...

Page 390: ... via the PORTF_MUX register The same principle holds true for the PWM1_TRIP signal on PG5 in the PORTG_MUX register RSI Considerations Pull up pull down enabling for RSI Pull down for SD_DATA 3 will be enabled only if SD_DATA 3 is selected on PG6 that is PORTG_MUX 9 8 b 01 and the PD_Dat3 bit is set in the RSI_CONFIG register Pull up for SD_DATA 3 will be enabled only if SD_DATA 3 is selected on P...

Page 391: ...ected for alternate function operation GP Counter Considerations If SPORT0 TX operation is not enabled RW0 is an input tap on pins PF0 PF2 and PF3 Otherwise RW0 is an input tap on PF0 PF1 and PF9 SPI Considerations If SPI0 or SPI1 is operating in master mode and the PSSE bit in the respec tive SPI_CTL register is set to 1 the SPIx_SSEL1 signal for that SPI interface can not be used as a slave sele...

Page 392: ...cts to the COUNTER0 TO output internally TACI1 connects to the COUNTER1 TO output internally PPI TMR0 is internally looped back to PPI_FS1 to be used as internally gener ated frame sync In this case PPI_CLK is the clock input for the Timer0 module TMR1 is internally looped back to PPI_FS2 to be used as internally gener ated frame sync In this case PPI_CLK is the clock input for the Timer1 module P...

Page 393: ...put enable is active then TMR6 is the clock input for TSCLK0 If SPORT0 s RSCLK0 is configured as an output and PORTF_MUX 3 2 b 00 and TMR5 input enable is active then RSCLK0 is the clock input for TMR5 If SPORT0 s TSCLK0 is configured as an output and PORTF_MUX 1 0 b 00 and TMR6 input enable is active then TSCLK0 is the clock input for TMR6 If TACI7 is selected in the TMR7 module then the signal f...

Page 394: ...the time that program flow is inter rupted When configured for edge sensitive interrupt generation an additional SCLK cycle of latency is introduced giving a total latency of 5 SCLK cycles between the time the edge is asserted and the time that the core program flow is interrupted Description of Operation The operation of the general purpose ports is described in the following sections Operation T...

Page 395: ... be used in GPIO mode General Purpose I O Modules The processor supports 35 bidirectional or general purpose I O GPIO signals These 35 GPIOs are managed by three different GPIO modules which are functionally identical One is associated with port F one with port G and one with port H Port F and port G each consist of 16 GPIOs PF15 0 and PG15 0 respectively Port H consists of three GPIOs PH7 0 Each ...

Page 396: ... the output driver by set ting PORTxIO_DIR bits for the same GPIO A write operation to any of the GPIO data registers sets the value of all GPIOs in this port that are configured as outputs GPIOs configured as inputs ignore the written value A read operation returns the state of the GPIOs defined as outputs and the sense of the inputs based on the polar ity and sensitivity settings if their input ...

Page 397: ...et registers are write 1 to set registers All 1s contained in the value written to a GPIO set register sets the respective bits in the GPIO data register The 0s have no effect For example assume that PF0 is configured as an output Writing 0x0001 to the GPIO set register drives a logic 1 on the PF0 pin without affecting the state of any other PFx pins The GPIO set registers are typi cally also used...

Page 398: ... register changes the pin state from logic 0 to logic 1 or from logic 1 to logic 0 on the PG1 pin without affecting the state of any other PGx pins Read operations from the GPIO toggle registers return the content of the GPIO data registers The state of the GPIOs can be read through any of these data set clear or toggle registers However the returned value reflects the state of the input pin only ...

Page 399: ...of the GPIO polarity registers are cleared at reset defaulting to active high polarity The GPIO interrupt sensitivity registers are used to configure each of the inputs as either a level sensitive or an edge sensitive source When using an edge sensitive mode an edge detection circuit is used to prevent a situ ation where a short event is missed because of the system clock rate The GPIO interrupt s...

Page 400: ...it means enabling the interrupt on this channel Interrupt A and interrupt B operate independently For example writing 1 to a bit in the mask interrupt A register does not affect interrupt channel B This facility allows GPIOs to generate GPIO interrupt A GPIO inter rupt B both GPIO interrupts A and B or neither A GPIO interrupt is generated by a logical OR of all unmasked GPIOs for that interrupt F...

Page 401: ...gure 9 1 GPIO Interrupt Generation Flow for Interrupt Channel A NO INPUT YES YES YES YES GENERATE INTERRUPT A START IS THE GPIO SET AS AN OUTPUT IN PORTxIO_DIR IS THE GPIO EDGE SENSITIVE AS DEFINED IN PORTxIO_EDGE IS THE INPUT AN ACTIVE LEVEL AS DEFINED IN PORTxIO_POLAR IS THE GPIO SET TO ONE YES IS EDGE DETECTED AS DEFINED IN PORTxIO_POLAR PORTxIO_BOTH IS THE INPUT DRIVER ENABLED IN PORTxIO_INEN ...

Page 402: ...ll bits in the register writes to the mask interrupt clear reg ister can be used to clear a single bit or a few bits only No read modify write operations are required The mask interrupt clear registers are write 1 to clear registers All ones contained in the value written to the mask interrupt clear register clear the respective bits in the mask interrupt register The zeroes have no effect Writing...

Page 403: ... GPIOs are assigned to the same interrupt channel it is up to the interrupt service routine to evaluate the GPIO data registers to determine the signaling interrupt source Figure 9 2 GPIO Interrupt Channels IRQ40 PF0 PORTFIO_MASKA_D PF1 PF2 PF3 PF4 PF5 PF6 PF7 PF8 PF9 PF10 PF11 PF12 PF13 PF14 PF15 PORTFIO_MASKB_D PG0 PORTGIO_MASKA_D PG1 PG2 PG3 PG4 PG5 PG6 PG7 PG8 PG9 PG10 PG11 PG12 PG13 PG14 PG15...

Page 404: ... PERIPHERAL WRITE PORTx_FER TO CLEAR APPROPRIATE PFx PGx AND PHx BITS SEE PERIPHERAL FOR MORE DETAILS OUTPUT INPUT GPIO OUTPUT OR INPUT WRITE PORTxIO_DIR TO CLEAR APPROPRIATE BITS FOR INPUT DIRECTION WRITE PORTxIO_INEN TO SET APPROPRIATE BITS TO ENABLE INPUT DRIVERS DIRECTION A WRITE PORTxIO_DIR TO SET APPROPRIATE BITS FOR OUTPUT DIRECTION SET CLEAR SET OR CLEAR GPIO WRITE PORTxIO_CLEAR TO SET APP...

Page 405: ...OGATE PORTx_DATA BITS TO DETERMINE EVENTS RISING OR FALLING BOTH EDGE RISING FALLING OR BOTH WRITE PORTxIO_BOTH TO SET APPROPRIATE BITS FOR BOTH EDGE SENSITIVITY WRITE PORTxIO_BOTH TO CLEAR APPROPRIATE BITS FOR EDGE SENSITIVITY RISING FALLING EDGE RISING OR FALLING WRITE PORTxIO_POLAR TO SET APPROPRIATE BITS FOR FALLING EDGE SENSITIVITY WRITE PORTxIO_POLAR TO CLEAR APPROPRIATE BITS FOR RISING EDGE...

Page 406: ... PORTx_HYSTERESIS Register This register configures Schmitt triggering SE for the PORTx inputs The Schmitt trigger can be set only for pin groups classified by the pin muxing controls For each controlled group of pins b 00 will disable Schmitt triggering while b 01 will enable it Combinations of b 1x are reserved Figure 9 5 Port F Hysteresis Register 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 0 1 0...

Page 407: ...15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 0 1 0 1 0 1 1 0 1 0 1 0 1 0 Reset 0x5555 Port G Hysteresis Register PORTG_HYSTERESIS PG13o12_SE PG8to6_SE PG1_SE PG11to9_SE PG5to3_SE PG2_SE PG0_SE PG15to14_SE 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 0 0 0 0 0 0 0 0 0 0 1 0 1 0 Reset 0x0015 Port H Hysteresis Register PORTH_HYSTERESIS Reserved PH0_SE PH1_SE PH2_SE ...

Page 408: ...AG_SE NMI_RST_BMODE_SE 00 Disable hysteresis for JTAG input signals 01 Enable hysteresis for JTAG input signals 1x Reserved 00 Enable hysteresis for NMI RESET and BMODE signals 01 Disable hysteresis for NMI RESET and BMODE signals 1x Reserved 00 Enable hysteresis for ARDY pin input from Flash 01 Disable hysteresis for ARDY pin input from Flash 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Non GPIO Drive S...

Page 409: ...iptions Port Multiplexer Control Registers PORTx_MUX Figure 9 10 shows the Port F Multiplexer Control register Refer to Table 9 1 on page 9 4 for more information on multiplexed configura tions within Port F Figure 9 10 Port F Multiplexer Control Register 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Port F Multiplexer Control Register PORTF_MUX PF0_MUX Reset 0x0000 PF1_MUX...

Page 410: ...ura tions within Port G Figure 9 11 Port G Multiplexer Control Register 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Port G Multiplexer Control Register PORTG_MUX PG0_MUX Reset 0x0000 PG1_MUX PG2_MUX PG5to3_MUX PG15to14_MUX PG13to12_MUX PG11to9_MUX PG8to6_MUX For all bit fields 00 1st Peripheral function 01 1st alternate peripheral function 10 2nd alternate peripheral func...

Page 411: ... on multiplexed configura tions within Port H Figure 9 12 Port H Multiplexer Control Register 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Port H Multiplexer Control Register PORTH_MUX PH0_MUX Reset 0x0000 PH1_MUX PH2_MUX Reserved For all bit fields 00 1st Peripheral function 01 1st alternate peripheral function 10 2nd alternate peripheral function 11 Reserved ...

Page 412: ... PORTx_FER Px0 Px12 Px13 Px14 Px15 Px1 Px2 Px3 Px4 Px5 For all bits 0 GPIO mode 1 Enable peripheral function Px6 Px7 Px11 Px10 Px9 Px8 Reset 0x0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GPIO Direction Registers PORTxIO_DIR Px0 Direction Px12 Direction Px13 Direction Px14 Direction Px15 Direction Px1 Direction Px2 Direction Px3 Direction Px4 Direction Px5 Direction F...

Page 413: ...x15 Input Enable Px1 Input Enable Px2 Input Enable Px3 Input Enable Px4 Input Enable Px5 Input Enable For all bits 0 Input Buffer Disabled 1 Input Buffer Enabled Px6 Input Enable Px7 Input Enable Px11 Input Enable Px10 Input Enable Px9 Input Enable Px8 Input Enable Reset 0x0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GPIO Data Registers PORTxIO Program Px0 Program Px1...

Page 414: ... Set Registers PORTxIO_SET Set Px0 Set Px12 Set Px13 Set Px14 Set Px15 Set Px1 Set Px2 Set Px3 Set Px4 Set Px5 Write 1 to set Set Px6 Set Px7 Set Px11 Set Px10 Set Px9 Set Px8 Reset 0x0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GPIO Clear Registers PORTxIO_CLEAR Clear Px0 Clear Px12 Clear Px13 Clear Px14 Clear Px15 Clear Px1 Clear Px2 Clear Px3 Clear Px4 Clear Px5 Wr...

Page 415: ...14 Toggle Px15 Toggle Px1 Toggle Px2 Toggle Px3 Toggle Px4 Toggle Px5 Write 1 to toggle Toggle Px6 Toggle Px7 Toggle Px11 Toggle Px10 Toggle Px9 Toggle Px8 Reset 0x0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GPIO Polarity Registers PORTxIO_POLAR Px0 Polarity Px12 Polarity Px13 Polarity Px14 Polarity Px15 Polarity Px1 Polarity Px2 Polarity Px3 Polarity Px4 Polarity Px...

Page 416: ...1 Sensitivity Px2 Sensitivity Px3 Sensitivity Px4 Sensitivity Px5 Sensitivity For all bits 0 Level 1 Edge Px6 Sensitivity Px7 Sensitivity Px11 Sensitivity Px10 Sensitivity Px9 Sensitivity Px8 Sensitivity Reset 0x0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GPIO Set on Both Edges Registers PORTxIO_BOTH Px0 Both Edges Px12 Both Edges Px13 Both Edges Px14 Both Edges Px15...

Page 417: ... A Enable Px5 Interrupt A For all bits 1 Enable 0 Disable Enable Px6 Interrupt A Enable Px7 Interrupt A Enable Px11 Interrupt A Enable Px10 Interrupt A Enable Px9 Interrupt A Enable Px8 Interrupt A Reset 0x0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GPIO Mask Interrupt B Registers PORTxIO_MASKB Enable Px0 Interrupt B Enable Px12 Interrupt B Enable Px13 Interrupt B En...

Page 418: ...rs PORTxIO_MASKA_SET Set Px0 Interrupt A Enable Set Px12 Interrupt A Enable Set Px13 Interrupt A Enable Set Px14 Interrupt A Enable Set Px15 Interrupt A Enable Set Px1 Interrupt A Enable Set Px2 Interrupt A Enable Set Px3 Interrupt A Enable Set Px4 Interrupt A Enable Set Px5 Interrupt A Enable For all bits 1 Set Set Px6 Interrupt A Enable Set Px7 Interrupt A Enable Set Px11 Interrupt A Enable Set ...

Page 419: ...ts 1 Set Reset 0x0000 Set Px0 Interrupt B Enable Set Px1 Interrupt B Enable Set Px2 Interrupt B Enable Set Px3 Interrupt B Enable Set Px4 Interrupt B Enable Set Px5 Interrupt B Enable Set Px6 Interrupt B Enable Set Px7 Interrupt B Enable Set Px9 Interrupt B Enable Set Px8 Interrupt B Enable Set Px12 Interrupt B Enable Set Px13 Interrupt B Enable Set Px14 Interrupt B Enable Set Px15 Interrupt B Ena...

Page 420: ...KA_CLEAR Clear Px0 Interrupt A Enable Clear Px12 Interrupt A Enable Clear Px13 Interrupt A Enable Clear Px14 Interrupt A Enable Clear Px15 Interrupt A Enable Clear Px1 Interrupt A Enable Clear Px2 Interrupt A Enable Clear Px3 Interrupt A Enable Clear Px4 Interrupt A Enable Clear Px5 Interrupt A Enable For all bits 1 Clear Clear Px6 Interrupt A Enable Clear Px7 Interrupt A Enable Clear Px11 Interru...

Page 421: ...et 0x0000 Clear Px0 Interrupt B Enable Clear Px1 Interrupt B Enable Clear Px2 Interrupt B Enable Clear Px3 Interrupt B Enable Clear Px4 Interrupt B Enable Clear Px5 Interrupt B Enable Clear Px6 Interrupt B Enable Clear Px7 Interrupt B Enable Clear Px9 Interrupt B Enable Clear Px8 Interrupt B Enable Clear Px12 Interrupt B Enable Clear Px13 Interrupt B Enable Clear Px14 Interrupt B Enable Clear Px15...

Page 422: ...LE Toggle Px0 Interrupt A Enable Toggle Px12 Interrupt A Enable Toggle Px13 Interrupt A Enable Toggle Px14 Interrupt A Enable Toggle Px15 Interrupt A Enable Toggle Px1 Interrupt A Enable Toggle Px2 Interrupt A Enable Toggle Px3 Interrupt A Enable Toggle Px4 Interrupt A Enable Toggle Px5 Interrupt A Enable For all bits 1 Toggle Toggle Px6 Interrupt A Enable Toggle Px7 Interrupt A Enable Toggle Px11...

Page 423: ... 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GPIO Mask Interrupt B Toggle Registers PORTxIO_MASKB_TOGGLE For all bits 1 Toggle Reset 0x0000 Toggle Px0 Interrupt B Enable Toggle Px1 Interrupt B Enable Toggle Px2 Interrupt B Enable Toggle Px3 Interrupt B Enable Toggle Px4 Interrupt B Enable Toggle Px5 Interrupt B Enable Toggle Px6 Interrupt B Enable Toggle Px7 Interrupt B Enable Toggle Px9 Interrupt B Enable Toggle...

Page 424: ...PORTFIO_DIR r0 h 0x0000 r0 l 0x0FC0 w p0 r0 ssync set port f clear register p0 l lo PORTFIO_CLEAR p0 h hi PORTFIO_CLEAR r0 l 0xFC0 w p0 r0 ssync set port f input enable register to enable input drivers of some GPIOs p0 l lo PORTFIO_INEN p0 h hi PORTFIO_INEN r0 h 0x0000 r0 l 0x003C w p0 r0 ssync set port f polarity register p0 l lo PORTFIO_POLAR p0 h hi PORTFIO_POLAR r0 0x00000 w p0 r0 ssync ...

Page 425: ...rod uct refer to ADSP BF504 ADSP BF504F ADSP BF506F Embedded Processor Data Sheet For GP Timer interrupt vector assignments refer to Table 4 3 on page 4 19 in Chapter 4 System Interrupts To determine how each of the GP Timers is multiplexed with other func tional pins refer to Table 9 1 on page 9 4 through Table 4 3 on page 4 19 in Chapter 9 General Purpose Ports For a list of MMR addresses for ea...

Page 426: ...eration Consistent management of period and pulse width values Interaction with PPI module for video frame sync operation Autobaud detection for UART module Graceful bit pattern termination when stopping Support for center aligned PWM patterns Error detection on implausible pattern values All read and write accesses to 32 bit registers are atomic Every timer has its dedicated interrupt request out...

Page 427: ...urce is the processor s peripheral clock SCLK Assuming the peripheral clock is running at 133 MHz the maximum period for the timer count is 232 1 133 MHz 32 2 seconds Figure 10 1 Internal Timer Structure TIMER0_CONFIG PERIOD MATCH SCLK ENABLE LATCH 32 TMRCLK TACLK0 TMR0 TIMER0_PERIOD WRITE TIMER0_PERIOD READ COMPARATOR TIMER0_COUNTER COMPARATOR TIMER0_WIDTH READ TIMER0_WIDTH WRITE 32 32 32 32 32 I...

Page 428: ...0000 0000 or 0x0000 0001 when the timer is enabled The counter always counts upward Usually it is clocked by SCLK In PWM mode it can be clocked by the alternate clock input TACLK or alternatively the common timer clock input TMRCLK In counter mode the counter is clocked by edges on the TMR input pin The significant edge is programmable After 232 1 clocks the counter overflows This is reported by t...

Page 429: ...nt ing three SCLK cycles after the TIMEN bit is set While the PWM mode is used to generate PWM patterns the capture mode WDTH_CAP is designed to receive PWM signals A PWM pattern is represented by a pulse width and a signal period This is described by the TIMER_WIDTH and TIMER_PERIOD register pair In capture mode these regis ters are read only Hardware always captures both values Regardless of whe...

Page 430: ...ers To poll the TIMIL bit Figure 10 2 Timers Interrupt Structure TIMIL TIMER IRQ PROCESSOR CORE TOVF_ERR RST RST SET SET RESET TOVF_ERR WRITE DATA MMR WRITE TO TIMER_STATUS 1 0 1 0 SYSTEM INTERRUPT CONTROLLER ILLEGAL TIMER_WIDTH COUNT WIDTH COUNT PERIOD ILLEGAL TIMER _PERIOD COUNTER OVERFLOW TRAILING EDGE LEADING EDGE PERIOD_CNT EXT_CLK WDTH_CAP PWM_OUT PWM_OUT TMODE EXT_CLK WDTH_CAP PWM_OUT TMODE...

Page 431: ...S register before the RTI instruction executes This ensures that the interrupt is not reissued Remember that writes to system registers are delayed If only a few instructions separate the TIMIL clear command from the RTI instruction an extra SSYNC instruction may be inserted In EXT_CLK mode reset the TIMIL bit in the TIMER_STATUS register at the very beginning of the inter rupt service routine to ...

Page 432: ... reads 0 if there has been no error since this timer was enabled or if software has per formed a W1C to clear any previous error If a previous error has not been acknowledged by software TOVF_ERR reads 1 Software should read TOVF_ERR to check for an error If TOVF_ERR is set software can then read ERR_TYP for more information Once detected software should write 1 to clear TOVF_ERR to acknowledge th...

Page 433: ... 1 Anything b 11 Set 2 0 b 11 Set 2 TIMER_PERIOD No change No change 2 TIMER_PERIOD b 11 Set Overflow not possible unless there is also another error such as TIMER_PERIOD 0 Anything Anything b 01 Set PWM_OUT PERIOD_CNT 0 Startup Anything 0 b 01 Set This case is not detected at startup but results in an overflow error once the counter counts through its entire range Anything 1 No change No change R...

Page 434: ...10 3 illus trates PWM_OUT mode WDTH_CAP Startup TIMER_PERIOD and TIMER_WIDTH are read only in this mode no error possible Rollover TIMER_PERIOD and TIMER_WIDTH are read only in this mode no error possible Overflow Anything Anything b 01 Set EXT_CLK Startup 0 Anything b 10 Set 1 Anything No change No change Rollover 0 Anything b 10 Set 1 Anything No change No change Overflow not possible unless the...

Page 435: ...RIOD_CNT IRQ_ENA OUT_DIS CLK_SEL EMU_RUN and TOGGLE_HI enable orthogonal functionality They may be set individually or in any combination although some combina tions are not useful such as TOGGLE_HI 1 with OUT_DIS 1 or PERIOD_CNT 0 Figure 10 3 Timer Flow Diagram PWM_OUT Mode TIN_SEL DATA BUS 0 1 PWM_CLK SCLK CLK_SEL EQUAL TIMER_ENABLE EQUAL 1 1 0 0 YES CLOCK RESET ASSERT DEASSERT INTERRUPT PERIOD_...

Page 436: ...hen PERIOD_CNT is set PWM_OUT continuous pulse mode the timer uses both the TIMER_PERIOD and TIMER_WIDTH registers and generates a repeating and possibly modulated waveform It generates an interrupt if enabled at the end of each period and stops only after it is disabled A setting of PERIOD_CNT 0 counts to the end of the width a setting of PERIOD_CNT 1 counts to the end of the period The TIMER_PER...

Page 437: ...pulse the timer interrupt latch bit TIMIL is set and the timer is stopped automatically No writes to the TIMER_DISABLE register are required in this mode If the PULSE_HI bit is set an active high pulse is generated on the TMR pin If PULSE_HI is not set the pulse is active low The pulse width may be programmed to any value from 1 to 232 1 inclusive Figure 10 4 Timer Enable and Automatic Disable Tim...

Page 438: ...ters are programmed with the values required by the PWM signal When the timer is enabled in this mode the TMR pin is pulled to a deas serted state each time the counter equals the value of the pulse width register and the pin is asserted again when the period expires or when the timer gets started To control the assertion sense of the TMR pin the PULSE_HI bit in the cor responding TIMER_CONFIG reg...

Page 439: ...period and pulse width values become active simul taneously Reads from TIMER_PERIOD and TIMER_WIDTH registers return the old values until the period expires The TOVF_ERR status bit signifies an error condition in PWM_OUT mode The TOVF_ERR bit is set if TIMER_PERIOD 0 or TIMER_PERIOD 1 at startup or when the timer counter register rolls over It is also set if the timer pulse width register is great...

Page 440: ...ported To generate the maximum frequency on the TMR output pin set the period value to 2 and the pulse width to 1 This makes the pin toggle each SCLK clock producing a duty cycle of 50 The period may be pro grammed to any value from 2 to 232 1 inclusive The pulse width may be programmed to any value from 1 to period 1 inclusive PULSE_HI Toggle Mode The waveform produced in PWM_OUT mode with PERIOD...

Page 441: ...w pulse is generated in the first third and all odd numbered periods and an active high pulse is generated in the second fourth and all even numbered periods When PULSE_HI is cleared an active high pulse is generated in the first third and all odd numbered periods and an active low pulse is generated in the second fourth and all even numbered periods The deasserted state at the end of one period m...

Page 442: ...tes the TIMER_PERIOD and TIMER_WIDTH registers once per waveform period When TOGGLE_HI 1 software updates the TIMER_PERIOD and TIMER_WIDTH registers twice per waveform Period values are half as large In odd numbered periods write Period Width instead of Width to the TIMER_WIDTH register in order to obtain center aligned pulses Figure 10 7 Three Timers With Same Period Settings TMR0 TMR1 TMR2 TIMER...

Page 443: ...DTH width Then when TOGGLE_HI 1 the pseudo code would be int period width int per1 per2 wid1 wid2 for period generate_period width generate_width Figure 10 8 Two Timers With Non Overlapping Clocks TMR0 TMR1 WAVEFORM PERIOD 1 WAVEFORM PERIOD 2 TIMER ENABLE ACTIVE LOW ACTIVE HIGH ACTIVE HIGH ACTIVE LOW ACTIVE LOW ACTIVE HIGH ACTIVE HIGH ACTIVE LOW TOGGLE_HI 1 PULSE_HI 0 TOGGLE_HI 1 PULSE_HI 1 TIMER ...

Page 444: ...wid1 does not need to equal wid2 The period can be offset to adjust the phase of the pulses produced per1 does not need to equal per2 The TRUN bit in the TIMER_STATUS register is updated only at the end of even numbered periods in TOGGLE_HI mode When TIMER_DISABLE is writ ten to 1 the current pair of counter periods one waveform period completes before the timer is disabled As when TOGGLE_HI 0 err...

Page 445: ...o way to select the falling edges of PWM_CLK In this mode the PULSE_HI bit controls only the polarity of the pulses produced The timer interrupt may occur slightly before the corresponding edge on the TMR pin the interrupt occurs on an SCLK edge the pin transitions on a later PWM_CLK edge It is still safe to program new period and pulse width values as soon as the interrupt occurs After a period e...

Page 446: ...e TIMER_DISABLE to stop the timer At the end of the pulse the timer stops automatically the corresponding bit in TIMER_ENABLE and TIMER_DISABLE is cleared and the corresponding TRUN bit is cleared See Figure 10 4 on page 10 13 To generate multiple pulses write a 1 to TIMER_ENABLE wait for the timer to stop then write another 1 to TIMER_ENABLE In continuous PWM generation mode PWM_OUT PERIOD_CNT 1 ...

Page 447: ...CNT 1 or the end of the cur rent pulse width PERIOD_CNT 0 This feature may be used to regain immediate control of a timer during an error recovery sequence Use this feature carefully because it may corrupt the PWM pattern generated at the TMR pin When a timer is disabled the TIMER_COUNTER register retains its state when a timer is re enabled the timer counter is reinitialized based on the operatin...

Page 448: ...TH_CAP mode In WDTH_CAP mode the TMR pin is an input pin The internally clocked timer is used to determine the period and pulse width of externally applied rectangular waveforms Setting the TMODE field to b 10 in the TIMER_CONFIG register enables this mode Figure 10 10 Timer Flow Diagram WDTH_CAP Mode SCLK TIMER_ENABLE RESET INTERRUPT PERIOD_CNT TMR PIN INTERRUPT LOGIC PULSE_HI TOVF_ERR TMR PIN PU...

Page 449: ...he TMR pin the PULSE_HI bit in the TIMER_CONFIG register is set or cleared If the PULSE_HI bit is cleared the measurement is initiated by a falling edge the content of the counter register is captured to the pulse width buffer on the rising edge and to the period buffer on the next falling edge When the PULSE_HI bit is set the measurement is initiated by a rising edge the counter value is captured...

Page 450: ...ured in the period that just ended If the PERIOD_CNT bit is cleared and a trailing edge occurred see Figure 10 12 then the TIMER_WIDTH register reports the pulse width measured in the pulse that just ended but the TIMER_PERIOD register reports the pulse period mea sured at the end of the previous period If the PERIOD_CNT bit is cleared and the first trailing edge occurred then the first period val...

Page 451: ...T 1 STARTS COUNTING NOTE FOR SIMPLICITY THE SYNCHRONIZATION DELAY BETWEEN TMR PIN EDGES AND BUFFER REGISTER UPDATES IS NOT SHOWN SCLK 1 3 1 2 3 4 6 7 8 TMR PIN PULSE_HI 0 TMR PIN PULSE_HI 1 2 4 5 1 X TIMER_COUNTER 4 TIMER_PERIOD BUFFER 2 3 TIMER_WIDTH BUFFER 4 TIMER_PERIOD 2 8 8 3 TIMER_WIDTH TIMIL TOVF_ERR TIMEN X 0 X 0 X 0 X 0 MEASUREMENT REPORT MEASUREMENT REPORT ...

Page 452: ...N PULSE_HI 0 TMR PIN PULSE_HI 1 2 3 5 6 8 3 4 3 4 7 1 2 1 X TIMER_COUNTER 8 4 TIMER_PERIOD BUFFER 3 TIMER_WIDTH BUFFER TIMER_PERIOD TIMER_WIDTH TIMIL TOVF_ERR TIMEN 2 1 2 0 4 3 8 1 2 X 0 X 0 X 0 X 0 STARTS COUNTING MEASUREMENT REPORT MEASUREMENT REPORT MEASUREMENT REPORT NOTE FOR SIMPLICITY THE SYNCHRONIZATION DELAY BETWEEN TMR PIN EDGES AND BUFFER REGISTER UPDATES IS NOT SHOWN ...

Page 453: ... timer interrupt if enabled is generated if the TIMER_COUNTER register wraps around from 0xFFFF FFFF to 0 in the absence of a leading edge At that point the TOVF_ERR bit in the TIMER_STATUS register and the ERR_TYP bits in the TIMER_CONFIG register are set indicating a count over flow due to a period greater than the counter s range This is called an error report When a timer generates an interrup...

Page 454: ...NTING SCLK 1 TMR PIN PULSE_HI 0 TMR PIN PULSE_HI 1 2 3 1 2 3 4 0 X TIMER_COUNTER 4 TIMER_PERIOD BUFFER 2 TIMER_WIDTH BUFFER TIMER_PERIOD TIMER_WIDTH TIMIL TOVF_ERR TIMEN 4 5 2 ERROR REPORT MEASUREMENT REPORT 0xFFFF FFFC 0xFFFF FFFD 0xFFFF FFFE 0xFFFF FFFF X 0 X 0 X 0 X 0 0 2 0 0 NOTE FOR SIMPLICITY THE SYNCHRONIZATION DELAY BETWEENTMR PIN EDGES AND BUFFER REGISTER UPDATES IS NOT SHOWN ...

Page 455: ... pin PULSE_HI 0 TMR pin PULSE_HI 1 2 1 2 3 4 0 X TIMER_COUNTER 4 X TIMER_PERIOD BUFFER 3 TIMER_WIDTH BUFFER TIMER_PERIOD TIMER_WIDTH TIMIL TOVF_ERR TIMEN 1 2 0 3 0 X 0 X 0 X 0 0 3 0 3 NOTE FOR SIMPLICITY THE SYNCHRONIZATION DELAY BETWEEN TMR PIN EDGES AND BUFFER REGISTER UPDATES IS NOT SHOWN STARTS COUNTING ERROR REPORT MEASUREMENT REPORT 0xFFFF FFFC 0xFFFF FFFD 0xFFFF FFFE 0xFFFF FFFF 3 ...

Page 456: ... Figure 10 13 the period is 0x1 0000 0004 but the pulse width could be either 0x0 0000 0002 or 0x1 0000 0002 The waveform applied to the TMR pin is not required to have a 50 duty cycle but the minimum TMR pin low time is one SCLK period and the min imum TMR pin high time is one SCLK period This implies the maximum TMR pin input frequency is SCLK 2 with a 50 duty cycle Under these conditions the WD...

Page 457: ...s one SCLK period This implies the maximum TMR pin input frequency is SCLK 2 Period may be programmed to any value from 1 to 232 1 inclusive After the timer has been enabled it resets the TIMER_COUNTER register to 0x0 and then waits for the first leading edge on the TMR pin This edge causes the TIMER_COUNTER register to be incremented to the value 0x1 Every subsequent leading edge increments the c...

Page 458: ...m always follow this order when enabling timers 1 Set timer mode 2 Write TIMER_WIDTH and TIMER_PERIOD registers as applicable 3 Enable timer If this order is not followed the plausibility check may fail because of undefined width and period values or writes to TIMER_WIDTH and TIMER_PERIOD may result in an error condition because the registers are read only in some modes The timer may not start as ...

Page 459: ...started timers require minimal interaction with software which is usually performed by an interrupt service routine In PWM_OUT mode soft ware must update the pulse width and or settings as required In WDTH_CAP mode it must store captured values for further processing In any case the service routine should clear the TIMIL bits of the timers it controls Timer Registers The timer peripheral module pr...

Page 460: ... for the TIMER_ENABLE TIMER_DISABLE and TIMER_STATUS registers On a 32 bit read of one of the 16 bit registers the upper word returns all 0s Timer Enable Register TIMER_ENABLE Figure 10 16 shows an example of the TIMER_ENABLE register for a product with eight timers The register allows simultaneous enabling of multiple timers so that they can run synchronously For each timer there is a single W1S ...

Page 461: ...s enabled All unused bits return 0 when read Figure 10 16 Timer Enable Register 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 Reset 0x0000 0 Timer Enable Register TIMER_ENABLE TIMEN0 Timer0 Enable TIMEN1 Timer1 Enable 1 Enable timer Read as 1 when enabled 1 Enable timer Read as 1 when enabled TIMEN2 Timer2 Enable 1 Enable timer Read as 1 when enabled TIMEN3 Timer3 Enable 1 En...

Page 462: ...ly Figure 10 17 Timer Disable Register 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 Reset 0x0000 0 Timer Disable Register TIMER_DISABLE TIMDIS0 Timer0 Disable TIMDIS1 Timer1 Disable 1 Disable timer Read as 1 if this timer is enabled 1 Disable timer Read as 1 if this timer is enabled TIMDIS2 Timer2 Disable 1 Disable timer Read as 1 if this timer is enabled TIMDIS3 Timer3 Disa...

Page 463: ... the end of a period During a TIMER_STATUS register read access all reserved or unused bits return a 0 Figure 10 18 on page 10 40 shows an example of the TIMER_STATUS register for a prod uct with eight timers For detailed behavior and usage of the TRUN bit see Stopping the Timer in PWM_OUT Mode on page 10 22 Writing the TRUN bits has no effect in other modes or when a timer has not been enabled Wr...

Page 464: ... Status TOVF_ERR6 Timer6 Counter Overflow Indicates that an error or an overflow occurred All bits are W1C 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 TIMIL0 Timer0 Interrupt 0 Read as 1 if timer running W1C to abort in PWM_OUT mode Indicates an interrupt request when IRQ_ENA is set TIMIL1 Timer1 Interrupt TRUN2 Timer2 Slave Enable Status TIMIL2 Timer2 Interrupt Indicates tha...

Page 465: ...he TIMER_CONFIG registers may be read at any time The ERR_TYP field is read only It is cleared at reset and when the timer is enabled Each time TOVF_ERR is set ERR_TYP 1 0 is loaded with a code that identi fies the type of error that was detected This value is held until the next error or timer enable occurs For an overview of error conditions see Table 10 1 on page 10 9 The TIMER_CONFIG register ...

Page 466: ...e action pulse 1 Positive action pulse 0 Use system clock SCLK for counter 1 Use PWM_CLK to clock counter 0 The effective state of PULSE_HI is the programmed state 1 The effective state of PULSE_HI alternates each period 00 No error 01 Counter overflow error 10 Period register programming error 11 Pulse width register programming error 00 Reset state unused 01 PWM_OUT mode 10 WDTH_CAP mode 11 EXT_...

Page 467: ...OD and TIMER_WIDTH in WDTH_CAP mode remain active during an emulation stop Some applications may require the timer to continue counting asynchro nously to the emulation halted processor core Set the EMU_RUN bit in TIMER_CONFIG to enable this behavior Timer Period TIMER_PERIOD and Timer Width TIMER_WIDTH Registers When a timer is enabled and running and the software writes new values to the TIMER_P...

Page 468: ...gister the value from the previous period is reused Writes to the 32 bit TIMER_PERIOD register and TIMER_WIDTH register are atomic it is not possible for the high word to be written without the low word also being written Values written to the TIMER_PERIOD registers or TIMER_WIDTH registers are always stored in the buffer registers Reads from the TIMER_PERIOD or TIMER_WIDTH registers always return...

Page 469: ... 10 counts there may not be enough time between updates from the buffer registers to write both the TIMER_PERIOD register and the TIMER_WIDTH register The next period may use one old value and one new value In order to prevent pulse width period errors write the TIMER_WIDTH register before the TIMER_PERIOD register when decreasing the values and write the TIMER_PERIOD register before the TIMER_WID...

Page 470: ... Disable timer 0 No effect TMODE b 01 b 10 b 11 PULSE_HI 1 Generate high width 0 Generate low width 1 Measure high width 0 Measure low width 1 Count rising edges 0 Count falling edges PERIOD_CNT 1 Generate PWM 0 Single width pulse 1 Interrupt after mea suring period 0 Interrupt after mea suring width Unused IRQ_ENA 1 Enable interrupt 0 Disable interrupt 1 Enable interrupt 0 Disable interrupt 1 Ena...

Page 471: ...riod every one coun ter period Unused Unused ERR_TYP Reports b 00 b 01 b 10 or b 11 as appropriate Reports b 00 or b 01 as appropriate Reports b 00 b 01 or b 10 as appropriate EMU_RUN 0 Halt during emulation 1 Count during emulation 0 Halt during emulation 1 Count during emulation 0 Halt during emulation 1 Count during emulation TMR Pin Depends on OUT_DIS 1 Three state 0 Output Depends on TIN_SEL ...

Page 472: ...t at rollover if width Period Set if counter wraps Set if counter wraps Set if counter wraps or set at startup or roll over if period 0 IRQ Depends on IRQ_ENA 1 Set when TOVF_ERR set or when counter equals period and PERIOD_CNT 1 or when counter equals width and PERIOD_CNT 0 0 Not set Depends on IRQ_ENA 1 Set when TOVF_ERR set or when counter captures period and PERIOD_CNT 1 or when counter captur...

Page 473: ...lo PORTG_MUX r7 l PFTE w p5 r7 r7 7 p5 5 sp rts timer_port_setup end Listing 10 2 generates signals on the TMR4 and TMR5 outputs By default timer 5 generates a continuous PWM signal with a duty cycle of 50 period 0x40 SCLKs width 0x20 SCLKs while the PWM signal gen erated by timer 4 has the same period but 25 duty cycle width 0x10 SCLKs If the preprocessor constant SINGLE_PULSE is defined every TM...

Page 474: ...4_CONFIG TIMER_ENABLE r7 r7 0x10 z p5 TIMER5_WIDTH TIMER_ENABLE r7 r7 0x20 z p5 TIMER4_WIDTH TIMER_ENABLE r7 ifndef SINGLE_PULSE r7 0x40 z p5 TIMER5_PERIOD TIMER_ENABLE r7 p5 TIMER4_PERIOD TIMER_ENABLE r7 endif r7 l TIMEN5 TIMEN4 w p5 r7 r7 7 p5 5 sp rts timer45_signal_generation end All subsequent examples use interrupts Thus Listing 10 3 illustrates how interrupts are generated and how interrupt...

Page 475: ...p5 EVT12 IMASK r7 unmask IVG12 in CEC r7 p5 bitset r7 bitpos EVT_IVG12 p5 r7 assign timer 5 IRQ IRQ37 in this example to IVG12 p5 h hi SIC_IAR4 p5 l lo SIC_IAR4 SIC_IAR register mapping is processor dependent r7 h 0xFF5F r7 l 0xFFFF p5 r7 enable timer 5 IRQ p5 h hi SIC_IMASK1 p5 l lo SIC_IMASK1 SIC_IMASK register mapping is processor dependent r7 p5 bitset r7 5 p5 r7 enable interrupt nesting r7 7 ...

Page 476: ...xample is just the clearing of the interrupt request and counting interrupt occurrences Listing 10 4 Periodic Interrupt Requests define SINGLE_PULSE timer5_interrupt_generation sp r7 7 p5 5 p5 h hi TIMER_ENABLE p5 l lo TIMER_ENABLE ifdef SINGLE_PULSE r7 l EMU_RUN IRQ_ENA OUT_DIS PWM_OUT else r7 l EMU_RUN IRQ_ENA PERIOD_CNT OUT_DIS PWM_OUT endif w p5 TIMER5_CONFIG TIMER_ENABLE r7 r7 0x1000 z ifndef...

Page 477: ...PULSE_HI 1 Figure 10 23 explains how the signal waveform represented by the period P and the pulse width W translates to timer period and width values Table 10 3 summarizes the register writes Since hardware only updates the written period and width values at the end of periods software can write new values immediately after the timers have been enabled Note that both timers period expires at exac...

Page 478: ...pulse width define N 4 number of pulses before disable timer45_toggle_hi sp r7 1 p5 5 p5 h hi TIMER_ENABLE p5 l lo TIMER_ENABLE config timers r7 l IRQ_ENA PERIOD_CNT TOGGLE_HI PULSE_HI PWM_OUT w p5 TIMER5_CONFIG TIMER_ENABLE r7 r7 l PERIOD_CNT TOGGLE_HI PULSE_HI PWM_OUT w p5 TIMER4_CONFIG TIMER_ENABLE r7 calculate timers widths and period r0 l lo P Figure 10 23 Non Overlapping Clock Pulses TMR5 EN...

Page 479: ...5 TIMER5_WIDTH TIMER_ENABLE r4 start timers r7 l TIMEN5 TIMEN4 w p5 TIMER_ENABLE TIMER_ENABLE r7 write values for second period p5 TIMER4_PERIOD TIMER_ENABLE r3 p5 TIMER5_WIDTH TIMER_ENABLE r2 r0 functions as signal period counter r0 h hi N 2 1 r0 l lo N 2 1 r7 1 p5 5 sp rts timer45_toggle_hi end isr_timer5 sp astat sp r7 5 p5 5 p5 h hi TIMER_ENABLE p5 l lo TIMER_ENABLE clear interrupt request r7 ...

Page 480: ... w p5 TIMER_DISABLE TIMER_ENABLE r7 r7 5 p5 5 sp astat sp rti isr_timer5 end Listing 10 5 generates N pulses on both timer output pins Disabling the timers does not corrupt the generated pulse pattern anyhow Listing 10 6 configures timer 5 in WDTH_CAP mode If looped back exter nally this code might be used to receive N PWM patterns generated by one of the other timers Ensure that the PWM generator...

Page 481: ... p5 h hi TIMER_ENABLE p5 l lo TIMER_ENABLE r7 l EMU_RUN IRQ_ENA PERIOD_CNT PULSE_HI WDTH_CAP w p5 TIMER5_CONFIG TIMER_ENABLE r7 r7 l TIMEN5 w p5 TIMER_ENABLE TIMER_ ENABLE r7 r7 7 p5 5 sp rts timer5_capture end isr_timer5 sp astat sp r7 7 p5 5 clear interrupt request first p5 h hi TIMER_STATUS p5 l lo TIMER_STATUS r7 h hi TIMIL5 r7 l lo TIMIL5 p5 r7 r7 p5 TIMER5_PERIOD TIMER_STATUS i2 r7 r7 p5 TIM...

Page 482: ...eously for synchronous operation Interface Overview Figure 10 24 shows the ADSP BF50x specific block diagram of the gen eral purpose timer module External Interface The TMRCLK input is common to all eight timers The PPI unit is clocked by the same pin therefore any of the timers can be clocked by PPI_CLK Since timer 0 and timer 1 are often used in conjunction with the PPI they are internally loope...

Page 483: ...registers must be set Figure 10 24 Timer Block Diagram TIMER 7 SIC CONTROLLER PAB TIMER 6 TIMER 5 TIMER 4 TIMER 3 TIMER 2 TIMER 1 TIMER 0 TIMER_DISABLE TIMER_ENABLE TIMER_STATUS IRQ 39 IRQ 38 IRQ 37 IRQ 36 IRQ 35 IRQ 34 IRQ 33 IRQ 32 PG5 PG11 PG4 PF13 PF7 UART1 RX PF1 CNT1 TO Output PF10 PG12 UART0 RX PG2 PG0 UART1 RX PG15 PF0 PH1 PF11 PG14 CNT0 TO Output PF5 PF4 TMR7 TACLK7 TACLK6 TMR6 TACI6 TACI...

Page 484: ...Unique Information for the ADSP BF50x Processor 10 60 ADSP BF50x Blackfin Processor Hardware Reference ...

Page 485: ...edded Processor Data Sheet For Core Timer interrupt vector assignments refer to Table 4 3 on page 4 19 in Chapter 4 System Interrupts For a list of MMR addresses for each Core Timer refer to Chapter A System MMR Assignments Core timer behavior for the ADSP BF50x that differs from the general information in this chapter can be found at the end of this chapter in the section Unique Information for t...

Page 486: ...dicated high priority interrupt channel Single shot or continuous operation Timer Overview Figure 11 1 provides a block diagram of the core timer External Interfaces The core timer does not directly interact with any pins of the chip Figure 11 1 Core Timer Block Diagram DEC TSCALE CCLK TIMER ENABLE AND PRESCALE LOGIC ZERO TCOUNT TCNTL TPERIOD COUNT REGISTER LOAD LOGIC TIMER INTERRUPT TINT TMREN CO...

Page 487: ... CCLK clock cycles When the value of the TCOUNT register reaches 0 an interrupt is generated and the TINT bit is set in the TCNTL register If the TAUTORLD bit in the TCNTL register is set then the TCOUNT register is reloaded with the contents of the TPERIOD register and the count begins again If the TAUTORLD bit is not set the timer stops operation The core timer can be put into low power mode by ...

Page 488: ... this is not a W1C bit Write a 0 to clear it However the write is optional It is not required to clear interrupt requests The core time module doesn t provide any further interrupt enable bit When the timer is enabled interrupts can be masked in the CEC controller Core Timer Registers The core timer includes four core memory mapped registers the timer control register TCNTL the timer count registe...

Page 489: ...than following periods To do this write to TPERIOD first and overwrite TCOUNT afterward Figure 11 2 Core Timer Control Register 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 X X X X X X X X X X X X 0 0 0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 X X X X X X X X X X X X X X X X TMPWR Core Timer Control Register TCNTL Reset Undefined TMREN 0 Puts the timer in low power mode 1 Active state Timer can ...

Page 490: ...n the timer is running Figure 11 3 Core Timer Count Register Figure 11 4 Core Timer Period Register Core Timer Count Register TCOUNT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 X X X X X X X X X X X X X X X X 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 X X X X X X X X X X X X X X X X Reset Undefined Count Value 31 16 Count Value 15 0 Core Timer Period Register TPERIOD 15 14 13 12 11 10 9 8 7 6 5 4 3...

Page 491: ...mples Listing 11 1 configures the core timer in auto reload mode Assuming a CCLK of 500 MHz the resulting period is 1 second The initial period is twice as long as the others Listing 11 1 Core Timer Configuration include defBF527 h ADSP BF527 product is used as an example section L1_code global _main _main Register service routine at EVT6 and unmask interrupt p1 l lo IMASK p1 h hi IMASK Figure 11 ...

Page 492: ...000 000 First Period 20 000 000 p1 l lo TCNTL p1 h hi TCNTL r0 50 z p1 TSCALE TCNTL r0 r0 l lo 10000000 r0 h hi 10000000 p1 TPERIOD TCNTL r0 r0 1 p1 TCOUNT TCNTL r0 R6 counts interrupts r6 0 z start in auto reload mode r0 TAUTORLD TMPWR TMREN z p1 r0 _main forever jump _main forever _main end interrupt service routine simple increments R6 isr_core_timer sp astat r6 1 astat sp rti isr_core_timer en...

Page 493: ...ADSP BF50x Blackfin Processor Hardware Reference 11 9 Core Timer Unique Information for the ADSP BF50x Processor None ...

Page 494: ...Unique Information for the ADSP BF50x Processor 11 10 ADSP BF50x Blackfin Processor Hardware Reference ...

Page 495: ...t vector assignments refer to Table 4 3 on page 4 19 in Chapter 4 System Interrupts For a list of MMR addresses for each Watchdog Timer refer to Chapter A System MMR Assignments Watchdog timer behavior for the ADSP BF50x that differs from the gen eral information in this chapter can be found at the end of this chapter in the section Unique Information for the ADSP BF50x Processor on page 12 11 Ove...

Page 496: ...error handler may recover the sys tem For safety however it is often better to reset and reboot the system directly by hardware control Especially in slave boot configurations a processor reset cannot automati cally force the Blackfin device to be rebooted In this case the processor may reset without booting again and may negotiate with the host device by the time program execution starts Alternat...

Page 497: ...ernal Interface The watchdog timer is clocked by the system clock SCLK Its registers are accessed through the 16 bit peripheral access bus PAB The 32 bit regis ters WDOG_CNT and WDOG_STAT must always be accessed by 32 bit read write operations Hardware ensures that those accesses are atomic Figure 12 1 Watchdog Timer Block Diagram EVENT CONTROL WRITE SCLK WDOG_CNT 32 PAB READ RELOAD RESET WDOG_STA...

Page 498: ...e WDOG_STAT register cannot however be written directly Rather software writes the watchdog period value into the 32 bit WDOG_CNT register before the watchdog is enabled Once the watchdog is started the period value cannot be altered To start the watchdog timer 1 Set the count value for the watchdog timer by writing the count value into the watchdog count register WDOG_CNT Since the watchdog timer...

Page 499: ...e watchdog by performing dummy writes to the WDOG_STAT register The values written are ignored but the write commands cause the WDOG_STAT register to be reloaded from the WDOG_CNT register If the watchdog is enabled with a zero value loaded to the counter and the WDRO bit was cleared the WDRO bit of the watchdog control register is set immediately and the counter remains at zero without further de...

Page 500: ...e current count value Values cannot be stored directly in WDOG_STAT but are instead copied from WDOG_CNT This can happen in two ways While the watchdog timer is disabled writing the WDOG_CNT register pre loads the WDOG_STAT register While the watchdog timer is enabled but not rolled over yet writes to the WDOG_STAT register load it with the value in WDOG_CNT Enabling the watchdog timer does not au...

Page 501: ...chdog events is disabled the watch dog timer operates as described except that no event is generated when the watchdog timer expires The watchdog enable WDEN 7 0 bit field is used to enable and disable the watchdog timer Writing any value other than the disable key 0xAD into this field enables the watchdog timer This multibit disable key mini mizes the chance of inadvertently disabling the watchdo...

Page 502: ...BOOT bit to prevent the memory from being rebooted Listing 12 1 Watchdog Timer Configuration include defBF527 h ADSP BF527 product is used as an example define WDOGPERIOD 0x00200000 section L1_code global _reset _reset optionally test whether reset was caused by watchdog Figure 12 4 Watchdog Control Register 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 1 0 1 0 1 1 0 1 0 0 0 Watchdog Control Reg...

Page 503: ...onally set NOBOOT bit to avoid reboot in case p0 h hi SYSCR p0 l lo SYSCR r0 w p0 z bitset r0 bitpos NOBOOT w p0 r0 start watchdog timer reset if expires p0 h hi WDOG_CNT p0 l lo WDOG_CNT r0 h hi WDOGPERIOD r0 l lo WDOGPERIOD p0 r0 p0 l lo WDOG_CTL r0 l WDEN WDEV_RESET w p0 r0 jump _main _reset end The subroutine shown in Listing 12 2 can be called by software to service the watchdog Note that the...

Page 504: ...ng 12 3 is an interrupt service routine that restarts the watchdog Note that the watchdog must be disabled first Listing 12 3 Watchdog Restarted by Interrupt Service Routine isr_watchdog sp astat sp p5 5 r7 7 p5 h hi WDOG_CTL p5 l lo WDOG_CTL r7 l WDDIS w p5 r7 bitset r7 bitpos WDRO w p5 r7 r7 p5 WDOG_CNT WDOG_CTL p5 WDOG_CNT WDOG_CTL r7 r7 l WDEN WDEV_GPI w p5 r7 p5 5 r7 7 sp astat sp rti isr_wat...

Page 505: ...ADSP BF50x Blackfin Processor Hardware Reference 12 11 Watchdog Timer Unique Information for the ADSP BF50x Processor None ...

Page 506: ...Unique Information for the ADSP BF50x Processor 12 12 ADSP BF50x Blackfin Processor Hardware Reference ...

Page 507: ... model consolidated register definitions and programming examples Specific Information for the ADSP BF50x For details regarding the number of GP counters for the ADSP BF50x product refer to ADSP BF504 ADSP BF504F ADSP BF506F Embedded Processor Data Sheet For GP counter interrupt vector assignments refer to Table 4 3 on page 4 19 in Chapter 4 System Interrupts To determine how each of the GP counte...

Page 508: ...on some devices also feature a zero position input zero marker that can be used to establish a reference point to verify that the acquired position does not drift over time In addition the incremental position information can be used to deter mine speed if the time intervals are measured The GP counter provides flexible ways to establish position information When used in conjunction with the GP ti...

Page 509: ...nd gate CDG pin that accept various forms of incremental inputs and are processed by the 32 bit counter The third input count zero marker CZM is the zero marker input The module interfaces to the processor by way of the peripheral access bus PAB and can optionally generate an interrupt request through the IRQ line There is also an output that can be used by the timer module to generate time stamps...

Page 510: ...n page 13 7 for more details The GP counter also features a flexible boundary comparison In all of the operating modes the counter can be compared to an upper and lower limit A variety of actions can be taken when these limits are reached Refer to Boundary Comparison Modes on page 13 10 for more details Quadrature Encoder Mode In this mode the CUD CDG inputs expect a quadrature encoded signal that...

Page 511: ...connected hardware Binary Encoder Mode This mode is almost identical to the previous mode with the exception that the CUD CDG inputs expect a binary encoded signal The order of tran sitions of the CUD and CDG inputs determines whether the counter increments or decrements The CNT_COUNTER register contains the number of transitions that have occurred Refer to Table 13 2 Optionally an interrupt is ge...

Page 512: ... at the CDG input the counter decrements The active edge can be selected by the CDGINV bit in the CNT_CONFIG register If this bit is cleared a rising edge will decrement the counter If this bit is set a falling edge will decrement the counter If simultaneous edges occur on pin CDG and pin CUD the counter remains unchanged and both up count and down count events are signaled in the CNT_STATUS regis...

Page 513: ...UD input will increment the counter a low input will decrement it If this bit is set the polarity is inverted The CDG pin can be used to gate the clock The polarity can be selected by the CDGINV bit in the CNT_CONFIG register If this bit is cleared a high CDG input will enable the counter a low input will stop it If this bit is set the polarity is inverted Functional Description The following sect...

Page 514: ...er programs the desired number of cycles and therefore the debouncing time The number of SCLK cycles for each pin can be selected in 18 steps ranging from 1 128 SCLK periods to 131072 128 SCLK periods see Figure 13 9 on page 13 24 The time tfilter is determined given SCLK and the DPRESCALE value con tained in the CNT_DEBOUNCE register by the following formula where DPRESCALE can contain values fro...

Page 515: ...MZC bit in the CNT_CONFIG register An active level at the CZM input clears the CNT_COUNTER register and holds it until the CZM pin is deactivated In addition if enabled by the CZMZIE bit in the CNT_IMASK register it will set the CZMZII bit in the CNT_STATUS reg ister If enabled by the peripheral interrupt controller this will generate an interrupt request The active level is selected by the CZMINV...

Page 516: ...e CZMINV bit in the CNT_CONFIG register rising edge if cleared falling edge if set to one Boundary Comparison Modes The GP counter includes two boundary registers CNT_MIN lower and CNT_MAX upper The counter value is compared to the lower and upper boundary Depending on which mode is selected different actions are taken if the count value reaches either of the boundary values There are four boundar...

Page 517: ...set both boundary regis ters to the initial CNT_COUNTER value The MAXCII and MINCII status bits are still set when the counter value matches the boundary register Boundary capture mode In this mode the CNT_COUNTER value is latched into the CNT_MIN register at one detected edge of the CZM input pin and latched into CNT_MAX at the opposite edge If the CZMINV bit in the CNT_CONFIG register is cleared...

Page 518: ...Down Count Events The UCII bit in the CNT_STATUS register indicates whether the counter has been incremented Similarly the DCII bit reports decrements The two events are independent For instance if the counter first increments by one and then decrements by two both bits remain set even though the resulting counter value shows a decrement by one In up down counter mode hardware may detect simultane...

Page 519: ...bit CNT_COUNT register has either incre mented from 0x7FFF FFFF to 0x8000 0000 or decremented from 0x8000 0000 to 0x7FFF FFFF If enabled by the COV31IE bit an interrupt request is generated Similarly in applications where only the lower 16 bits of the counter are of interest the COV15II status bit reports counter transitions from 0xXXXX 7FFF to 0xXXXX 8000 or from 0xXXXX 8000 to 0xXXXX 7FFF If ena...

Page 520: ...advanced since the last counter event For this purpose the GP counter has an internal signal that connects to the alternate capture input TACIx of one of the GP timers It is func tional in all modes with the exception of the timed direction mode Refer to Internal Interfaces in Chapter 9 General Purpose Ports for infor mation regarding which GP timer s are associated with which GP counter module s ...

Page 521: ...tain the time between the read of CNT_COUNTER and the next event This mode can also be used with PULSE_HI 0 In this case the period of TO is measured between falling edges It will result in the same values as in the previous case only the latching occurs one SCLK cycle later Capturing Counter Interval and CNT_COUNTER Read Timing It is possible to also capture the time elapsed since the last count ...

Page 522: ...unt event and the read of the CNT_COUNTER register both measured in number of SCLK cycles The result is that when reading the CNT_COUNTER register the two time measurements are also latched and the user has a coherent triplet of infor mation to calculate speed and position Figure 13 3 Operation With GP Timer Module SCLK CUD CDG TO CNT_COUNTER TIMER_COUNTER TIMER_PERIOD BUFFER TIMER_WIDTH BUFFER TI...

Page 523: ...NT_COUNTER is incremented decremented every SCLK cycle timed direction mode the TO signal is incorrect Figure 13 4 Capturing Counter Interval SCLK CUD CDG TO CNT_COUNTER CNT_COUNTER READ TIMER_COUNTER TIMER_PERIOD BUFFER TIMER_WIDTH BUFFER TIMER_PERIOD TIMER_PERIOD TIMER_WIDTH Measurement report of interest due to read of CNT_COUNTER 1 2 3 4 5 6 12 3 3 8 1 4 2 2 11 x 2 3 3 8 1 4 2 2 11 12 1 2 1 2 ...

Page 524: ...DTH_CAP mode with the settings described in the Capturing Timing Information on page 13 14 Then enable the interrupts and the periph eral itself Registers The GP counter interface has eight memory mapped registers MMRs that regulate its operation Descriptions and bit diagrams for MMRs is provided in the sections that follow Counter Module Register Overview Refer to Table 13 3 for an overview of al...

Page 525: ... 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 0 CNTE Counter Enable 0 Disabled 1 Enabled 0 Disabled 1 Enabled CDGINV CDG Pin Polarity Invert 0 Active high rising edge 1 Active low falling edge CUDINV CUD Pin Polarity Invert 0 Active high rising edge 1 Active low falling edge CNTMODE Counter Operating Mode 000 QUAD_ENC quadrature encoder mode 001 BIN_ENC binary encoder mode 010 UD_CNT up down counter mode 011 ...

Page 526: ...ware writes a 1 to the bit write 1 to clear or the GP counter is disabled For explanations of the register bits refer to Control and Signaling Events on page 13 11 Figure 13 6 Counter Interrupt Mask Register Counter Interrupt Mask CNT_IMASK Register Reset 0x0000 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 0 ICIE Illegal Gray binary code inter rupt enable UCIE Upcount interr...

Page 527: ... can be initialized to zero by writing a one to the W1LCNT_ZERO W1LMIN_ZERO and W1LMAX_ZERO fields In addition to clearing registers CNT_COMMAND allows the boundary registers to be modified in a number of ways The current counter value in CNT_COUNT can be captured and loaded into either of the two boundary Figure 13 7 Counter Status Register Counter Status CNT_STATUS Register Reset 0x0000 14 13 12...

Page 528: ... simultaneously by set ting multiple bits in the CNT_COMMAND register However there are restrictions The bits associated with each command have been grouped together such that all bits that involve a write to the CNT_COUNTER register are located within bits 3 0 of the CNT_COMMAND register All commands that involve a write to the CNT_MIN register are located within bits 7 4 of the CNT_COMMAND regis...

Page 529: ...0 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 0 W1LCNT_ZERO Write one to zero CNT_COUNTER W1A W1LCNT_MIN Write 1 to load CNT_COUNTER from CNT_MIN W1A W1LCNT_MAX Write one to load CNT_COUNTER from CNT_MAX W1A W1LMIN_ZERO Write one to zero CNT_MIN Register W1A W1LMIN_CNT Write one to capture CNT_COUNTER to CNT_MIN Register W1A W1LMIN_MAX Write one to copy former CNT_MAX to new CNT_MIN W1A W...

Page 530: ...Debounce Register 0 0 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 0 Counter Debounce CNT_DEBOUNCE Register Reset 0x0000 DPRESCALE DEBOUNCE DELAY 00000 1 x 128 SCLK cycles 00001 2 x 128 SCLK cycles 00010 4 x 128 SCLK cycles 00011 8 x 128 SCLK cycles 00100 16 x 128 SCLK cycles 00101 32 x 128 SCLK cycles 00110 64 x 128 SCLK cycles 00111 128 x 128 SCLK cycles 01000 256 x 128 SCLK c...

Page 531: ...eads and write are atomic by providing respective shadow registers This register can be accessed with either 32 bit or 16 bit operations This allows for using the GP counter as a 16 bit counter if sufficient for the application Figure 13 10 Counter Count Value Register Counter Count Value CNT_COUNTER Register Count Value Reset 0x0000 0000 31 30 29 28 27 26 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19...

Page 532: ... 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 0 CNT_MAX Counter Max 31 30 29 28 27 26 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 0 CNT_MAX Counter Max Counter Minimal Count CNT_MIN Register Reset 0x0000 0000 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 0 31 30 29 28 27 26 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 0 CNT_MIN 31 16 Counter...

Page 533: ...tup Counter Interrupts P5 H hi CNT_IMASK P5 L lo CNT_IMASK R5 nCZMZIE Counter zeroed by zero marker interrupt CZMEIE Zero marker error interrupt CZMIE CZM pin interrupt push button CZEROIE Counts to zero interrupt nCOV15IE Counter bit 15 overflow interrupt nCOV31IE Counter bit 31 overflow interrupt MAXCIE Max count interrupt MINCIE Min count interrupt DCIE Downcount interrupt UCIE Upcount interrup...

Page 534: ... Identifier UCII Up count Interrupt Identifier DCII Down count Interrupt Identifier MINCII Min Count Interrupt Identifier MAXCII Max Count Interrupt Identifier COV31II Bit 31 Overflow Interrupt Identifier COV15II Bit 15 Overflow Interrupt Identifier CZEROII Count to Zero Interrupt Identifier CZMII CZM Pin Interrupt Identifier CZMEII CZM Error Interrupt Identifier CZMZII CZM Zeroes Counter Interrup...

Page 535: ...IC_IAR3 R6 H hi 0xFFFF4FFF R6 L lo 0xFFFF4FFF R7 H hi 0x00000000 R7 L lo 0x00000000 R5 P5 R5 R5 R6 zero the counter interrupt field R5 R5 R7 set Counter interrupt to required priority P5 R5 Set up the interrupt vector for the counter R5 H hi _IVG11_handler R5 L lo _IVG11_handler P5 H hi EVT11 P5 L lo EVT11 P5 R5 Unmask IVG11 interrupt in the IMASK register P5 H hi IMASK P5 L lo IMASK R5 P5 bitset ...

Page 536: ...ng the GP counter interrupts On entry to the handler the SIC_ISR0 register is interrogated to determine if the counter is waiting for an interrupt to be serviced If so the handler responsible for processing all counter interrupts is called Listing 13 3 Sample Interrupt Handler for GP Counter Interrupts _IVG11_handler Stack management SP RETS SP ASTAT SP R7 0 P5 0 Was it a counter interrupt P5 H hi...

Page 537: ...counter Stack management SP RETS SP R7 0 P5 0 Determine what counter interrupts we wish to service R5 w P5 z P5 H hi CNT_IMASK P5 L lo CNT_IMASK R5 w P5 z P5 H hi CNT_STATUS P5 L lo CNT_STATUS R6 w P5 z R5 R5 R6 Interrupt handlers for all GP counter interrupts _IVG11_handler counter illegal_code CC bittst R5 bitpos ICII IF CC JUMP _IVG11_handler counter up_count Clear the serviced request R6 ICII ...

Page 538: ...ear the serviced request R6 UCII z w P5 R6 insert up count handler here _IVG11_handler counter up_count end _IVG11_handler counter down_count CC bittst R5 bitpos DCII IF CC JUMP _IVG11_handler counter min_count Clear the serviced request R6 DCII z w P5 R6 insert down count handler here _IVG11_handler counter down_count end _IVG11_handler counter min_count CC bittst R5 bitpos MINCII IF CC JUMP _IVG...

Page 539: ...1_handler counter b31_overflow Clear the serviced request R6 MAXCII z w P5 R6 insert max count handler here _IVG11_handler counter max_count end _IVG11_handler counter b31_overflow CC bittst R5 bitpos COV31II IF CC JUMP _IVG11_handler counter b15_overflow Clear the serviced request R6 COV31II z w P5 R6 insert bit 31 overflow handler here _IVG11_handler counter b31_overflow end _IVG11_handler count...

Page 540: ...overflow end _IVG11_handler counter count_to_zero CC bittst R5 bitpos CZEROII IF CC JUMP _IVG11_handler counter czm Clear the serviced request R6 CZEROII z w P5 R6 insert count to zero handler here _IVG11_handler counter count_to_zero end _IVG11_handler counter czm CC bittst R5 bitpos CZMII IF CC JUMP _IVG11_handler counter czm_error Clear the serviced request R6 CZMII z w P5 R6 insert czm handler...

Page 541: ...ror end _IVG11_handler counter czm_zeroes_counter CC bittst R5 bitpos CZMZII IF CC JUMP _IVG11_handler counter all_serviced Clear the serviced request R6 CZMZII z w P5 R6 insert czm zeroes counter handler here _IVG11_handler counter czm_zeroes_counter end _IVG11_handler counter all_serviced Restore from stack R7 0 P5 0 SP RETS SP RTS _IVG11_handler counter end Listing 13 4 shows how to set up time...

Page 542: ...rovided in Listing 13 3 on page 13 30 Listing 13 4 Setting Up Timer 7 for Counter Event Period Capture configure the timer for WDTH_CAP mode P5 H hi TIMER7_CONFIG P5 l lo TIMER7_CONFIG R5 PULSE_HI PERIOD_CNT TIN_SEL WDTH_CAP z w P5 R5 l Enable Timer 7 P5 H hi TIMER_ENABLE0 P5 L lo TIMER_ENABLE0 R5 TIMEN7 z w P5 R5 L _IVG11_handler counter up_count CC bittst R5 bitpos UCII IF CC JUMP _IVG11_handler...

Page 543: ...ocessor Hardware Reference 13 37 General Purpose Counter P5 L lo TIMER7_PERIOD R5 P5 P5 H hi _event_period P5 L lo _event_period P5 R5 _IVG11_handler counter up_count end Unique Information for the ADSP BF50x Processor None ...

Page 544: ...Unique Information for the ADSP BF50x Processor 13 38 ADSP BF50x Blackfin Processor Hardware Reference ...

Page 545: ...SP BF504 ADSP BF504F ADSP BF506F Embedded Processor Data Sheet For PWM Controller interrupt vector assignments refer to Table 4 3 on page 4 19 in Chapter 4 System Interrupts To determine how the PWM Controller is multiplexed with other func tional pins refer to Table 9 1 on page 9 4 through Table 9 3 on page 9 6 in Chapter 9 General Purpose Ports For a list of MMR addresses for the PWM Controller ...

Page 546: ...WM_BL PWM_CH and PWM_CL Three Phase PWM Timing Unit As the core of the PWM Controller this block generates three pairs of complemented center based PWM signals and PWM_SYNC coordination Dead Time Control Unit This block inserts emergency dead time after the ideal PWM output pair including crossover is generated Output Control Unit This block permits the redirection of the outputs of the Three Phas...

Page 547: ...PWM synchronization pulse and also controls whether an external PWM_SYNC pulse is used Figure 14 1 PWM Controller Block Diagram PWM CONFIGURATION REGISTERS PWM DUTY CYCLE REGISTERS PWM_STAT2 PWM_CTRL PWM_TM PWM_CHA PWM_CHB PWM_CHC PWM_DT PWM_SEG 8 6 PWM_SEG 5 0 PWM_GATE THREE PHASE PWM TIMING UNIT DEAD TIME CONTROL UNIT OUTPUT CONTROL UNIT GATE DRIVE UNIT PWM SYNC PULSE CONTROL UNIT PWM SHUTDOWN A...

Page 548: ... of the two sig nals of a PWM pair for easy control of ECMs or BDCMs In crossover mode the PWM signal destined for the high side switch is diverted to the complementary low side output and the signal destined for the low side switch is diverted to the corresponding high side output signal for ECM or BDCM modes of operation A typical configuration for these types of motors is shown in Figure 14 2 I...

Page 549: ...TE register directly controls the chopping frequency In addition high frequency chopping can be independently enabled for the high and low side outputs using separate control bits in the PWM_GATE register In addition all PWM outputs require sufficient sink and source capability to directly drive most opto isolators Figure 14 2 Active Low PWM Signals for ECM Control PWMCHA PWMCHB PWMCHA PWMCHB 2 PW...

Page 550: ...d 0 selects single update mode The PWM generator can provide an internal synchronization pulse on the PWM_SYNC pin that is synchronized to the PWM switching frequency In single update mode a PWM_SYNC pulse is produced at the start of each PWM period In double update mode an additional PWM_SYNC pulse is also produced at the midpoint of each PWM period The width of the PWM_SYNC pulse is programmable...

Page 551: ...circuitry does not go through any clocked logic thereby ensuring correct PWM shutdown even in the event of a loss of the processor system clock A trip shutdown in hardware resets the PWM_EN bit in the PWM_CTRL register but all the other pro grammable registers maintain their current state Software The PWM system may be shut down in software by disabling the PWM_ENABLE bit in the PWM_CTRL register ...

Page 552: ...cally execute an interrupt service routine ISR to update the three PWM channel duties according to a control algorithm based on expected motor operation and sampled data of the existing motor operation PWM_SYNC can also trigger the ADC to sample data for use during the ISR During processor boot the PWM Controller is initialized and program flow enters a wait loop When a PWM_SYNCINT interrupt occur...

Page 553: ... requiring output crossover During an external trip event if not disabled the PWM outputs will be turned off that is set to the opposite of the on polarity configured by the PWM_POLARITY bit of the PWM_CTRL register and the PWM sync pulse will continue to operate if already enabled A PWM_TRIPINT interrupt will occur if unmasked notifying the software of this event To handle cases where clock signa...

Page 554: ...l Unit The 16 bit Three Phase PWM Timing Unit is the core of the PWM Con troller and produces three pairs of pulse width modulated signals with high resolution and minimal processor overhead The outputs of this unit are such that a low level is interpreted as a command to turn on active low the associated power device Three configuration registers PWM_CTRL PWM_TM and PWM_DT determine the fundament...

Page 555: ... by Therefore the PWM switching period Ts can be written as For example for an fSCLK of 100 MHz and a desired PWM switching fre quency fPWM of 10 kHz Ts 100 s the correct value to load into the PWM_TM register is The largest value that can be written to the 16 bit PWM_TM register is 0xFFFF 65 535 which at an fSCLK of 100 MHz corresponds to a min imum PWM switching frequency of PWM_TM values of 0 a...

Page 556: ... capacitor of a typical voltage source inverter The 10 bit read write PWM_DT register controls the dead time This register controls the dead time inserted into the three pairs of PWM output sig nals Dead time Td is related to the value in the PWM_DT register by Therefore a PWM_DT value of 0x00A introduces a 200 ns delay for a SCLK of 100 MHz between turning off any PWM signal for example AH and th...

Page 557: ...PWM Timing Unit In addition the PWM_SEG register is also latched into the Output Control Unit on the rising edge of the PWM_SYNC pulse In effect this means that the characteristics and resultant duty cycles of the PWM signals can be updated only once per PWM period at the start of each cycle This results in PWM patterns that are symmetrical about the midpoint of the switching period In double upda...

Page 558: ...putational burden on the processor Alternatively the same PWM update rate may be maintained at half the switching frequency yielding lower switching losses The PWM_STAT2 status register is provided for software simulation This register contains the output values of all the three pairs of PWM signals PWM_AH PWM_AL PWM_BH PWM_BL PWM_CH and PWM_CL PWM Duty Cycle PWM_CHA PWM_CHB and PWM_CHC Registers ...

Page 559: ...by the fundamental time increment tSCLK and comparing to the two s com plement counter Notice that the switching patterns are perfectly symmetrical about the midpoint of the switching period in single update mode since the same values of PWM_CHA PWM_TM and PWM_DT are used to define the signals in both half cycles of the period As implied by Figure 14 3 the programmed duty cycles are adjusted to in...

Page 560: ...ds produced by the Three Phase PWM Tim ing Unit and illustrated in Figure 14 3 may be written as Figure 14 3 Typical PWM Outputs of Three Phase Timing Unit in Single Update Mode Active Low Waveforms PWMCHA PWMCHA 2 PWMDT PWM_AH PWM_AL PWMTM 2 PWMTM 2 PWMTM 2 COUNT 0 0 2 PWMDT PWMTM PWMTM PWM_PHASE PWMSYNC_OUT T AH PWMTM 2 PWMCHA PWMDT tSCLK Range of TAH 0 2 PWMTM tSCLK ...

Page 561: ...is figure illustrates a completely general case in which the switching frequency dead time and duty cycle are changed in the second half of the PWM period Of course the same value for any or all of these quantities may be used in both halves of the PWM cycle However it can be seen that there is no guarantee that a symmetri cal PWM signal will be produced by the Three Phase PWM Timing Unit in doubl...

Page 562: ...mode can be defined as Figure 14 4 Typical PWM Outputs of Three Phase Timing Unit in Double Update Mode Active Low Waveforms PWMCHA1 PWMCHA2 2 PWMDT1 PWM_AH PWM_AL PWMTM1 2 PWMTM2 2 PWMTM1 2 COUNT 0 0 2 PWMDT2 PWMTM1 PWMTM2 PWM_PHASE PWMSYNC_OUT PWMTM2 2 T AH PWMTM1 2 PWMTM2 2 PWMCHA1 PWMCHA2 PWMDT 1 PWMDT 2 tSCLK T AL PWMTM1 2 PWMTM2 2 PWMCHA1 PWMCHA2 PWMDT 1 PWMDT 2 tSCLK ...

Page 563: ...ch ing period is given by Again the values of TAH and TAL are constrained to lie between zero and Ts Similar PWM signals to those illustrated in Figure 14 2 on page 14 5 and in Figure 14 3 on page 14 16 can be produced on the BH BL CH and CL outputs by programming the PWM_CHB and PWM_CHC registers in a manner identical to that described for PWM_CHA T S PWMTM1 PWMTM2 tSCLK d AH T AH T S 1 2 PWMCHA1...

Page 564: ...ion with the PWM_DT register Full Off Mode The PWM for any pair of PWM signals is said to operate in full off mode when the desired high side output of the Three Phase PWM Timing Unit is in the off state high or low as specified by the PWM_POLARITY bit of the PWM_CTRL register between successive PWM_SYNC pulses This state may be entered by virtue of the commanded duty cycle values in conjunction w...

Page 565: ...provided the desired output is still scheduled to be in the on state after the emergency dead time delay Figure 14 5 illustrates two examples of such transitions In the top half marked A of Figure 14 5 no special action dead time is needed when transitioning from normal modulation to full on mode at the half cycle boundary in double update mode However in the bottom half marked B of Figure 14 5 wh...

Page 566: ...he Three Phase PWM Timing Unit over one full PWM period is illustrated in Figure 14 6 During the first half cycle when the PWM_PHASE bit of the PWM_STAT register is cleared the Three Phase PWM Timing Unit decrements from PWMTM 2 to PWMTM 2 using a two s complement count Then the Figure 14 5 Examples of Transitioning from Normal Modulation to Full On Mode A or Full Off Mode B PWMCHA1 2 PWMDT PWM_AH...

Page 567: ...e of the PWM_TM register is altered at the midpoint in double update mode the duration of the second half period when the PWM_PHASE bit of the PWM_STAT register is set may differ from that of the first half cycle PWM_TM is double buffered a change in one half of the PWM switching period will only take effect in the next half period Figure 14 6 Operation of Internal PWM Timer PWM TIMER DECREMENTS F...

Page 568: ...od In dou ble update mode improved accuracy is possible since different values of the duty cycles registers are used to specify the on times in both the first half and second half of the PWM period As a result it is possible to adjust the on time over the entire period in increments of tSCLK This cor responds to an effective PWM accuracy of tSCLK in double update mode 10 ns for a 100 MHz fSCLK The...

Page 569: ...f the PWM_SEG register enables crossover mode for the AH AL pair of PWM signals setting BHBL_XOVR enables crossover on the BH BL pair and setting CHCL_XOVR enables cross over on the CH CL pair If crossover mode is enabled for any pair of PWM signals the high side PWM signal for example AH from the Three Phase PWM Timing Unit is diverted to the associated low side output of the Output Control Unit ...

Page 570: ...t controls AH the BL_EN bit controls BL the BH_EN bit controls BH the CL_EN bit controls CL and the CH_EN bit controls the CH output If the associated bit of the PWM_SEG register is set the correspond ing PWM output is disabled irrespective of the value of the corresponding duty cycle register This PWM output signal will remain in the off state as long as the corresponding enable disable bit of th...

Page 571: ...M_SEG register to crossover the BH BL pair if PWM signals it is possible to turn on the high side switch of phase A and the low side switch of phase B at the same time In ECM control usually the third inverter leg phase C in this example is disabled for a number of PWM cycles This is implemented by disabling the CH and CL outputs by setting the CH_EN and CL_EN bits of the PWM_SEG register This is ...

Page 572: ...er is 0x00A7 In normal ECM operation each inverter leg is disabled for certain lengths of time such that the PWM_SEG register is changed based upon the position of the rotor shaft motor commutation Figure 14 7 Example of Active Low Signals for ECM Control PWMCHA PWMCHB PWMCHA PWMCHB 2 PWMDT PWM_AH PWM_AL PWM_BH PWM_BL PWM_CH PWM_CL PWMTM 2 PWMTM 2 PWMTM 2 COUNT 0 0 ...

Page 573: ...quired for high side drivers only for low side drivers only or for both high side and low side switches Therefore independent control of this mode for both high and low side switches is included with two separate control bits CHOPHI and CHOPLO in the PWM_GATE register Typical PWM output signals with high frequency chopping enabled on both high and low side signals are shown in Figure 14 8 Chopping...

Page 574: ...ed before operation of the PWM Controller and typically are not changed during normal operation of the PWM Controller Following a reset all bits of the PWM_GATE register are cleared so that high frequency chopping is disabled by default PWM Polarity Control The polarity of the PWM signals produced at output pins AH to CL can be programmed via the PWM_POLARITY bit of the PWM_CTRL register Setting F...

Page 575: ...which output control features are applied to the PWM signal The following hierarchy indicates the order from most important to least important in which signal features are applied to the PWM output signal 1 Channel duty generation 2 Channel crossover 3 Low side invert 4 Output enable 5 Emergency dead time insertion 6 Active signal chopping 7 Polarity Switched Reluctance SR Mode The PWM Controller ...

Page 576: ...h switches at the same time SR mode provides four mode types hard chop alternate chop soft chop bottom on and soft chop top on see Table 14 2 Three registers PWM_CHAL PWM_CHBL and PWM_CHCL are used to define edge placement of the low side of the channel The PWM_DT register which is not used is internally forced to 0 by hardware when SR mode is active The four switched reluctance SR chop modes are ...

Page 577: ... and Table 14 2 describes the four mode types Figure 14 9 Four SR Mode Types SOFT CHOP TOP ON SOFT CHOP BOTTOM ON HARD CHOP ALTER NATE CHOP PWMCHA1 PWMCHA2 PWMCHAL1 PWM_AL PWM_AH PWM_AL PWM_AH PWM_AL PWM_AH PWM_AL PWMCHA1 PWMCHAL1 PWMCHA1 PWMCHAL1 PWMCHAL2 PWMCHA2 PWMCHA2 PWMCHAL2 PWMCHAL2 PWMTM1 PWMTM2 PWMTM 2 PWMTM 2 PWMTM 2 PWM_AH COUNT 0 0 ...

Page 578: ...es in the next PWM half cycle The PWM_CHA duty register is used for the high channel and the PWM_CHAL duty register is used for the low channel A similar structure is present for the B and C channels Alternate chop Similar to normal PWM operation but the PWM channel high and low signal edges are opposite and are independently programmed The PWM_CHA duty register is used for the high channel and th...

Page 579: ...fault PWM_SYNC width is 10 24 s again for an fSCLK of 100 MHz External PWM SYNC Generation By setting the PWM_EXTSYNC bit of the PWM_CTRL register the PWM is set up in a mode to expect an external PWM SYNC on the PWM_SYNC pin The external sync should be synchronized by setting the PWM_SYNCSEL bit of the PWM_CTRL register to 0 which assumes the selected external PWM SYNC is asynchronous The externa...

Page 580: ...ed by the PWM_POLARITY bit of the PWM_CTRL register However the PWM_SYNC pulse occurs if it was previously enabled and the associated interrupt is also not stopped The processor s PWM_TRIP signal should have an external pull down resistor if the pin becomes disconnected the PWM Controller will be disabled The state of the PWM_TRIP pin can be read from the PWM_TRIP bit of the PWMSTAT register On th...

Page 581: ...e PWM_EN bit is written to 0 and the time the waveforms are disabled the latency is 2 SCLK cycles After enabling the PWM_EN bit output waveforms will begin to appear from the next PWM pulse PWM Registers Descriptions and bit diagrams for each of the PWM memory mapped registers MMRs are provided in the following sections Table 14 3 PWM Registers Name Description PWM_CTRL PWM control register on pag...

Page 582: ...PWM_CHBL PWM channel BL duty control SR mode only on page 14 47 PWM_CHCL PWM channel CL duty control SR mode only on page 14 47 PWM_LSI PWM low side invert SR mode only on page 14 49 PWM_STAT2 PWM simulation status register on page 14 49 Figure 14 10 PWM Control Register Table 14 3 PWM Registers Cont d Name Description 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 PWM Contr...

Page 583: ...gle update mode 1 double update mode RW 0 3 PWM_EXTSYNC External sync 0 internal sync 1 external sync RW 0 4 PWM_SYNCSEL External sync select 0 asynchronous 1 synchronous RW 1 5 PWM_POLARITY PWM output polarity 1 active high 0 active low RW 1 6 PWM_SRMODE PWM SR Mode 0 enabled 1 disabled RW 1 7 PWMTRIPINT_EN Interrupt enable for trip 1 enabled 0 disabled RW 0 8 PWMSYNCINT_EN Interrupt enable for s...

Page 584: ...STAT Register Bit Name Function Type Default 0 PWM_PHASE PWM phase 0 first half 1 second half RO 0 1 PWM_POL PWM polarity 1 active high 0 active low RO 1 2 PWM_SR PWM SR mode 0 active 1 inactive RO 1 3 PWM_TRIP PWM trip RO 0 7 4 Reserved 0 8 PWM_TRIPINT PWM trip interrupt via hardware pin or software R W1C 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 PWM Status Register ...

Page 585: ...re provided in Figure 14 12 and Table 14 6 9 PWM_SYNCINT PWM sync interrupt R W1C 0 15 10 Reserved 0 Figure 14 12 PWM Period Register Table 14 6 PWM_TM Register Bit Name Function Type Default 15 0 PWM_TM PWM period unsigned RW 0 Table 14 5 PWM_STAT Register Cont d Bit Name Function Type Default 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PWM Period Register PWM_TM PWM_TM ...

Page 586: ...ermits the mixing of the output PWM signals with a high frequency chopping signal The features of gate drive chopping mode are controlled by the PWM_GATE register Bit diagrams and descriptions are provided in Figure 14 14 and Table 14 8 Figure 14 13 PWM Dead Time Register Table 14 7 PWM_DT Register Bit Name Function Type Default 9 0 PWM_DT PWM dead time unsigned RW 0 15 10 Reserved 0 15 14 13 12 1...

Page 587: ...for each are provided in Figure 14 15 through Figure 14 17 and Table 14 9 through Table 14 11 Figure 14 14 PWM Chopping Control Register Table 14 8 PWM_GATE Register Bit Name Function Type Default 7 0 GDCLK PWM gate chopping period unsigned RW 0 8 CHOPHI Gate chopping enable high side RW 0 9 CHOPLO Gate chopping enable low side RW 0 15 10 Reserved 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 ...

Page 588: ...ction Type Default 15 0 PWMCHB Channel B duty two s complement RW 0 Figure 14 17 PWM Channel C Duty Control Register 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PWM Channel A Duty Control Register PWM_CHA PWMCHA Reset 0x0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PWM Channel B Duty Control Register PWM_CHB PWMCHB Reset 0x0000 15 14 13 12 11 ...

Page 589: ...r each output pair Bit diagrams and descriptions are provided in Figure 14 18 and Table 14 12 Table 14 11 PWM_CHC Register Bit Name Function Type Default 15 0 PWMCHC Channel C duty two s complement RW 0 Figure 14 18 PWM Crossover and Output Enable Register 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PWM Crossover and Output Enable Register PWM_SEG CH_EN CL_EN BH_EN BL_EN ...

Page 590: ... enabled RW 0 2 BH_EN BH output enable 1 disabled 0 enabled RW 0 3 BL_EN BL output enable 1 disabled 0 enabled RW 0 4 AH_EN AH output enable 1 disabled 0 enabled RW 0 5 AL_EN AL output enable 1 disabled 0 enabled RW 0 6 CHCL_XOVR Channel C output crossover 1 XOVR 0 not XOVR RW 0 7 BHBL_XOVR Channel B output crossover 1 XOVR 0 not XOVR RW 0 8 AHAL_XOVR Channel A output crossover 1 XOVR 0 not XOVR R...

Page 591: ... used to program duty cycle for a low side channel in SR switched reluctance mode only Bit diagrams and descriptions for each register are provided in Figure 14 20 through Figure 14 22 and Table 14 14 through Table 14 16 Figure 14 19 PWM Sync Pulse Width Control Register Table 14 13 PWM_SYNCWT Register Bit Name Function Type Default 9 0 PWMSYNCWT PWM sync pulse width unsigned RW 0x03FF 15 10 Reser...

Page 592: ...n Type Default 15 0 PWMCHBL Channel B duty two s complement RW 0 Figure 14 22 PWM Channel CL Duty Control Register 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PWM Channel AL Duty Control Register PWM_CHAL PWM_CHAL Reset 0x0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PWM Channel BL Duty Control Register PWM_CHBL PWM_CHBL Reset 0x0000 15 14 13 ...

Page 593: ...ls via software This can be useful for Table 14 16 PWM_CHCL Register Bit Name Function Type Default 15 0 PWM_CHCL Channel C duty two s complement RW 0 Figure 14 23 PWM Low Side Invert Register Table 14 17 PWM_LSI Register Bit Name Function Type Default 0 PWM_SR_LSI_A PWM SR mode low side invert channel A RW 0 1 PWM_SR_LSI_B PWM SR mode low side invert channel B RW 0 2 PWM_SR_LSI_C PWM SR mode low ...

Page 594: ...ion Type Default 0 PWM_AL PWM_AL output signal for S W observation RO 0 1 PWM_AH PWM_AH output signal for S W observation RO 0 2 PWM_BL PWM_BL output signal for S W observation RO 0 3 PWM_BH PWM_BH output signal for S W observation RO 0 4 PWM_CL PWM_CL output signal for S W observation RO 0 5 PWM_CH PWM_CH output signal for S W observation RO 0 15 6 Reserved 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0...

Page 595: ...ramming Examples on page 15 46 Overview The ADSP BF50x Blackfin processors feature multiple separate and iden tical UART modules ADSP BF50x processors feature two UARTs referred to as UART0 and UART1 The UART modules are full duplex peripherals compatible with PC style industry standard UARTs sometimes called Serial Controller Interfaces SCI The UARTs convert data between serial and parallel forma...

Page 596: ... outputs for reception transmission and status Independent DMA operation for receive and transmit Programmable automatic RTS CTS hardware flow control on UART1 False start bit detection SIR IrDA operation mode Internal loop back Improved bit rate granularity The UARTs are logically compliant to EIA 232E EIA 422 EIA 485 and LIN standards but usually require external transceiver devices to meet elec...

Page 597: ...neral pur pose ports These two pins usually connect to an external transceiver device that meets the electrical requirements of full duplex for example Figure 15 1 UART Block Diagram UARTx_LSR UARTx_MSR UARTx_THR UARTx_RBR UARTx_IER UARTx_MCR SIC CONTROLLER UARTx_DLL UARTx_DLH DMA CONTROLLER UARTx_SCR UARTx_GCTL TSR PORTS UARTx RXREQ TXREQ PAB DABx STATREQ 8 8 BLACKFIN UARTxRX UARTxTX UARTx_LCR SE...

Page 598: ...e 15 1 UART Signals Signal Pin Port Control Autobaud Timer UART0 TX PF1 or PG13 PORTF_MUX 3 2 b 01 PORTF_FER 1 1 or PORTG_MUX 13 12 b 00 PORTG_FER 13 1 UART0 RX PF0 or PG12 PORTF_MUX 1 0 b 01 PORTF_FER 0 1 or PORTG_MUX 13 12 b 00 PORTG_FER 12 1 Timer 6 TMR6 or Timer 2 TACI2 UART0 RTS PG14 PORTG_MUX 15 14 b 00 PORTG_FER 14 1 UART0 CTS PG15 PORTG_MUX 15 14 b 00 PORTG_FER 15 1 UART1 TX PF6 or PG3 POR...

Page 599: ... to the DAB16 bus Each UART has three interrupt outputs The transmit request and receive request outputs can function as DMA requests and connect to the DMA controller Therefore if the DMA is not enabled the DMA controller simply forwards the request to the SIC controller The status interrupt output connects directly to the SIC controller When no DMA channel is assigned a UART has only one inter r...

Page 600: ...ed on one of the TX pins Aside from the standard UART functionality the UART also supports serial data communication by way of infrared signals according to the rec ommendations of the Infrared Data Association IrDA The physical layer known as IrDA SIR 9 6 115 2 Kbps rate is based on return to zero inverted RZI modulation Pulse position modulation is not supported Using the 16x data rate clock RZI...

Page 601: ... This is bit 0 of the value written to UARTx_THR Writes to the UARTx_THR register clear the THRE flag Transfers of data from UARTx_THR to the transmit shift registers TSR set this status flag in UARTx_ LSR again When enabled by the ETBEI bit in the UARTx_IER register the THRE flag requests an interrupt on the dedicated TXREQ output This signal is routed through the DMA controller If the associated...

Page 602: ... condition is assumed Otherwise the detected falling edge is discarded After detection of the start bit the received word is shifted into the inter nal shift register RSR at a bit rate characterized by the following formula After the corresponding stop bit is received the content of the RSR register is transferred through the 4 deep receive FIFO to the UARTx_RBR register shown in Figure 15 13 Fina...

Page 603: ... when the receive buffer holds two or more words If RFIT is set the RFCS bit is set when the receive buffer holds four or more words The RFCS bit is cleared by hardware when core or DMA read the UARTx_RBR register and when the buffer is flushed below the level of two RFIT 0 or four RFIT 4 If the associated interrupt bit ERFCI is enabled status interrupt is reported when the RFCS bit is set If erro...

Page 604: ... attempts to see a start bit The data is shifted into the internal RSR register After the 9th sample of the first stop bit is processed the received data is copied to the 5 stage receive buffer and the RSR recov ers for further data The receiver samples data bits close to their midpoint Because the receiver clock is usually asynchronous to the transmitter s data rate the sampling point may drift r...

Page 605: ...ACTS bits The signals are usually active low that is transmission is halted when the pin state is high The polarity of the UARTxCTS and UARTxRTS pins can be inverted by setting the FCPOL bit in the UARTx_MCR register If ACTS is enabled the UARTxCTS bit in the UARTx_MSR register holds the complement value FCPOL 0 or the value FCPOL 1 of the UARTxCTS input pin In either case the UARTxCTS bit reads 1...

Page 606: ...buffer does not contain any more data than the word in the UARTx_RBR register If RFRT is set the UARTxRTS pin is deasserted when the receive buffer already holds four words and a fifth start bit is detected The UARTxRTS is re asserted when the buffer con tains less than four words Hardware guarantees minimal UARTxRTS deassertion pulse width of at least the number of data bits as defined by the WLS...

Page 607: ... UART clock periods This results in the final representation of the original 0 as a high pulse of only 3 16 clock periods in a 16 cycle UART clock period The pulse is centered around the middle of the bit time as shown in Figure 15 4 The final IrDA pulse is fed to the off chip infrared driver This modulation approach ensures a pulse width output from the UART of three cycles high out of every 16 U...

Page 608: ...ive cross cou pling typically do not last for more than a fraction of the system clock period Sources outside of the chip and not part of the transmitter can be avoided by appropriate shielding The only other source of a glitch is the transmitter itself The processor relies on the transmitter to perform within specification If the transmitter violates the specification unpre dictable results may o...

Page 609: ...transition corresponds to a UART NRZ value of 0 IRPOL 1 assumes that the receive data input idles 1 and each active 0 transition corresponds to a UART NRZ value of 0 In the IrDA mode the EDB0 bit is ignored The sample frequency is always exactly 16 times the bit rate Figure 15 5 IrDA Receiver Pulse Detection 0 1 16 16 PULSE DETECT OR OUTPUT SAMPLING WINDOWN 8 16 16 16 RECOVERED NRZ INPUT 1 0 8 16 ...

Page 610: ...DSP BF50x Blackfin Processor Hardware Reference Volume 1 of 2 On ADSP BF50x processors not all UARTs have a DMA channel assigned by default Even if disabled a DMA channel is still required to forward the DMA requests to the SIC controller as interrupt requests see Figure 15 1 on page 15 3 Also if no DMA channel is assigned the UART loses its normal receive and trans mit interrupt functionality To ...

Page 611: ...cleared by clearing the ETBEI bit in the UARTx_IER_CLEAR register Receive interrupts are enabled by the ERBFI bit in the UARTx_IER_SET reg ister If set the receive request is asserted along with the DR bit in the UART_LSR register indicating that new data is available in the UARTx_RBR register When software reads the UARTx_RBR hardware clears the DR bit again which in turn clears the receive inter...

Page 612: ...e enabled by the EDSSI bit in the UARTx_IER_ SET register If active a status interrupt is generated when the sticky SCTS bit in the UARTx_MSR register is set indicating that the transmitter s UARTx CTS input been re asserted A W1C operation to the SCTS bit clears the interrupt request A transmission finished interrupt is enabled by the ETFI bit in the UARTx_ IER_SET register If active a status int...

Page 613: ... bit clock to more closely match the bit rate of the communication partner There is Table 15 2 UART Bit Rate Examples With 133 MHz SCLK Bit Rate Dfactor 16 DL Actual Error Dfactor 1 DL Actual Error 2400 3464 2399 68 0 013 55417 2399 99 0 001 4800 1732 4799 36 0 013 27708 4800 06 0 001 9600 866 9598 73 0 013 13854 9600 12 0 001 19200 433 19197 46 0 013 6927 19200 23 0 001 38400 216 38483 80 0 218 3...

Page 614: ... The capture capabilities of the timers are often used to supervise the bit rate at runtime If the Blackfin UART was talking to any device supplied by a weak clock oscillator that drifts over time the Blackfin can re adjust its UART bit rate dynamically as required Often autobaud detection is used for initial bit rate negotiations There the Blackfin processor is most likely a slave device waiting ...

Page 615: ... bits and 1 start bit apply the following formula Real UARTxRX signals often have asymmetrical falling and rising edges and the sampling logic level is not exactly in the middle of the signal volt age range At higher bit rates such pulse width based autobaud detection might not return adequate results without additional analog signal condi tioning Measuring signal periods works around this issue a...

Page 616: ... Mode In non DMA mode data is moved to and from the UART by the proces sor core To transmit a character load it into UARTx_THR Received data can be read from UARTx_RBR The processor must write and read a limited number of characters at a time To prevent any loss of data and misalignments of the serial data stream the UARTx_LSR register provides two status flags for handshaking THRE and DR The THRE...

Page 617: ...ecause polling is processor inten sive it is not typically used in real time signal processing environments Since read operations from UARTx_LSR registers have no side effects differ ent software threads can interrogate these registers without mutual impacts Polling the SIC_ISRx register without enabling the interrupts by SIC_MASKx is an alternate method of operation to consider Software can write...

Page 618: ...t by the processor loading and interrupt priorities For more information see Direct Memory Access on page 7 1 DMA interrupt routines must explicitly write 1s to the corresponding DMAx_IRQ_STATUS registers to clear the latched request of the pending interrupt The UART s DMA is enabled by first setting up the system DMA control registers and then enabling the UART ERBFI and or ETBEI interrupts in th...

Page 619: ...n may abort in the middle of the stream causing data loss if the UART clock was disabled without additional synchronization with the TEMT bit The UART s DMA supports 8 bit and 16 bit operation but not 32 bit operation Sign extension is not supported Mixing Modes Especially on the transmit side switching from DMA mode to non DMA operation on the fly requires some thought By default the interrupt ti...

Page 620: ...words with the most signif icant byte zero filled Table 15 3 provides an overview of the UART registers Unlike on ADSP BF52x processors register addresses are not shared on ADSP BF50x processors Each register has its own MMR address Conse quently the DLAB bit is not present on ADSP BF50x processors UARTx_ LSR registers Software must use 16 bit word load store instructions to access these registers...

Page 621: ...er on page 15 45 UARTx_LCR 0x0C 0x0C UART line control registers on page 15 28 UARTx_MCR 0x10 0x10 UART modem control registers on page 15 31 UARTx_LSR 0x14 0x14 UART line status registers on page 15 33 UARTx_MSR 0x18 N A UART modem status registers on page 15 36 UARTx_SCR 0x1C 0x1C UART scratch registers on page 15 44 UARTx_IER_SET 0x20 N A UART interrupt enable set registers on page 15 39 UARTx_...

Page 622: ...FC0 200C SB Set Break 0 No force 1 Force TX pin to 0 STP Stick Parity Forces parity to defined value if set and PEN 1 EPS 0 parity transmitted and checked as 1 EPS 1 parity transmitted and checked as 0 EPS Even Parity Select 0 Odd parity when PEN 1 and STP 0 1 Even parity WLS 1 0 Word Length Select 00 5 bit word 01 6 bit word 10 7 bit word 11 8 bit word STB Stop Bits 0 1 stop bit 1 2 stop bits for...

Page 623: ...ty bit with the expected value and issues a parity error if they don t match If PEN is cleared the STP and the EPS bits are ignored The STP bit controls whether the parity is generated by hardware based on the data bits or whether it is set to a fixed value If STP 0 the hardware cal culates the parity bit value based on the data bits Then the EPS bit determines whether odd or even parity mode is c...

Page 624: ...whether or not data is currently transmitted It functions even when the UART clock is disabled Since the UARTxTX pin normally drives high it can be used as a flag output pin if the UART is not used 1 0 1 0x57 1110 1010 1 1 1 0 x x 1 1 1 0 x x 1 1 1 1 x x 0 1 1 1 x x 0 Table 15 5 UART Parity Cont d PEN STP EPS Data hex Data binary LSB first Parity ...

Page 625: ... from RSR TX remains active Internally redirects TX to RSR Deasserts pin UARTxRTS Disconnects pin CTS Internally redirects bit MRTS of UARTx_MCR to bit CTS of UART_MSR Enable transmit receive by setting MRTS bit FCPOL Flow Control Pin Polarity For memory mapped addresses see Table 15 6 0 Set RFCS 1 if RX buffer count 2 1 Set RFCS 1 if RX buffer count 4 RFIT Receive FIFO IRQ Threshold ignored if AR...

Page 626: ...asserted if the buffer contains less than two words If RFRT 1 the RTS signal is deasserted when already four words are held by the receive buffer and a fifth start bit is detected The RTS signal is re asserted if the buffer contains less than four words Similarly the automatic CTS ACTS bit must be set to enable the CTS input pin for UARTxTX handshaking If enabled the CTS status bit in the UARTx_MS...

Page 627: ...ansmitter Writing a 0 to the MRTS bit clears bit UARTxCTS and disable the UART s transmitter UARTx_LSR Registers The line status UARTx_LSR registers contain UART status information as shown in Figure 15 10 Unlike the industrial standard the ADSP BF50x processor s UARTx_LSR register is not read only Writes to this register can perform write one to clear W1C operations on most status bits Reading th...

Page 628: ...ART Line Status Register Memory Mapped Addresses Register Name Memory Mapped Address UART0_LSR 0xFFC0 0414 UART1_LSR 0xFFC0 2014 DR Data Ready RO TEMT TSR and UARTx_THR Empty RO UART Line Status Registers UARTx_LSR 0 Full 1 Both empty 0 THR not empty 1 THR empty 0 No break interrupt 1 Break interrupt this indicates UARTxRX was held low for more than the max imum word length BI Break Interrupt W1C ...

Page 629: ...icky and can be cleared by W1C operations The THRE transmit hold register empty bit indicates that the UART transmit channel is ready for new data and software can write to UARTx_ THR Writes to UARTx_THR clear the THRE bit It is set again when data is passed from UARTx_THR to the internal TSR register The TEMT transmitter empty bit indicates that both the UARTx_THR regis ter and the internal TSR r...

Page 630: ... as there is data to transmit regardless of the value of UARTxCTS When ACTS 0 the software can pause transmission temporarily by setting the XOFF bit Figure 15 11 UART Modem Status Registers Table 15 8 UART Modem Status Register Memory Mapped Addresses Register Name Memory Mapped Address UART0_MSR 0xFFC0 0418 UART1_MSR 0xFFC0 2018 SCTS Sticky CTS W1C UART Modem Status Registers UARTx_MSR Reset 0x0...

Page 631: ...ad sufficient times until the buffer is drained below the threshold The RFCS bit can trigger a status interrupt if enabled by the ERFCI bit in the UARTx_IER_SET register In loopback mode LOOP_ENA 1 the UARTxCTS bit is disconnected from the UARTxCTS input pin Instead it is directly connected to the MRTS bit of the UARTx_MCR register Previous implementations of the UART did not have this register It...

Page 632: ...ART Transmit Holding Registers Table 15 9 UART Transmit Holding Register Memory Mapped Addresses Register Name Memory Mapped Address UART0_THR 0xFFC0 0428 UART1_THR 0xFFC0 2028 Figure 15 13 UART Receive Buffer Registers Transmit Hold 7 0 UART Transmit Holding Registers UARTx_THR W Reset 0x0000 For memory mapped addresses see Table 15 9 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 ...

Page 633: ... set Setting this register without enabling system DMA causes the UART to notify the processor of data inventory state by means of interrupts For proper operation in this mode system interrupts must be enabled and appropriate interrupt handling routines must be present Each UART features three separate interrupt channels to handle data transmit data receive and line status events independently reg...

Page 634: ...rate RX interrupt if DR bit in UARTx_LSR is set 0 No interrupt 1 Generate TX interrupt if THRE bit in UARTx_LSR is set 0 No interrupt 1 Generate status interrupt if any of UARTx_LSR 4 1 is set Reset 0x0000 ETFI Enable Transmission Finished Interrupt Unused EDSSI Enable Modem Status Interrupt 0 No interrupt 1 Generate status interrupt if TFI bit in UARTx_LSR is set 0 No interrupt 1 Generate status ...

Page 635: ...egister Name Memory Mapped Address UART0_IER_CLEAR 0xFFC0 0424 UART1_IER_CLEAR 0xFFC0 2024 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ERBFI Enable Receive Buf fer Full Interrupt UART Interrupt Enable Clear Registers UARTx_IER_CLEAR ETBEI Enable Transmit Buffer Empty Interrupt ELSI Enable RX Status Interrupt 0 No interrupt 1 Generate RX interrupt if DR bit in UARTx_LSR is...

Page 636: ...status interrupt channel when both the transmit buffer register and transmit shift register are empty as indicated by the TFI bit in the UARTx_LSR register The ETFI interrupt can be used to avoid expensive polling of the TEMT bit when the UART clock or line drivers should be disabled after transmission has com pleted W1C the TFI bit to clear the interrupt request In DMA operation the ETDPTI bit s ...

Page 637: ...gisters UARTx_DLL and UARTx_DLH Registers The two 8 bit clock divisor latch registers UARTx_DLH and UARTx_DLL build a 16 bit clock divisor value They divide the system clock SCLK down to the bit clock These registers are shown in Figure 15 16 Figure 15 16 UART Divisor Latch Registers 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0...

Page 638: ...shown in Figure 15 17 are reset to 0x00 They are used for general purpose data storage and do not control the UART hardware in any way Table 15 13 UART Divisor Latch Low Byte Register Memory Mapped Addresses Register Name Memory Mapped Address UART0_DLL 0xFFC0 0400 UART1_DLL 0xFFC0 2000 Table 15 14 UART Divisor Latch High Byte Register Memory Mapped Addresses Register Name Memory Mapped Address UA...

Page 639: ...RT Clocks 0 Disable UART clocks 1 Enable UART clocks Reset 0x0000 IREN Enable IrDA Mode 0 Disable IrDA 1 Enable IrDA FPE Force Parity Error on Transmit 0 Normal operation 1 Force error FFE Force Framing Error on Transmit 0 Normal operation 1 Force error UART Global Control Registers UARTx_GCTL TPOLC IrDA TX Polarity Change 0 Serial line idles low 1 Serial line idles high RPOLC IrDA RX Polarity Cha...

Page 640: ...ly in loopback mode The EDBO bit enables bypassing of the divide by 16 prescaler in bit clock generation This improves bit rate granularity especially at high bit rates See Bit Rate Generation on page 15 18 Do not set this bit in IrDA mode The EGLSI bit redirects TX and RX interrupt requests to the status inter rupt output of the UART by ORing them with all other kinds of UART status interrupt req...

Page 641: ...lue to be written into DLH DLL registers p0 contains the UARTx_GCTL register address Return values none uart_init sp r7 r7 UCEN z First of all enable UART clock w p0 UART0_GCTL UART0_GCTL r7 w p0 UART0_DLL UART0_GCTL r0 write lower byte to DLL r7 r0 8 w p0 UART0_DLH UART0_GCTL r7 write upper byte to DLH r7 STB WLS 8 z config to w p0 UART0_LCR UART0_GCTL r7 8 bits no parity 2 stop bits r7 sp rts ua...

Page 642: ...ontains the UARTx_GCTL register address p1 contains the TIMERx_CONFIG register address Return values r0 holds timer period value equals 8 bits uart_autobaud sp r7 5 p5 5 r5 h hi TIMER0_CONFIG for generic timer use calculate r5 l lo TIMER0_CONFIG specific bits first r7 p1 r7 r7 r5 r7 4 r7 holds the x of TIMERx_CONFIG now r5 TIMEN0 z r5 r7 r5 holds TIMENx TIMDISx now r6 TRUN0 TOVL_ERR0 TIMIL0 z r6 r...

Page 643: ...CC r7 0 if CC jump uart_autobaud wait w p5 TIMER_DISABLE TIMER_STATUS r5 disable Timer x p5 TIMER_STATUS TIMER_STATUS r6 clear pending latches Save period value to R0 r0 p1 TIMER0_PERIOD TIMER0_CONFIG delay processing as autobaud character is still ongoing r7 OUT_DIS IRQ_ENA PERIOD_CNT PWM_OUT z w p1 TIMER0_CONFIG TIMER0_CONFIG r7 w p5 TIMER_ENABLE TIMER_STATUS r5 uart_autobaud delay r7 w p5 TIMER...

Page 644: ...PG12 PG13 z w p0 r0 p0 l lo UART0_GCTL select UART 0 p0 h hi UART0_GCTL p1 l lo TIMER2_CONFIG select TIMER 2 p1 h hi TIMER2_CONFIG call uart_autobaud r0 7 divide PERIOD value by 16 x 8 call uart_init The subroutine in Listing 15 4 transmits a character by polling operation Listing 15 4 UART Character Transmission Transmit a single byte by polling the THRE bit Input parameters r0 holds the characte...

Page 645: ...hown in Listing 15 5 to transmit a C style string that is terminated by a null character Listing 15 5 UART String Transmission Transmit a null terminated string Input parameters p1 points to the string p0 contains UARTx_GCTL register address Return values none uart_puts sp rets sp r0 uart_puts loop r0 b p1 z CC r0 0 if CC jump uart_puts exit call uart_putc jump uart_puts loop uart_puts exit r0 sp ...

Page 646: ...e ORed together in the SIC controller or by the EGLSI control bit If they had three different service routines they may look as shown in Listing 15 6 Listing 15 6 UART Non DMA Interrupt Operation isr_uart_rx sp astat sp r7 r7 w p0 UART0_RBR UART0_GCTL z b p4 r7 ssync r7 sp astat sp rti isr_uart_rx end isr_uart_tx sp astat sp r7 r7 b p3 z CC r7 0 if CC jump isr_uart_tx final w p0 UART0_THR UART0_GC...

Page 647: ... sp astat sp ssync rti isr_uart_error end Listing 15 7 transmits a string by DMA operation waits until DMA com pletes and sends an additional string by polling Note the importance of the SYNC bit Listing 15 7 UART Transmission SYNC Bit Use section data byte sHello Hello Blackfin User 13 10 0 byte sWorld How is life 13 10 0 section program p1 l lo IMASK p1 h hi IMASK r0 l lo isr_uart_tx register se...

Page 648: ..._CONFIG r7 l lo sHello r7 h hi sHello p5 DMA7_START_ADDR DMA7_CONFIG r7 r7 length sHello z r7 1 don t send trailing null character w p5 DMA7_X_COUNT DMA7_CONFIG r7 r7 1 w p5 DMA7_X_MODIFY DMA7_CONFIG r7 r7 FLOW_STOP WDSIZE_8 DI_EN SYNC DMAEN z w p5 r7 p0 l lo UART0_GCTL select UART 0 p0 h hi UART0_GCTL r0 ETBEI z enable and issue first request w p0 UART0_IER UART0_GCTL r0 wait4dma just one way to ...

Page 649: ...ART Port Controllers p1 h hi sWorld call uart_puts forever jump forever isr_uart_tx sp astat sp r7 r7 DMA_DONE z W1C interrupt request w p5 DMA7_IRQ_STATUS DMA7_CONFIG r7 r7 ETBEI z w p0 UART0_IER_CLEAR UART0_GCTL r7 ssync r7 sp astat sp rti isr_uart_tx end ...

Page 650: ...Programming Examples 15 56 ADSP BF50x Blackfin Processor Hardware Reference ...

Page 651: ...DSP BF50x product refer to ADSP BF504 ADSP BF504F ADSP BF506F Embedded Processor Data Sheet For TWI interrupt vector assignments refer to Table 4 3 on page 4 19 in Chapter 4 System Interrupts To determine how each of the TWIs is multiplexed with other functional pins refer to Table 9 1 on page 9 4 through Table 9 3 on page 9 6 in Chapter 9 General Purpose Ports For a list of MMR addresses for each...

Page 652: ...Protocol related inter rupts are optional The TWI externally moves 8 bit data while maintaining compliance with the I2 C bus protocol The TWI controller includes these features Simultaneous master and slave operation on multiple device systems Support for multi master bus arbitration 7 bit addressing 100K bits second and 400K bits second data rates General call address support Master clock synchro...

Page 653: ... one bit at a time at the SCL rate to and from other TWI devices The SCL signal synchronizes the shifting and sampling of the data on the serial data pin External Interface The SDA serial data and SCL serial clock signals are open drain and as such require pull up resistors Figure 16 1 TWI Block Diagram PAB TWI INTERFACE LOGIC CLOCK GENERATION Tx REG 2 DEEP FIFO 2 DEEP FIFO Rx REG Tx SHIFT REG Rx ...

Page 654: ...eference is derived from SCLK using a prescaled value PRESCALE fSCLK 10MHz The PRESCALE value is the number of system clock SCLK periods used in the generation of one internal time reference The value of PRESCALE must be set to create an internal time reference with a period of 10 MHz It is represented as a 7 bit binary value It is not always possible to achieve 10 MHz accuracy In such cases it is...

Page 655: ... can be updated by their respective functional blocks The FIFO buffer is configured as a1 byte wide 2 deep transmit FIFO buf fer and a 1 byte wide 2 deep receive FIFO buffer The transmit shift register serially shifts its data out externally off chip The output can be controlled for generation of acknowledgements or it can be manually overwritten The receive shift register receives its data serial...

Page 656: ...retching when config ured in slave mode Description of Operation The following sections describe the operation of the TWI interface TWI Transfer Protocols The TWI controller follows the transfer protocol of the Philips I2C Bus Specification version 2 1 dated January 2000 A simple complete transfer is diagrammed in Figure 16 2 To better understand the mapping of TWI controller register contents to ...

Page 657: ...is shown in Figure 16 4 The TWI controller s serial clock SCL output follows these rules Once the clock high CLKHI count is complete the serial clock out put is driven low and the clock low CLKLOW count begins Once the clock low count is complete the serial clock line is three stated and the clock synchronization logic enters into a delay mode shaded area until the SCL line is detected at a logic ...

Page 658: ...c 1 level the TWI controller has lost arbitration and ends generation of clock and data Note arbitration is not performed only at serial clock edges but also during the entire time SCL is high Start and Stop Conditions Start and stop conditions involve serial data transitions while the serial clock is a logic 1 level The TWI controller generates and recognizes these transitions Typically start and...

Page 659: ...ontroller addressed as a slave transmitter If the master asserts a stop condition during the data phase of a transfer the TWI controller concludes the transfer SCOMP and indicates a slave transfer error SERR TWI controller as a master transmitter or master receiver If the stop bit is set during an active master transfer the TWI con troller issues a stop condition as soon as possible avoiding any e...

Page 660: ...ng with loading transmit FIFO data The byte following the general call address usually defines what action needs to be taken by the slaves in response to the call The command in the second byte is interpreted based on the value of its LSB For a TWI slave device this is not applicable and the bytes received after the general call address are considered data Fast Mode Fast mode essentially uses the ...

Page 661: ...r is enabled a bus busy condition may be detected This condition should clear after tBUF has expired assuming no additional bus activity has been detected Slave Mode When enabled slave mode operation supports both receive and transmit data transfers It is not possible to enable only one data transfer direction and not acknowledge NAK the other This is reflected in the following setup 1 Program TWI...

Page 662: ... is intended for slave mode transmission Table 16 2 shows what the interaction between the TWI controller and the processor might look like using this example Master Mode Clock Setup Master mode operation is set up and executed on a per transfer basis An example of programming steps for a receive and for a transmit are given separately in following sections The clock setup programming step listed ...

Page 663: ...MASK Enable bits associated with the desired interrupt sources As an example programming the value 0x0030 results in an interrupt output to the processor in the event that the master transfer completes and the master transfer has an error 5 Program TWI_MASTER_CTL Ultimately this prepares and enables master mode operation As an example programming the value 0x0201 enables master mode operation gene...

Page 664: ...r in the event that the master transfer completes and the master transfer has an error 4 Program TWI_MASTER_CTL Ultimately this prepares and enables master mode operation As an example programming the value 0x0205 enables master mode operation generates a 7 bit address sets the direction to master receive uses standard mode timing and receives 8 data bytes before generating a Stop condition After ...

Page 665: ...ogrammer in developing a service routine Transmit Receive Repeated Start Sequence Figure 16 7 shows a repeated start data transmit followed by a data receive sequence Table 16 4 Master Mode Receive Setup Interaction TWI Controller Master Processor Interrupt RCVFULL Receive buffer is full Read receive FIFO buffer Acknowledge Clear interrupt source bits Interrupt MCOMP Master transfer com plete Ackn...

Page 666: ...the RSTART bit to indicate a repeated start and set the MDIR bit if the following trans fer is a data receive MCOMP interrupt This interrupt was generated because all data has been transferred DCNT 0 If no errors were generated a start condition is initi ated Clear the RSTART bit and program the DCNT with the desired number of bytes to receive RCVSERV interrupt This interrupt is generated due to t...

Page 667: ...sfer is a data transmit MCOMP interrupt This interrupt has occurred due to the completion of the data receive transfer If no errors were generated a start condition is ini tiated Clear the RSTART bit and program the DCNT with the desired number of bytes to transmit XMTSERV interrupt This interrupt is generated due to a FIFO access Simple data han dling is all that is required MCOMP interrupt The t...

Page 668: ...er supports three modes of clock stretching Clock Stretching During FIFO Underflow Clock Stretching During FIFO Overflow on page 16 20 Clock Stretching During Repeated Start Condition on page 16 21 Clock Stretching During FIFO Underflow During a master mode transmit an interrupt is generated at the instant the transmit FIFO becomes empty At this time the most recent byte begins transmission If the...

Page 669: ... Transmit FIFO buffer is empty Acknowledge Clear interrupt source bits Write transmit FIFO buffer Interrupt MCOMP Master transmit com plete DCNT 0x00 Acknowledge Clear interrupt source bits S ADDRESS DATA ACK WITH STRETCH ACK R W DATA ACK DATA 11 01 00 XMTSTAT 1 0 TWI_XMT_DATA IS READ AT THIS TIME AND CLOCK STRETCHING IS RELEASED ACKNOWLEDGE WITH STRETCH 01 SCL ACKNOWLEDGE STRETCH BEGINS SOON AFTE...

Page 670: ...ta bytes previously received are read from the receive FIFO buffer TWI_RCV_DATA8 TWI_RCV_DATA16 No other action is required to release the clock and continue the reception of data This behavior continues until the reception is complete DCNT 0x00 at which time the reception is concluded MCOMP as shown in Figure 16 10 and described in Table 16 6 Figure 16 10 Clock Stretching During FIFO Overflow S A...

Page 671: ...ate a transfer complete interrupt MCOMP to signify the initial transfer has completed DCNT 0 This initial transfer is handled without any special bit setting sequences or timings The clock stretching logic described above applies here With no system related timing constraints the subsequent transfer receive or transmit is setup and activated This sequence can be repeated as many times as required ...

Page 672: ...ive clearing RSTART and setting new DCNT value nonzero Interrupt RCVSERV Receive FIFO is full Acknowledge Clear interrupt source bits Read receive FIFO buffer Interrupt MCOMP Master receive complete Acknowledge Clear interrupt source bits S ADDRESS RSTART STRETCH ADDRESS ACK R W DATA ACK DATA 0x01 0x00 0x80 DCNT 7 0 MDIR DIRECTION AND DCNT ARE WRITTEN AT THIS TIME CLOCK STRETCHING IS RELEASED REPE...

Page 673: ...RITE DATA INTO TWI_XMT_DATA REGISTER INTERRUPT SOURCE SCOMP XMTSERV WRITE TO TWI_XMT_DATA REGISTER TO PRE LOAD THE TX FIFO WRITE TO TWI_FIFO_CTL TO SELECT WHETHER 1 OR 2 BYTES GENERATE INTERRUPTS WRITE TO TWI_INT_MASK TO UNMASK TWI EVENTS TO GENERATE INTERRUPTS WRITE TO TWI_SLAVE_CTL TO ENABLE SLAVE FUNCTIONALITY WAIT FOR INTERRUPTS WRITE TWI_INT_STAT TO CLEAR INTERRUPT READ DATA FROM TWI_RCV_DATA...

Page 674: ... EVENTS TO GENERATE INTERRUPTS WAIT FOR INTERRUPTS WRITE TWI_MASTER_CTL WITH COUNT MDIR CLEARED AND MEN SET THIS STARTS THE TRANSFER RECEIVE WRITE TWI_INT_STAT TO CLEAR INTERRUPT INTERRUPT SOURCE XMTSERV MCOMP WRITE TWI_MASTER_CTL WITH COUNT MDIR SET AND MEN SET THIS STARTS THE TRANSFER WAIT FOR INTERRUPTS INTERRUPT SOURCE MCOMP RCVSERV WRITE TWI_INT_STAT TO CLEAR INTERRUPT READ DATA FROM TWI_RCV_...

Page 675: ...TROL register When this feature is set all slave asserted acknowl edgement bits are ignored by this master This feature is valid only during transfers where the TWI is mastering an SCCB bus Slave mode transfers should be avoided when this feature is enabled because the TWI controller always generates an acknowledge in slave mode For either master and or slave mode of operation the TWI controller i...

Page 676: ... 2500 ns and an internal time reference of 10 MHz period 100 ns CLKDIV 2500 ns 100 ns 25 For an SCL with a 30 duty cycle then CLKLOW 17 and CLKHI 8 Note that CLKLOW and CLKHI add up to CLKDIV The CLKHI field of the TWI_CLKDIV register specifies the number of 10 MHz time reference periods the serial clock SCL waits before a new clock Figure 16 14 TWI Control Register TWI Control Register TWI_CONTRO...

Page 677: ...ter controls the logic associated with slave mode operation Settings in this register do not affect master mode operation and should not be modified to control master mode functionality Figure 16 15 SCL Clock Divider Register Figure 16 16 TWI Slave Mode Control Register 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SCL Clock Divider Register TWI_CLKDIV CLKLOW 7 0 Reset 0x00...

Page 678: ...ata transfer 1 Slave receive transfers generate a data NAK not acknowledge at the conclusion of a data transfer The slave is still considered to be addressed Slave transmit data valid STDVAL 0 Data in the transmit FIFO is for master mode transmits and is not allowed to be used during a slave transmit and the transmit FIFO is treated as if it is empty 1 Data in the transmit FIFO is available for a ...

Page 679: ...ddress during the addressing phase of a transfer TWI Slave Mode Status Register TWI_SLAVE_STAT Figure 16 17 TWI Slave Mode Address Register Figure 16 18 TWI Slave Mode Status Register 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TWI Slave Mode Address Register TWI_SLAVE_ADDR SADDR 6 0 Slave Mode Address Reset 0x0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0...

Page 680: ...oes not affect slave mode status bits General call GCALL This bit self clears if slave mode is disabled SEN 0 0 At the time of addressing the address was not determined to be a general call 1 At the time of addressing the address was determined to be a general call Slave transfer direction SDIR This bit self clears if slave mode is disabled SEN 0 0 At the time of addressing the transfer direction ...

Page 681: ...equired Normal master and slave mode operation should not require override operation 0 Normal serial clock operation under the control of master mode clock generation and slave mode clock stretching logic 1 Serial clock output is driven to an active 0 level overriding all other logic This state is held until this bit is cleared Figure 16 19 TWI Master Mode Control Register 15 14 13 12 11 10 9 8 7 ...

Page 682: ...7 0 Indicates the number of data bytes to transfer As each data word is transferred DCNT is decremented When DCNT is 0 a stop condition is generated Setting DCNT to 0xFF disables the counter In this transfer mode data continues to be transferred until it is concluded by setting the STOP bit Repeat start RSTART 0 Transfer concludes with a stop condition 1 Issue a repeat start condition at the concl...

Page 683: ...its s timing specifications in use Master transfer direction MDIR 0 The initiated transfer is master transmit 1 The initiated transfer is master receive Master mode enable MEN This bit self clears at the completion of a transfer after the DCNT bit decrements to zero including transfers terminated due to errors 0 Master mode functionality is disabled If this bit is cleared dur ing operation the tra...

Page 684: ...address should be written to this regis ter For example if the slave address is b 1010000X where X is the read write bit then TWI_MASTER_ADDR is programmed with b 1010000 which corresponds to 0x50 When sending out the address on the bus the TWI controller appends the read write bit as appropriate based on the state of the MDIR bit in the master mode control register Figure 16 20 TWI Master Mode Ad...

Page 685: ...s could be due to having no pull up resistor on SCL or another agent is driving SCL low the acknowl edge bits ANAK and DNAK do not update This result occurs because the acknowledge conditions are sampled during the high phase of SCL Figure 16 21 TWI Master Mode Status Register 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TWI Master Mode Status Register TWI_MASTER_STAT Rese...

Page 686: ...ck sense SCLSEN This status bit can be used when direct sensing of the serial clock line is required The register value is delayed due to the input filter nominally 50 ns Normal master and slave mode operation should not require this feature 0 An inactive one is currently being sensed on the serial clock 1 An active zero is currently being sensed on the serial clock The source of the active driver...

Page 687: ...r read error BUFRDERR 0 The current master transmit has not detected a buffer read error 1 The current master transfer was aborted due to a transmit buf fer read error At the time data was required by the transmit shift register the buffer was empty This bit is W1C Data not acknowledged DNAK 0 The current master receive has not detected a NAK during data transmission 1 The current master transfer ...

Page 688: ...fer is complete or while an enabled master is waiting for an idle bus 1 A master transfer is in progress TWI FIFO Control Register TWI_FIFO_CTL The TWI_FIFO_CTL register control bits affect only the FIFO and are not tied in any way with master or slave mode operation Figure 16 22 TWI FIFO Control Register 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TWI FIFO Control Regist...

Page 689: ...nsmit buffer interrupt length XMTINTLEN This bit determines the rate at which transmit buffer interrupts are to be generated Interrupts may be generated with each byte trans mitted or after two bytes are transmitted 0 An interrupt XMTSERV is set when XMTSTAT indicates one or two bytes in the FIFO are empty 01 or 00 1 An interrupt XMTSERV is set when the XMTSTAT field in the TWI_FIFO_STAT register ...

Page 690: ... buffer is empty TWI FIFO Status Register TWI_FIFO_STAT TWI FIFO Status The fields in the TWI_FIFO_STAT register indicate the state of the FIFO buffers receive and transmit contents The FIFO buffers do not discrimi nate between master data and slave data By using the status and control bits provided the FIFO can be managed to allow simultaneous master and slave operation Figure 16 23 TWI FIFO Stat...

Page 691: ... is allowed 10 Reserved 11 The FIFO is full and contains two bytes of data Either a sin gle or double byte peripheral read of the FIFO is allowed Transmit FIFO status XMTSTAT 1 0 The XMTSTAT field is read only It indicates the number of valid data bytes in the FIFO buffer The status is updated with each FIFO buffer write using the peripheral data bus or read access by the transmit shift register S...

Page 692: ...Figure 16 24 TWI Interrupt Mask Register 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TWI Interrupt Mask Register TWI_INT_MASK For all bits 0 Interrupt generation disabled 1 Interrupt generation enabled SINITM Slave Transfer Initiated Interrupt Mask Reset 0x0000 SCOMPM Slave Transfer Complete Interrupt Mask SERRM Slave Transfer Error Interrupt Mask SOVFM Slave Overflow Int...

Page 693: ...VSTAT field in the TWI_FIFO_STAT register is updated to either 01 or 11 If RCVINTLEN is 1 this bit is set each time RCVSTAT is updated to 11 0 The receive FIFO does not require servicing or the RCVSTAT field has not changed since this bit was last cleared 1 The receive FIFO has one or two 8 bit locations available to be read Figure 16 25 TWI Interrupt Status Register 15 14 13 12 11 10 9 8 7 6 5 4 ...

Page 694: ...locations avail able to be written Master transfer error MERR 0 No errors have been detected 1 A master error has occurred The conditions surrounding the error are indicated by the master status register TWI_MASTER_STAT Master transfer complete MCOMP 0 The completion of a transfer has not been detected 1 The initiated master transfer has completed In the absence of a repeat start the bus has been ...

Page 695: ... during the data receive phase of a transfer Slave transfer complete SCOMP 0 The completion of a transfer has not been detected 1 The transfer is complete and either a stop or a restart was detected Slave transfer initiated SINIT 0 A transfer is not in progress An address match has not occurred since the last time this bit was cleared 1 The slave has detected an address match and a transfer has be...

Page 696: ...only one transmit data byte to the FIFO buffer With each access the transmit status XMTSTAT field in the TWI_FIFO_STAT regis ter is updated If an access is performed while the FIFO buffer is full the write is ignored and the existing FIFO buffer data and its status remains unchanged Figure 16 26 TWI FIFO Transmit Data Single Byte Register 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0...

Page 697: ...te 0 is the first byte to be transferred and byte 1 is the second byte to be transferred With each access the transmit status XMTSTAT field in the TWI_FIFO_STAT register is updated If an access is performed while the FIFO buffer is not empty the write is ignored and the existing FIFO buf fer data and its status remains unchanged Figure 16 27 Transmit Little Endian Byte Order Figure 16 28 TWI FIFO ...

Page 698: ...FO Receive Data Double Byte Register TWI_RCV_DATA16 The TWI_RCV_DATA16 register holds a 16 bit data value read from the FIFO buffer To reduce interrupt output rates and peripheral bus access times a double byte receive data access can be performed Two data bytes can be read effectively emptying the receive FIFO buffer with a single access The data is read in little endian byte order as shown in Fi...

Page 699: ...ta and its status remains unchanged Figure 16 30 Receive Little Endian Byte Order Figure 16 31 TWI FIFO Receive Data Double Byte Register RECEIVE DATA REGISTER B1 B0 TRANSMISSION LINE B1 B0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TWI FIFO Receive Data Double Byte Register TWI_RCV_DATA16 All bits are WO RCVDATA16 15 0 Receive FIFO 16 Bit Data Reset 0x0000 ...

Page 700: ...initiate polled receive and transmit transfers in master mode Listing 16 1 Master Mode Receive Transmit Transfer Macro for the count field of the TWI_MASTER_CTL register x can be any value between 0 and 0xFE 254 A value of 0xFF disables the counter define TWICount x DCNT x 6 section L1_data_b byte TX_file file_size DATA hex BYTE RX_CHECK file_size byte rcvFirstWord 2 SECTION program _main TWI Mast...

Page 701: ...internal time reference of 10 MHz period 100 ns CLKDIV 2500 ns 100 ns 25 For an SCL with a 30 duty cycle then CLKLOW 17 0x11 and CLKHI 8 R5 CLKHI 0x8 CLKLOW 0x11 z W P1 LO TWI_CLKDIV R5 enable these signals to generate a TWI interrupt optional R1 RCVSERV XMTSERV MERR MCOMP z W P1 LO TWI_INT_MASK R1 The address needs to be shifted one place to the right for example 1010 001x becomes 0101 0001 0x51 ...

Page 702: ...eated Start RESTART optional 3 speed mode FAST or SLOW 4 direction of transfer MDIR 1 for reads MDIR 0 for writes 5 Master Enable MEN This will kick off the master transfer R1 TWICount 0x2 FAST MDIR MEN W P1 LO TWI_MASTER_CTL R1 ssync Poll the FIFO Status register to know when 2 bytes have been shifted into the RX FIFO Rx_stat R1 W P1 LO TWI_FIFO_STAT Z R0 0xC R1 R1 R0 CC R1 R0 IF cc jump Rx_stat ...

Page 703: ...ith the first two bytes this is necessary to avoid the generation of the Buffer Read Error BUFRDERR which occurs whenever a transmit transfer is initiated while the transmit buffer is empty R3 W P2 Z W P1 LO TWI_XMT_DATA16 R3 Initiating the Write operation Program the Master Control register with 1 the number of bytes to transfer TWICount x 2 Repeated Start RESTART optional 3 speed mode FAST or St...

Page 704: ... byte location empty in the tx fifo XMTSERV_Status R1 W P1 LO TWI_INT_STAT z CC BITTST R1 bitpos XMTSERV test XMTSERV bit if CC jump XMTSERV_Status W P1 LO TWI_INT_STAT R1 clear status SSYNC write byte into the transmit FIFO R3 B P2 Z W P1 LO TWI_XMT_DATA8 R3 Loop_End1 SSYNC check that master transfer has completed M_COMP1 R1 W P1 LO TWI_INT_STAT z CC BITTST R1 bitpos MCOMP1 if CC jump M_COMP M_CO...

Page 705: ...the subroutine _TWI_ISR shown in Listing 16 3 Listing 16 2 Slave Mode Setup include defBF527 h BF527 is used here as an example change as appropriate include startup h define file_size 254 define SYSMMR_BASE 0xFFC00000 define COREMMR_BASE 0xFFE00000 GLOBAL _main EXTERN _TWI_ISR section L1_data_b BYTE TWI_RX file_size BYTE TWI_TX file_size transmit dat section L1_code _main TWI Slave Initialization...

Page 706: ...TROL R1 Slave address program the address to which this slave will respond to this is an arbitrary 7 bit value R1 0x5F W P1 LO TWI_SLAVE_ADDR R1 Pre load the TX FIFO with the first two bytes to be transmitted in the event the slave is addressed and a transmit is required R3 0xB537 Z W P1 LO TWI_XMT_DATA16 R3 FIFO Control determines whether an interrupt is generated for every byte transferred or fo...

Page 707: ...t data valid STDVAL set so that the contents of the TX FIFO can be used by this slave when a master requests data from it 2 Slave Enable SEN to enable Slave functionality R1 STDVAL SEN W P1 LO TWI_SLAVE_CTL R1 TWI_SLAVE_INIT END P2 H HI TWI_RX P2 L LO TWI_RX P4 H HI TWI_TX P4 L LO TWI_TX Remap the vector table pointer from the default __I10HANDLER to the new _TWI_ISR interrupt service routine R1 H...

Page 708: ...S EVT_IVG10 P0 LO IMASK R1 wait for interrupts idle _main END Listing 16 3 TWI Slave Interrupt Service Routine Function _ TWI_ISR Description This ISR is executed when the TWI controller detects a slave initiated transfer After an interrupt is ser viced its corresponding bit is cleared in the TWI_INT_STAT register This done by writing a 1 to the particular bit posi tion All bits are write 1 to cle...

Page 709: ...sfer Initiated CC BITTST R1 BITPOS SINIT if CC JUMP RECEIVE R0 SINIT Z W P1 LO TWI_INT_STAT R0 clear interrupt source bit ssync Receive service RECEIVE CC BITTST R1 BITPOS RCVSERV if CC JUMP TRANSMIT R0 W P1 LO TWI_RCV_DATA8 Z read data B P2 R0 store bytes into a buffer pointed to by P2 R0 RCVSERV Z W P1 LO TWI_INT_STAT R0 clear interrupt source bit ssync JUMP _TWI_ISR END exit Transmit service ...

Page 710: ...0 clear interrupt source bit ssync JUMP _TWI_ISR END exit slave transfer error SlaveError CC BITTST R1 BITPOS SERR if CC JUMP SlaveOverflow R0 SERR Z W P1 LO TWI_INT_STAT R0 clear interrupt source bit ssync JUMP _TWI_ISR END exit slave overflow SlaveOverflow CC BITTST R1 BITPOS SOVF if CC JUMP SlaveTransferComplete R0 SOVF Z W P1 LO TWI_INT_STAT R0 clear interrupt source bit ssync JUMP _TWI_ISR EN...

Page 711: ...uffer and set clear sema phores etc R0 W P1 LO TWI_FIFO_STAT z CC BITTST R0 BITPOS RCV_HALF BIT 2 indicates whether there s a byte in the FIFO or not if CC JUMP _TWI_ISR END R0 W P1 LO TWI_RCV_DATA8 Z read data B P2 R0 store bytes into a buffer pointed to by P2 _TWI_ISR END RTI Electrical Specifications All logic complies with the Electrical Specification outlined in the Philips I2C Bus Specificat...

Page 712: ...Unique Information for the ADSP BF50x Processor 16 62 ADSP BF50x Blackfin Processor Hardware Reference ...

Page 713: ...ng examples Familiarity with the CAN stan dard is assumed Refer to Version 2 0 of CAN Specification from Robert Bosch GmbH This chapter contains Overview Interface Overview on page 17 2 CAN Operation on page 17 9 Functional Operation on page 17 22 CAN Register Definitions on page 17 39 Programming Examples on page 17 85 Overview Key features of the CAN module are Conforms to the CAN 2 0B active st...

Page 714: ...message error tracking and fault node confinement as means to improve network reliability to the level required for control applications Interface Overview The interface to the CAN bus is a simple two wire line See Figure 17 1 for a symbolic representation of the CAN transceiver interconnection and Figure 17 2 for a block diagram The Blackfin processor s CANTX output and CANRX input pins are conne...

Page 715: ...SAGE IDENTIFICATION DATA LENGTH MAILBOX 2 MAILBOX 1 MAILBOX CONTROL 1 TRANSMIT MAILBOX INTERRUPT TRANSMIT 1 MAILBOX INTERRUPT MASK 1 RECEIVE MESSAGE LOST 1 REMOTE FRAME HANDLING 1 OVERWRITE PROTECTION SINGLE SHOT 1 MAILBOX INTERRUPT RECEIVE 1 TRANSMIT REQUEST RESET 1 RECEIVE MESSAGE PENDING 1 MAILBOX DIRECTION 1 TRANSMIT ACKNOWLEDGE 1 ABORT ACKNOWLEDGE 1 TRANSMIT REQUEST SET 1 MAILBOX ENABLE 1 INT...

Page 716: ...n direction Accordingly the CAN module architecture is based around a 32 entry mailbox RAM The mailbox is accessed sequentially by the CAN serial interface or the Black fin core Each mailbox consists of eight 16 bit control and data registers and two optional 16 bit acceptance mask registers all of which must be configured before the mailbox itself is enabled Since the mailbox area is implemented ...

Page 717: ... data field sent MSB first from the CAN_MBxx_DATA3 2 1 0 registers respectively based on the number of bytes defined in the DLC For example if only one byte is transmitted or received DLC 1 then it is stored in the most significant byte of the CAN_MBxx_DATA3 register Two bytes for the time stamp value TSV in the CAN_MBxx_TIMESTAMP register Figure 17 3 CAN Mailbox Area FDF EXTID_HI DFC AME EXTID_HI...

Page 718: ...sters for the 32 mailboxes Each bit in these registers represents one specific mailbox Since CAN MMRs are all 16 bits wide pairs of registers are required to manage certain functionality for all 32 individual mailboxes Mailboxes 0 15 are configured monitored in registers with a suffix of 1 Similarly mailboxes 16 31 use the same named register with a suffix of 2 For exam ple the CAN mailbox directi...

Page 719: ...k registers CAN_MBTIF1 and CAN_MBTIF2 mailbox transmit interrupt flag registers CAN_MBRIF1 and CAN_MBRIF2 mailbox receive interrupt flag registers Since mailboxes 24 31 support transmit operation only and mailboxes 0 7 are receive only mailboxes the lower eight bits in the 1 registers and the upper eight bits in the 2 registers are sometimes reserved or are restricted in their usage CAN Protocol B...

Page 720: ...e sensed on CANRX is the value driven on CANTX transmission continues oth erwise the CAN controller senses that it has lost arbitration and configuration determines what the next course of action is once arbitra tion is lost See Figure 17 5 for more details regarding CAN frame structure Figure 17 5 is a basic 11 bit identifier frame After the SOF and identifier is the RTR bit which indicates wheth...

Page 721: ...t bit in the IDE field wins arbitration against an extended frame with the same lower 11 bits therefore standard frames are higher priority than extended frames The substitute remote request bit SRR always sent as recessive the reserved bits r0 and r1 always sent as dominant and the checksum CRC are generated automatically by the internal logic CAN Operation The CAN controller is in configuration ...

Page 722: ...ls the nominal bit time and the sample point of the individual bits in the CAN protocol Figure 17 7 shows the three phases of a CAN bit the synchronization segment the segment before the sample point and the segment after the sample point The synchronization segment is fixed to one TQ It is required to syn chronize the nodes on the bus All signal edges are expected to occur within this segment The...

Page 723: ...ch a re synchronization attempt The SJW value should not exceed TSEG2 or TSEG1 Therefore the fundamental rule for writing CAN_TIMING is SJW TSEG2 TSEG1 In addition to this fundamental rule phase segment 2 must also be greater than or equal to the Information Processing Time IPT This is the time required by the logic to sample CANRX input On the Blackfin CAN mod ule this is 3 SCLK cycles Because of...

Page 724: ...he module does not receive transmit messages or error frames After leaving the configuration mode all CAN core internal registers and the CAN error counters are set to their initial values A software reset does not change the values of CAN_CLOCK and CAN_TIMING Thus an ongoing transfer via the CAN bus cannot be corrupted by chang ing the bit timing parameter or initiating the software reset SRS 1 i...

Page 725: ...sible for receive transmit mail boxes if the automatic remote frame handling feature is enabled RFHn 1 in CAN_RFHx Special care should be given to mailbox area management when a TRSn bit is set Write access to the mailbox is permissible with TRSn set but chang ing data in such a mailbox may lead to unexpected data during transmission Enabling and disabling mailboxes has an impact on transmit reque...

Page 726: ...tion on the CAN bus line is lost or there is an error frame on the CAN bus line Single Shot Transmission If the single shot transmission feature is used OPSSn 1 in CAN_OPSSx the corresponding TRSn bit is cleared after the message is successfully sent or if the transmission is aborted due to a lost arbitration or an error frame on Figure 17 8 CAN Transmit Operation Flow Chart AT LEAST 1 BIT SET IN ...

Page 727: ...is then reloaded from CAN_UCRC Each time the counter reaches a value of 0 the TRS11 bit is automatically set by internal logic and the corresponding message from mailbox 11 is sent For proper auto transmit operation mailbox 11 must be configured as a transmit mailbox and must contain valid data identifier control bits and data before the counter first expires after this mode is enabled Receive Ope...

Page 728: ...means that the bit does not need to match when AME 1 This way a mailbox can accept a group of messages If the acceptance filter finds a matching identifier the content of the received data frame is stored in that mailbox A received message is stored only once even if multiple receive mailboxes match its identifier If the current identifier does not match any mailbox the message is not stored Table...

Page 729: ...rwritten or not If OPSSn 0 the receive message lost bit RMLn in CAN_RMLx is set and the stored message is overwritten This Figure 17 9 CAN Receive Operation Flow Chart MAILBOX ENABLED AME Y FROM MESSAGE RECEIVER PREVIOUS MAILBOX 0 COMPARE ALL BITS MATCH Y N EXIT NEXT MAILBOX N 1 COMPARE UNMASKED BITS ONLY NEXT MAILBOX MAILBOX DIRECTION RECEIVE MAILBOX READY TRANSMIT REMOTE MAILBOX N NEXT MAILBOX Y...

Page 730: ...N_CONTROL and the mailbox is set up for filtering on data field the filtering is done on the standard ID of the message and data fields The data field filtering can be programmed for either the first byte only or the first two bytes as shown in Table 17 2 If the FDF bit is set in the corresponding CAN_AMxxH register the CAN_AMxxL register holds the data field mask DFM 15 0 If the FDF bit is cleare...

Page 731: ...request RTR bit Only configurable mailboxes 8 23 can process remote frames but all mailboxes can receive and transmit remote frame requests When setup for automatic remote frame handling the CAN_OPSSx register has no effect All content of a mailbox is always overwritten by an incoming message If a remote frame is received the DLC of the corresponding mailbox is overwritten with the received value ...

Page 732: ... a watchdog interrupt occurs the UCEIF bit in the CAN_GIF register is also set The counter can be reloaded with the contents of CAN_UCRC or disabled by writing to the CAN_UCCNF register The time period it takes for the watchdog interrupt to occur is controlled by the value written into the CAN_UCRC register by the user Time Stamps To get an indication of the time of reception or the time of transm...

Page 733: ...IM register If the interrupt source is unmasked a bit in the global CAN interrupt flag register is also set UCEIF in the CAN_GIF register Temporarily Disabling Mailboxes If this mailbox is used for automatic remote frame handling the data field must be updated without losing an incoming remote request frame and without sending inconsistent data Therefore the CAN controller allows for temporary mai...

Page 734: ...he internal logic waits until the reception is complete or there is an error on the CAN bus to set TDA Once TDA is set the mailbox can then be completely disabled MCn 0 without the risk of losing an incoming frame The temporary disable request TDR bit must then be reset as soon as possible When TDA is set for a given mailbox only the data field of that mailbox can be updated Accesses to the contro...

Page 735: ...he corresponding trans mit interrupt flag is set MBTIFn 1 in CAN_MBTIFx after the message in mailbox n is sent correctly TAn 1 in CAN_TAx The TAn bits maintain state even after the corresponding mailbox n is disabled MCn 0 If the automatic remote frame handling feature is used the transmit interrupt flag is set after the requested data frame is sent from the mailbox If any MBTIFn bits are set in C...

Page 736: ...nterrupt latch should be cleared by a W1C opera tion to the corresponding bit of the CAN_GIS register This clears the related bits of both the CAN_GIS and CAN_GIF registers There are several interrupt events that can activate this GIRQ interrupt Access denied interrupt ADIM ADIS ADIF At least one access to the mailbox RAM occurred during a data update by internal logic External trigger output inte...

Page 737: ...ess to unimplemented address interrupt UIAIM UIAIS UIAIF There was a CPU access to an address which is not implemented in the controller module Wakeup interrupt WUIM WUIS WUIF The CAN module has left the sleep mode because of detected activ ity on the CAN bus line Bus Off interrupt BOIM BOIS BOIF The CAN module has entered the bus off state This interrupt source is active if the status of the CAN ...

Page 738: ...WTIS EWTIF The CAN transmit error counter TXECNT has reached the warning limit If the bit in CAN_GIS and CAN_GIF is reset and the error warning mode is still active this bit is not set again If the module leaves the error warning mode the bit in CAN_GIS and CAN_GIF remains set Event Counter For diagnostic functions it is possible to use the universal counter as an event counter The counter can be ...

Page 739: ...me a message is received without detected errors but not stored in a mailbox because the mailbox contains unread data RMLn is set UCCNF 3 0 0xD Message received Counter is incremented every time a message is received without detected errors whether the received message is rejected or stored in a mailbox UCCNF 3 0 0xE Message stored Counter is incremented every time a message is received without de...

Page 740: ...of bus errors may occur during transmissions Bit error A bit error can be detected by the transmitting node only When ever a node is transmitting it continuously monitors its receive pin CANRX and compares the received data with the transmitted data During the arbitration phase the node simply postpones the trans mission if the received and transmitted data do not match However after the arbitrati...

Page 741: ...e error counter register CAN_CEC In addition to the standard errors the CAN_ESR register features a flag that signals when the CANRX pin sticks at dominant level indicating that shorted wires are likely Error Frames It is of central importance that all nodes on the CAN bus ignore data frames that one single node failed to receive To accomplish this every node sends an error frame as soon as it has...

Page 742: ...rs the error frame is initiated at the end of the frame rather than immediately after the failing bit After having received 8 recessive bits every node knows that the error con dition has been resolved and starts transmission if messages are pending The former transmitter that had to abort its operation must win the new arbitration again otherwise its message is delayed as determined by priority F...

Page 743: ...mes of other nodes Error Levels The CAN specification requires each node in the system to operate in one of three levels See Table 17 3 This prevents nodes with high error rates from blocking the entire network as the errors might be caused by local hardware The Blackfin CAN module provides an error counter for trans mit TEC and an error counter for receive REC The CAN error count register CAN_CEC...

Page 744: ...warning level can be pro grammed using the error warning register CAN_EWR More information is available on page 17 84 Additionally interrupts can occur for all of these levels by unmasking them in the global CAN interrupt mask register CAN_GIM shown on page 17 47 The interrupts include the bus off interrupt BOIM the error passive interrupt EPIM the error warning receive interrupt EWRIM and the err...

Page 745: ...eatures that aid in the debugging of the CAN software and system Listing 17 1 provides an example of enabling CAN debug features When these features are used the CAN module may not be com pliant to the CAN specification All test modes should be enabled or disabled only when the module is in configuration mode CCA 1 in the CAN_STATUS register or in suspend mode CSA 1 in CAN_STATUS The CDE bit is us...

Page 746: ...mitted on the CAN bus or via an internal loop back mode is received back directly to the internal receive buffer After a correct transmission the internal logic treats this as a normal receive mes sage This feature allows the user to test most of the CAN features without an external device The mode auto acknowledge bit MAA allows the CAN module to generate its own acknowledge during the ACK slot o...

Page 747: ...nsmit and receive error counters in the CAN_CEC register When this bit is set the CAN_CEC holds its current contents and is not allowed to increment or dec rement the error counters This mode does not conform to the CAN specification Writes to the error counters should be in debug mode only Write access during reception may lead to undefined values The maxi mum value which can be written into the ...

Page 748: ...re transmitted on CAN bus line CANRX input and internal loop are enabled internal OR of TX and RX 1 1 0 0 1 1 Normal transmission on CAN bus line Read back No external acknowledge required Transmit message and acknowledge are transmitted on CAN bus line CANRX input is ignored Internal loop is enabled 1 1 0 1 1 1 No transmission on CAN bus line Read back No external acknowledge required Neither tra...

Page 749: ...ode is requested during the bus off recovery sequence the module stops after the bus off recovery sequence has completed The module does not enter the suspend mode and the CSA bit is not set Software must manually clear the CSR bit to restart the module Once this mode is entered the module is no longer active on the CAN bus line slightly reducing power consumption When the CAN module is in suspend...

Page 750: ...ep mode a dominant bit on the CANRX pin also ends sleep mode CAN Wakeup From Hibernate State For greatest power savings the Blackfin processor provides a hibernate state where the internal voltage regulator shuts off the internal power sup ply to the chip turning off the core and system clocks in the process In this mode the only power drawn roughly 50 A is that used by the regulator circuitry awa...

Page 751: ...it CANWE set and the HIBERNATEB bit set to 0 CAN Register Definitions The following sections describe the CAN register definitions Global CAN Registers on page 17 43 Mailbox Mask Registers on page 17 48 Mailbox Control Registers on page 17 68 Universal Counter Registers on page 17 82 Error Registers on page 17 84 Table 17 5 through Table 17 9 show the functions of the CAN registers Table 17 5 Glob...

Page 752: ... Global CAN interrupt flag register Bits 15 11 are reserved Table 17 6 CAN Mailbox Mask Register Mapping Register Name Function Notes CAN_AMxxH L Acceptance mask registers Change only when mailbox MBxx is dis abled CAN_MBxx_ID1 0 Mailbox word 7 6 register Do not write when MBxx is enabled CAN_MBxx_TIMESTAMP Mailbox word 5 register Holds timestamp information when time stamp mode is active CAN_MBxx...

Page 753: ...Do not modify OPSSn bit if mailbox n is enabled CAN_TRSx Transmission request set registers May by set by internal logic under certain cir cumstances TRS 7 0 are read only CAN_TRRx Transmission request reset regis ters TRRn bits must not be set if mailbox n is dis abled or TRSn 0 CAN_AAx Abort acknowledge registers AAn bit is reset if TRSn bit is set manually but not when TRSn is set by internal l...

Page 754: ...AN_UCCNF Universal counter mode register Bits 15 8 and bit 4 are reserved CAN_UCCNT Universal counter register Counts up or down based on universal counter mode CAN_UCRC Universal counter reload capture reg ister In timestamp mode holds time of last success ful transmit or receive Table 17 9 CAN Error Register Mapping Register Name Function Notes CAN_CEC CAN error counter register Undefined while ...

Page 755: ...t 0x0080 0xFFC0 2AA0 DNM DeviceNet Mode 0 Disable 1 Enable ABO Auto Bus On CCR CAN Configuration Mode Request 0 Cancelled 1 Requested CSR CAN Suspend Mode Request 0 Cancelled 1 Requested SMR Sleep Mode Request 0 Not requested 1 Enters Sleep mode WBA Wake Up on CAN Bus Activity 0 Stays in Sleep mode 1 Can leave Sleep mode 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 Enter...

Page 756: ...obal CAN Status Register CAN_STATUS RO WT CAN Transmit Warning Flag 0 TXECNT below limit 1 TXECNT at limit Reset 0x0000 0xFFC0 2A8C WR CAN Receive Warning Flag 0 RXECNT below limit 1 RXECNT at limit EP CAN Error Passive Mode 0 Both TXECNT and RXECNT 128 1 TXECNT or RXECNT error passive level EBO CAN Error Bus Off Mode 0 TXECNT 256 1 TXECNT bus off limit REC Receive Mode 0 Not in receive mode 1 In ...

Page 757: ...Input Pin CANRX 0 Enable CANRX input pin 1 Disable CANRX input pin drive recessive internally DTO Disable Transmit Out put Pin CANTX 0 Enable CANTX output pin 1 Disable CANTX output pin drive recessive CDE CAN Debug Mode Enable 0 Debug mode disabled 1 Debug mode enabled MRB Mode Read Back 0 Read back mode disabled 1 Read back mode enabled MAA Mode Auto Acknowledge 0 Auto acknowledge mode disabled ...

Page 758: ...ceive flags set 1 One or more receive flags set Reset 0x00X0 X depen dent on pin values 0xFFC0 2AA4 MBTIRQ Mailbox Transmit Interrupt Output 0 No transmit flags set 1 One or more transmit flags set GIRQ Global CAN Interrupt Output 0 No global CAN flags set 1 One or more global CAN flags set CANRX Serial Input From Transceiver RO Serial input from CAN bus line from transceiver 0 Value is dominant 1...

Page 759: ...unter Exceeded Interrupt Mask RMLIM Receive Message Lost Interrupt Mask AAIM Abort Acknowledge Interrupt Mask WUIM Wakeup Interrupt Mask UIAIM Unimplemented Address Interrupt Mask 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Global CAN Interrupt Status Register CAN_GIS All bits are W1C EWTIS Error Warning Transmit Interrupt Status Reset 0x0000 0xFFC0 2A94 EWRIS Error Warni...

Page 760: ... EWRIF Error Warning Receive Interrupt Flag EPIF Error Passive Interrupt Flag BOIF Bus Off Interrupt Flag ADIF Access Denied Interrupt Flag EXTIF External Trigger Interrupt Flag UCEIF Universal Counter Exceeded Interrupt Flag RMLIF Receive Message Lost Interrupt Flag AAIF Abort Acknowledge Interrupt Flag WUIF Wakeup Interrupt Flag UIAIF Unimplemented Address Interrupt Flag 15 14 13 12 11 10 9 8 7 ...

Page 761: ...k Register H Memory Mapped Addresses Register Name Memory Mapped Address CAN_AM00H 0xFFC0 2B04 CAN_AM01H 0xFFC0 2B0C CAN_AM02H 0xFFC0 2B14 CAN_AM03H 0xFFC0 2B1C CAN_AM04H 0xFFC0 2B24 CAN_AM05H 0xFFC0 2B2C CAN_AM06H 0xFFC0 2B34 CAN_AM07H 0xFFC0 2B3C CAN_AM08H 0xFFC0 2B44 CAN_AM09H 0xFFC0 2B4C CAN_AM10H 0xFFC0 2B54 CAN_AM11H 0xFFC0 2B5C CAN_AM12H 0xFFC0 2B64 CAN_AM13H 0xFFC0 2B6C CAN_AM14H 0xFFC0 2B...

Page 762: ...gure 17 21 Acceptance Mask Register L Table 17 11 Acceptance Mask Register L Memory Mapped Addresses Register Name Memory Mapped Address CAN_AM00L 0xFFC0 2B00 CAN_AM01L 0xFFC0 2B08 CAN_AM02L 0xFFC0 2B10 Table 17 10 Acceptance Mask Register H Memory Mapped Addresses Cont d Register Name Memory Mapped Address 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 X X X X X X X X X X X X X X X X Acceptance Mask Regis...

Page 763: ...B58 CAN_AM12L 0xFFC0 2B60 CAN_AM13L 0xFFC0 2B68 CAN_AM14L 0xFFC0 2B70 CAN_AM15L 0xFFC0 2B78 CAN_AM16L 0xFFC0 2B80 CAN_AM17L 0xFFC0 2B88 CAN_AM18L 0xFFC0 2B90 CAN_AM19L 0xFFC0 2B98 CAN_AM20L 0xFFC0 2BA0 CAN_AM21L 0xFFC0 2BA8 CAN_AM22L 0xFFC0 2BB0 CAN_AM23L 0xFFC0 2BB8 CAN_AM24L 0xFFC0 2BC0 CAN_AM25L 0xFFC0 2BC8 CAN_AM26L 0xFFC0 2BD0 CAN_AM27L 0xFFC0 2BD8 Table 17 11 Acceptance Mask Register L Memor...

Page 764: ...01_ID1 0xFFC0 2C3C CAN_MB02_ID1 0xFFC0 2C5C CAN_MB03_ID1 0xFFC0 2C7C CAN_MB04_ID1 0xFFC0 2C9C CAN_MB05_ID1 0xFFC0 2CBC CAN_MB06_ID1 0xFFC0 2CDC Table 17 11 Acceptance Mask Register L Memory Mapped Addresses Cont d Register Name Memory Mapped Address 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 X X X X X X X X X X X X X X X X Mailbox Word 7 Register CAN_MBxx_ID1 EXTID 17 16 Extended Identifier Reset 0xXXX...

Page 765: ...B16_ID1 0xFFC0 2E1C CAN_MB17_ID1 0xFFC0 2E3C CAN_MB18_ID1 0xFFC0 2E5C CAN_MB19_ID1 0xFFC0 2E7C CAN_MB20_ID1 0xFFC0 2E9C CAN_MB21_ID1 0xFFC0 2EBC CAN_MB22_ID1 0xFFC0 2EDC CAN_MB23_ID1 0xFFC0 2EFC CAN_MB24_ID1 0xFFC0 2F1C CAN_MB25_ID1 0xFFC0 2F3C CAN_MB26_ID1 0xFFC0 2F5C CAN_MB27_ID1 0xFFC0 2F7C CAN_MB28_ID1 0xFFC0 2F9C CAN_MB29_ID1 0xFFC0 2FBC CAN_MB30_ID1 0xFFC0 2FDC CAN_MB31_ID1 0xFFC0 2FFC Table...

Page 766: ...C78 CAN_MB04_ID0 0xFFC0 2C98 CAN_MB05_ID0 0xFFC0 2CB8 CAN_MB06_ID0 0xFFC0 2CD8 CAN_MB07_ID0 0xFFC0 2CF8 CAN_MB08_ID0 0xFFC0 2D18 CAN_MB09_ID0 0xFFC0 2D38 CAN_MB10_ID0 0xFFC0 2D58 CAN_MB11_ID0 0xFFC0 2D78 CAN_MB12_ID0 0xFFC0 2D98 CAN_MB13_ID0 0xFFC0 2DB8 CAN_MB14_ID0 0xFFC0 2DD8 CAN_MB15_ID0 0xFFC0 2DF8 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 X X X X X X X X X X X X X X X X Mailbox Word 6 Register CA...

Page 767: ...C0 2E98 CAN_MB21_ID0 0xFFC0 2EB8 CAN_MB22_ID0 0xFFC0 2ED8 CAN_MB23_ID0 0xFFC0 2EF8 CAN_MB24_ID0 0xFFC0 2F18 CAN_MB25_ID0 0xFFC0 2F38 CAN_MB26_ID0 0xFFC0 2F58 CAN_MB27_ID0 0xFFC0 2F78 CAN_MB28_ID0 0xFFC0 2F98 CAN_MB29_ID0 0xFFC0 2FB8 CAN_MB30_ID0 0xFFC0 2FD8 CAN_MB31_ID0 0xFFC0 2FF8 Table 17 13 Mailbox Word 6 Register Memory Mapped Addresses Cont d Register Name Memory Mapped Address ...

Page 768: ...P 0xFFC0 2C94 CAN_MB05_TIMESTAMP 0xFFC0 2CB4 CAN_MB06_TIMESTAMP 0xFFC0 2CD4 CAN_MB07_TIMESTAMP 0xFFC0 2CF4 CAN_MB08_TIMESTAMP 0xFFC0 2D14 CAN_MB09_TIMESTAMP 0xFFC0 2D34 CAN_MB10_TIMESTAMP 0xFFC0 2D54 CAN_MB11_TIMESTAMP 0xFFC0 2D74 CAN_MB12_TIMESTAMP 0xFFC0 2D94 CAN_MB13_TIMESTAMP 0xFFC0 2DB4 CAN_MB14_TIMESTAMP 0xFFC0 2DD4 CAN_MB15_TIMESTAMP 0xFFC0 2DF4 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 X X X X...

Page 769: ...IMESTAMP 0xFFC0 2EB4 CAN_MB22_TIMESTAMP 0xFFC0 2ED4 CAN_MB23_TIMESTAMP 0xFFC0 2EF4 CAN_MB24_TIMESTAMP 0xFFC0 2F14 CAN_MB25_TIMESTAMP 0xFFC0 2F34 CAN_MB26_TIMESTAMP 0xFFC0 2F54 CAN_MB27_TIMESTAMP 0xFFC0 2F74 CAN_MB28_TIMESTAMP 0xFFC0 2F94 CAN_MB29_TIMESTAMP 0xFFC0 2FB4 CAN_MB30_TIMESTAMP 0xFFC0 2FD4 CAN_MB31_TIMESTAMP 0xFFC0 2FF4 Table 17 14 Mailbox Word 5 Register Memory Mapped Addresses Cont d Re...

Page 770: ...AN_MB04_LENGTH 0xFFC0 2C90 CAN_MB05_LENGTH 0xFFC0 2CB0 CAN_MB06_LENGTH 0xFFC0 2CD0 CAN_MB07_LENGTH 0xFFC0 2CF0 CAN_MB08_LENGTH 0xFFC0 2D10 CAN_MB09_LENGTH 0xFFC0 2D30 CAN_MB10_LENGTH 0xFFC0 2D50 CAN_MB11_LENGTH 0xFFC0 2D70 CAN_MB12_LENGTH 0xFFC0 2D90 CAN_MB13_LENGTH 0xFFC0 2DB0 CAN_MB14_LENGTH 0xFFC0 2DD0 CAN_MB15_LENGTH 0xFFC0 2DF0 CAN_MB16_LENGTH 0xFFC0 2E10 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0...

Page 771: ...H 0xFFC0 2F30 CAN_MB26_LENGTH 0xFFC0 2F50 CAN_MB27_LENGTH 0xFFC0 2F70 CAN_MB28_LENGTH 0xFFC0 2F90 CAN_MB29_LENGTH 0xFFC0 2FB0 CAN_MB30_LENGTH 0xFFC0 2FD0 CAN_MB31_LENGTH 0xFFC0 2FF0 Figure 17 26 Mailbox Word 3 Register Table 17 15 Mailbox Word 4 Register Memory Mapped Addresses Cont d Register Name Memory Mapped Address 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 X X X X X X X X X X X X X X X X Mailbox ...

Page 772: ...3 0xFFC0 2CAC CAN_MB06_DATA3 0xFFC0 2CCC CAN_MB07_DATA3 0xFFC0 2CEC CAN_MB08_DATA3 0xFFC0 2D0C CAN_MB09_DATA3 0xFFC0 2D2C CAN_MB10_DATA3 0xFFC0 2D4C CAN_MB11_DATA3 0xFFC0 2D6C CAN_MB12_DATA3 0xFFC0 2D8C CAN_MB13_DATA3 0xFFC0 2DAC CAN_MB14_DATA3 0xFFC0 2DCC CAN_MB15_DATA3 0xFFC0 2DEC CAN_MB16_DATA3 0xFFC0 2E0C CAN_MB17_DATA3 0xFFC0 2E2C CAN_MB18_DATA3 0xFFC0 2E4C CAN_MB19_DATA3 0xFFC0 2E6C CAN_MB20...

Page 773: ...A3 0xFFC0 2F2C CAN_MB26_DATA3 0xFFC0 2F4C CAN_MB27_DATA3 0xFFC0 2F6C CAN_MB28_DATA3 0xFFC0 2F8C CAN_MB29_DATA3 0xFFC0 2FAC CAN_MB30_DATA3 0xFFC0 2FCC CAN_MB31_DATA3 0xFFC0 2FEC Table 17 16 Mailbox Word 3 Register Memory Mapped Addresses Cont d Register Name Memory Mapped Address ...

Page 774: ...B05_DATA2 0xFFC0 2CA8 CAN_MB06_DATA2 0xFFC0 2CC8 CAN_MB07_DATA2 0xFFC0 2CE8 CAN_MB08_DATA2 0xFFC0 2D08 CAN_MB09_DATA2 0xFFC0 2D28 CAN_MB10_DATA2 0xFFC0 2D48 CAN_MB11_DATA2 0xFFC0 2D68 CAN_MB12_DATA2 0xFFC0 2D88 CAN_MB13_DATA2 0xFFC0 2DA8 CAN_MB14_DATA2 0xFFC0 2DC8 CAN_MB15_DATA2 0xFFC0 2DE8 CAN_MB16_DATA2 0xFFC0 2E08 CAN_MB17_DATA2 0xFFC0 2E28 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 X X X X X X X X ...

Page 775: ...8 CAN_MB22_DATA2 0xFFC0 2EC8 CAN_MB23_DATA2 0xFFC0 2EE8 CAN_MB24_DATA2 0xFFC0 2F08 CAN_MB25_DATA2 0xFFC0 2F28 CAN_MB26_DATA2 0xFFC0 2F48 CAN_MB27_DATA2 0xFFC0 2F68 CAN_MB28_DATA2 0xFFC0 2F88 CAN_MB29_DATA2 0xFFC0 2FA8 CAN_MB30_DATA2 0xFFC0 2FC8 CAN_MB31_DATA2 0xFFC0 2FE8 Table 17 17 Mailbox Word 2 Register Memory Mapped Addresses Cont d Register Name Memory Mapped Address ...

Page 776: ...B05_DATA1 0xFFC0 2CA4 CAN_MB06_DATA1 0xFFC0 2CC4 CAN_MB07_DATA1 0xFFC0 2CE4 CAN_MB08_DATA1 0xFFC0 2D04 CAN_MB09_DATA1 0xFFC0 2D24 CAN_MB10_DATA1 0xFFC0 2D44 CAN_MB11_DATA1 0xFFC0 2D64 CAN_MB12_DATA1 0xFFC0 2D84 CAN_MB13_DATA1 0xFFC0 2DA4 CAN_MB14_DATA1 0xFFC0 2DC4 CAN_MB15_DATA1 0xFFC0 2DE4 CAN_MB16_DATA1 0xFFC0 2E04 CAN_MB17_DATA1 0xFFC0 2E24 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 X X X X X X X X ...

Page 777: ...4 CAN_MB22_DATA1 0xFFC0 2EC4 CAN_MB23_DATA1 0xFFC0 2EE4 CAN_MB24_DATA1 0xFFC0 2F04 CAN_MB25_DATA1 0xFFC0 2F24 CAN_MB26_DATA1 0xFFC0 2F44 CAN_MB27_DATA1 0xFFC0 2F64 CAN_MB28_DATA1 0xFFC0 2F84 CAN_MB29_DATA1 0xFFC0 2FA4 CAN_MB30_DATA1 0xFFC0 2FC4 CAN_MB31_DATA1 0xFFC0 2FE4 Table 17 18 Mailbox Word 1 Register Memory Mapped Addresses Cont d Register Name Memory Mapped Address ...

Page 778: ...B05_DATA0 0xFFC0 2CA0 CAN_MB06_DATA0 0xFFC0 2CC0 CAN_MB07_DATA0 0xFFC0 2CE0 CAN_MB08_DATA0 0xFFC0 2D00 CAN_MB09_DATA0 0xFFC0 2D20 CAN_MB10_DATA0 0xFFC0 2D40 CAN_MB11_DATA0 0xFFC0 2D60 CAN_MB12_DATA0 0xFFC0 2D80 CAN_MB13_DATA0 0xFFC0 2DA0 CAN_MB14_DATA0 0xFFC0 2DC0 CAN_MB15_DATA0 0xFFC0 2DE0 CAN_MB16_DATA0 0xFFC0 2E00 CAN_MB17_DATA0 0xFFC0 2E20 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 X X X X X X X X ...

Page 779: ...0 CAN_MB22_DATA0 0xFFC0 2EC0 CAN_MB23_DATA0 0xFFC0 2EE0 CAN_MB24_DATA0 0xFFC0 2F00 CAN_MB25_DATA0 0xFFC0 2F20 CAN_MB26_DATA0 0xFFC0 2F40 CAN_MB27_DATA0 0xFFC0 2F60 CAN_MB28_DATA0 0xFFC0 2F80 CAN_MB29_DATA0 0xFFC0 2FA0 CAN_MB30_DATA0 0xFFC0 2FC0 CAN_MB31_DATA0 0xFFC0 2FE0 Table 17 19 Mailbox Word 0 Register Memory Mapped Addresses Cont d Register Name Memory Mapped Address ...

Page 780: ... 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Mailbox Configuration Register 1 CAN_MC1 MC0 MC12 MC13 MC14 MC15 MC1 MC2 MC3 MC4 MC5 For all bits 0 Mailbox disabled 1 Mailbox enabled MC6 MC7 MC11 MC10 MC9 MC8 Reset 0x0000 0xFFC0 2A00 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Mailbox Configuration Register 2 CAN_MC2 MC16 MC28 MC29 MC30 MC31 MC17 MC18 MC19 MC20 MC21 ...

Page 781: ...MD1 RO MD2 RO MD3 RO MD4 RO MD5 RO For all bits 0 Mailbox configured as transmit mode 1 Mailbox configured as receive mode MD6 RO MD7 RO MD11 MD10 MD9 MD8 Reset 0x00FF 0xFFC0 2A04 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Mailbox Direction Register 2 CAN_MD2 MD16 MD28 RO MD29 RO MD30 RO MD31 RO MD17 MD18 MD19 MD20 MD21 For all bits 0 Mailbox configured as transmit mode ...

Page 782: ... 0 0 0 0 Receive Message Pending Register 1 CAN_RMP1 RMP0 RMP12 RMP13 RMP14 RMP15 RMP1 RMP2 RMP3 RMP4 RMP5 All bits are W1C RMP6 RMP7 RMP11 RMP10 RMP9 RMP8 Reset 0x0000 0xFFC0 2A18 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Receive Message Pending Register 2 CAN_RMP2 RMP16 RMP28 RO RMP29 RO RMP30 RO RMP31 RO RMP17 RMP18 RMP19 RMP20 RMP21 All bits are W1C RMP22 RMP23 RMP2...

Page 783: ...0 0 0 0 0 0 0 0 0 0 0 0 0 0 Receive Message Lost Register 1 CAN_RML1 RML0 RML12 RML13 RML14 RML15 RML1 RML2 RML3 RML4 RML5 RO RML6 RML7 RML11 RML10 RML9 RML8 Reset 0x0000 0xFFC0 2A1C 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Receive Message Lost Register 2 CAN_RML2 RML16 RML28 RML29 RML30 RML31 RML17 RML18 RML19 RML20 RML21 RO RML22 RML23 RML27 RML26 RML25 RML24 Reset 0...

Page 784: ...0 0 0 0 0 0 0 0 0 0 0 Overwrite Protection Single Shot Transmission Register 1 CAN_OPSS1 OPSS0 OPSS12 OPSS13 OPSS14 OPSS15 OPSS1 OPSS2 OPSS3 OPSS4 OPSS5 OPSS6 OPSS7 OPSS11 OPSS10 OPSS9 OPSS8 Reset 0x0000 0xFFC0 2A30 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Overwrite Protection Single Shot Transmission Register 2 CAN_OPSS2 OPSS16 OPSS28 OPSS29 OPSS30 OPSS31 OPSS17 OPSS1...

Page 785: ...0 0 0 0 0 0 0 0 0 0 Transmission Request Set Register 1 CAN_TRS1 TRS0 RO TRS12 TRS13 TRS14 TRS15 TRS1 RO TRS2 RO TRS3 RO TRS4 RO TRS5 RO TRS6 RO TRS7 RO TRS11 TRS10 TRS9 TRS8 Reset 0x0000 0xFFC0 2A08 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Transmission Request Set Register 2 CAN_TRS2 TRS16 TRS28 TRS29 TRS30 TRS31 TRS17 TRS18 TRS19 TRS20 TRS21 TRS22 TRS23 TRS27 TRS26 T...

Page 786: ... 0 0 0 0 0 0 0 0 0 0 0 0 0 Transmission Request Reset Register 1 CAN_TRR1 TRR0 RO TRR12 TRR13 TRR14 TRR15 TRR1 RO TRR2 RO TRR3 RO TRR4 RO TRR5 RO TRR6 RO TRR7 RO TRR11 TRR10 TRR9 TRR8 Reset 0x0000 0xFFC0 2A0C 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Transmission Request Reset Register 2 CAN_TRR2 TRR16 TRR28 TRR29 TRR30 TRR31 TRR17 TRR18 TRR19 TRR20 TRR21 TRR22 TRR23 TR...

Page 787: ... 0 0 0 0 0 0 0 0 0 Abort Acknowledge Register 1 CAN_AA1 AA0 RO AA12 AA13 AA14 AA15 AA1 RO AA2 RO AA3 RO AA4 RO AA5 RO All bits are W1C AA6 RO AA7 RO AA11 AA10 AA9 AA8 Reset 0x0000 0xFFC0 2A14 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Abort Acknowledge Register 2 CAN_AA2 AA16 AA28 AA29 AA30 AA31 AA17 AA18 AA19 AA20 AA21 All bits are W1C AA22 AA23 AA27 AA26 AA25 AA24 Rese...

Page 788: ...0 0 0 0 0 0 0 0 0 0 0 0 0 Transmission Acknowledge Register 1 CAN_TA1 TA0 RO TA12 TA13 TA14 TA15 TA1 RO TA2 RO TA3 RO TA4 RO TA5 RO All bits are W1C TA6 RO TA7 RO TA11 TA10 TA9 TA8 Reset 0x0000 0xFFC0 2A10 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Transmission Acknowledge Register 2 CAN_TA2 TA16 TA28 TA29 TA30 TA31 TA17 TA18 TA19 TA20 TA21 All bits are W1C TA22 TA23 TA2...

Page 789: ... 0 0 0 0 0 0 0 0 0 0 0 Temporary Mailbox Disable Feature Register CAN_MBTD TDPTR 4 0 Temporary Disable Pointer Reset 0x0000 0xFFC0 2AAC TDA Temporary Disable Acknowledge TDR Temporary Disable Request 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Remote Frame Handling Register 1 CAN_RFH1 RFH0 RO RFH12 RFH13 RFH14 RFH15 RFH1 RO RFH2 RO RFH3 RO RFH4 RO RFH5 RO RFH6 RO RFH7 RO ...

Page 790: ... 0 0 0 0 0 0 0 0 0 Remote Frame Handling Register 2 CAN_RFH2 RFH16 RFH28 RO RFH29 RO RFH30 RO RFH31 RO RFH17 RFH18 RFH19 RFH20 RFH21 RFH22 RFH23 RFH27 RO RFH26 RO RFH25 RO RFH24 RO Reset 0x0000 0xFFC0 2A6C 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Mailbox Interrupt Mask Register 1 CAN_MBIM1 MBIM0 MBIM12 MBIM13 MBIM14 MBIM15 MBIM1 MBIM2 MBIM3 MBIM4 MBIM5 MBIM6 MBIM7 MBIM...

Page 791: ...rupt Mask Register 2 CAN_MBIM2 MBIM16 MBIM28 MBIM29 MBIM30 MBIM31 MBIM17 MBIM18 MBIM19 MBIM20 MBIM21 MBIM22 MBIM23 MBIM27 MBIM26 MBIM25 MBIM24 Reset 0x0000 0xFFC0 2A68 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Mailbox Transmit Interrupt Flag Register 1 CAN_MBTIF1 MBTIF0 RO MBTIF12 MBTIF13 MBTIF14 MBTIF15 MBTIF1 RO MBTIF2 RO MBTIF3 RO MBTIF4 RO MBTIF5 RO All bits are W1C...

Page 792: ...nsmit Interrupt Flag Register 2 CAN_MBTIF2 MBTIF16 MBTIF28 MBTIF29 MBTIF30 MBTIF31 MBTIF17 MBTIF18 MBTIF19 MBTIF20 MBTIF21 All bits are W1C MBTIF22 MBTIF23 MBTIF27 MBTIF26 MBTIF25 MBTIF24 Reset 0x0000 0xFFC0 2A60 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Mailbox Receive Interrupt Flag Register 1 CAN_MBRIF1 MBRIF0 MBRIF12 MBRIF13 MBRIF14 MBRIF15 MBRIF1 MBRIF2 MBRIF3 MBRI...

Page 793: ... 2 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Mailbox Receive Interrupt Flag Register 2 CAN_MBRIF2 MBRIF16 MBRIF28 RO MBRIF29 RO MBRIF30 RO MBRIF31 RO MBRIF17 MBRIF18 MBRIF19 MBRIF20 MBRIF21 All bits are W1C MBRIF22 MBRIF23 MBRIF27 RO MBRIF26 RO MBRIF25 RO MBRIF24 RO Reset 0x0000 0xFFC0 2A64 ...

Page 794: ...Trigger UCE Universal Counter Enable 0 No action 1 write 1 to reload counter in watchdog mode write 1 to clear counter in all other modes 0 No trigger 1 mailbox 4 reception reloads counter in watchdog mode mailbox 4 reception clears counter in time stamp mode no effect in other modes 0 Counter disabled 1 Counter enabled 0x0 Reserved 0x1 Time stamp mode 0x2 Watchdog mode 0x3 Auto transmit mode 0x4 ...

Page 795: ...e 17 59 Universal Counter Reload Capture Register 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Universal Counter Register CAN_UCCNT UCCNT 15 0 Reset 0x0000 0xFFC0 2AC4 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Universal Counter Reload Capture Register CAN_UCRC UCVAL 15 0 Reset 0x0000 0xFFC0 2AC8 ...

Page 796: ... 0 CAN Error Counter Register CAN_CEC RXECNT 7 0 Receive Error Counter Reset 0x0000 0xFFC0 2A90 TXECNT 7 0 Transmit Error Counter 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 Error Status Register CAN_ESR All bits are W1C ACKE Acknowledge Error Reset 0x0020 0xFFC0 2AB4 SER Stuff Bit Error CRCE CRC Error FER Form Error BEF Bit Error Flag SA0 Stuck at Dominant 15 14 13 12 11...

Page 797: ...appropriate header file is included in the source code that is include defBF537 h for ADSP BF537 projects CAN Setup Code The following code initializes the port pins to connect to the CAN con troller and configures the CAN timing parameters Listing 17 2 Initializing CAN Initialize_CAN P0 H HI PORT_MUX CAN pins muxed on Port J P0 L LO PORT_MUX R0 PJCE_CAN Z Enable CAN TX RX pins W P0 R0 SSYNC Set C...

Page 798: ...x 1 TSEG1 1 TSEG2 1 2us TQ x 1 4 1 3 1 2e 6 TQ x 1 5 4 TQ 2e 6 10 TQ 2e 7 Once time quantum TQ is known BRP can be derived from the TQ formula in the HRM Assume the default PLL settings are used for the ADSP BF537 EZ KIT which implies that System Clock SCLK is 50MHz TQ BRP 1 SCLK 2e 7 BRP 1 50e6 BRP 1 10 BRP 9 P0 L LO CAN_CLOCK R0 9 Z W P0 R0 SSYNC RTS Initializing and Enabling CAN Mailboxes Befor...

Page 799: ...e CAN Mailbox Area Mailbox 8 transmits ID 0x411 with 4 bytes of data Bytes 0 and 1 are a data pattern 0xAABB Bytes 2 and 3 will be a count value for the number of times that message is properly sent Mailbox 9 will receive message ID 0x007 Initialize Mailbox 8 For Transmit R0 0x411 2 Put Message ID in correct slot P0 L LO CAN_MB_ID1 8 Access MB08 ID1 Register W P0 R0 Remote frame disabled 11 bit ID...

Page 800: ...ed Mailboxes P0 L LO CAN_MC1 R0 W P0 Z BITSET R0 BITPOS MC8 Enable MB08 BITSET R0 BITPOS MC9 Enable MB09 W P0 R0 SSYNC RTS Initiating CAN Transfers and Processing Interrupts After the mailboxes are properly set up transfers can be requested in the CAN controller This code example initializes the CAN level interrupts takes the CAN controller out of configuration mode requests a transfer and then wa...

Page 801: ...CAN Configuration Mode Clear CCR P0 L LO CAN_CONTROL R0 W P0 Z BITCLR R0 BITPOS CCR W P0 R0 P0 L LO CAN_STATUS Wait for CAN Configuration Acknowledge CCA WAIT_FOR_CCA_TO_CLEAR R1 W P0 Z CC BITTST R1 BITPOS CCA IF CC JUMP WAIT_FOR_CCA_TO_CLEAR P0 L LO CAN_TRS1 R0 TRS8 Transmit Request MB08 W P0 R0 Issue Transmit Request SSYNC Wait_Here_For_IRQs NOP NOP NOP JUMP Wait_Here_For_IRQs CAN_TX_HANDLER ISR...

Page 802: ... Upper Byte to Check Lower R6 R6 R7 Byte for Wrap R5 0xFF Check Wrap Condition CC R6 R5 Check if Lower Byte Wraps IF CC JUMP HANDLE_COUNT_WRAP R7 1 If no wrap Increment Count JUMP PREPARE_TO_SEND HANDLE_COUNT_WRAP R6 0xFF00 Z Mask Off Lower Byte R7 R7 R6 Sets Lower Byte to 0 R6 0x0100 Z Increment Value for Upper Byte R7 R7 R6 Increment Upper Byte PREPARE_TO_SEND W P5 R7 Set New TX Data P5 L LO CAN...

Page 803: ... again CAN_RX_HANDLER SP R7 7 P5 4 Save Clobbered Registers SP ASTAT P4 H CAN_RX_WORD Set Pointer to Storage Element P4 L CAN_RX_WORD P5 H HI CAN_MBRIF1 P5 L LO CAN_MBRIF1 R7 MBRIF9 W P5 R7 Clear Interrupt Request Bit for MB09 P5 L LO CAN_MB_DATA3 9 R7 W P5 Z Read data from mailbox W P4 R7 Store data to memory ASTAT SP Restore Clobbered Registers R7 7 P5 4 SP SSYNC RTI ...

Page 804: ...Programming Examples 17 92 ADSP BF50x Blackfin Processor Hardware Reference ...

Page 805: ... BF504 ADSP BF504F ADSP BF506F Embedded Processor Data Sheet For SPI DMA channel assignments refer to Table 7 7 on page 7 105 in Chapter 7 Direct Memory Access For SPI interrupt vector assignments refer to Table 4 3 on page 4 19 in Chapter 4 System Interrupts To determine how each of the SPIs is multiplexed with other functional pins refer to Table 9 1 on page 9 4 through Table 9 3 on page 9 6 in ...

Page 806: ...environments The SPI compatible peripheral implementation also supports programmable bit rate and clock phase polarities The SPI features the use of open drain drivers to support the multimaster scenario and to avoid data contention Features The SPI includes these features Full duplex synchronous serial interface Supports 8 or 16 bit word sizes Programmable baud rate clock phase and polarity Suppo...

Page 807: ...ion Interface Overview Figure 18 1 provides a block diagram of the SPI The interface is essen tially a shift register that serially transmits and receives data bits one bit at a time at the SCK rate to and from other SPI devices SPI data is transmit ted and received at the same time through the use of a shift register When an SPI transfer occurs data is simultaneously transmitted shifted serially ...

Page 808: ...I Signal on page 18 5 Master In Slave Out MISO Signal on page 18 5 SPI Slave Select Input Signal SPISS on page 18 6 SPI Slave Select Enable Output Signals on page 18 7 Slave Select Inputs on page 18 8 Figure 18 1 SPI Block Diagram MOSI MISO SCK SPI INTERFACE LOGIC SHIFT REGISTER SPI_RDBR RECEIVE REGISTER SPI_TDBR TRANSMIT REGISTER SPI IRQ OR DMA REQUEST SPI INTERNAL CLOCK GENERATOR SPI_CTL SPI_FLG...

Page 809: ...iven on the MISO and MOSI lines Clock polarity and clock phase relative to data are programma ble in the SPI_CTL register and define the transfer format Master Out Slave In MOSI Signal The master out slave in MOSI signal is one of the bidirectional I O data pins If the processor is configured as a master the MOSI pin transmits data out If the processor is configured as a slave the MOSI pin receive...

Page 810: ...t can act as an error signal input in a multimaster environment In multimaster mode if the SPISS input signal of a master is asserted driven low and the PSSE bit in the SPI_CTL register is enabled an error has occurred This means that another device is also trying to be the master device The enable lead time T1 the enable lag time T2 and the sequential transfer delay time T3 each must always be gr...

Page 811: ...able signals automatically depending upon the configuration of the specific processor See Figure 18 14 on page 18 38 for details These signals are always active low in the SPI protocol Since the respec tive pins are not driven during reset it is recommended to pull them up by a resistor If enabled as a master the SPI uses the SPI_FLG register to enable gen eral purpose port pins to be used as indi...

Page 812: ... When PSSE 1 the SPISS input is the master mode error input Otherwise SPISS is ignored Use of FLS Bits in SPI_FLG for Multiple Slave SPI Systems The FLSx bits in the SPI_FLG register are used in a multiple slave SPI environment For example if there are eight SPI devices in the system including a master processor equipped with seven slave selects the master processor can support the SPI mode transa...

Page 813: ...ne SPI device by enabling only one slave SPI device at a time In case 3 all eight devices connected through SPI ports can be other processors 3 If all the slaves are also processors then the requester can receive data from only one processor enabled by clearing the EMISO bit in the six other slave processors at a time and transmit broadcast data to all seven at the same time This EMISO feature may...

Page 814: ...r when the shift register value is loaded into the receive buffer It becomes empty when the receive buffer is read The SPIF bit in the SPI_STAT register is set when the SPI port is disabled Upon entering DMA mode the transmit buffer and the receive buffer become empty That is the TXS bit and the RXS bit in the SPI_STAT register are initially cleared upon entering DMA mode Figure 18 4 Single Master...

Page 815: ...MMRs the primary performance criteria is latency not throughput Transfer latencies for both read and write transfers on the peripheral bus are two SCLK cycles The DAB bus provides a means for DMA SPI transfers to gain access to on chip and off chip memory with little or no degradation in core band width to memory The SPI peripheral as a DMA master is capable of sourcing DMA accesses The arbitratio...

Page 816: ...e combinations are selected using the CPOL and CPHA bits in SPI_CTL as shown in Figure 18 5 Figure 18 6 on page 18 14 and Figure 18 7 on page 18 14 demonstrate the two basic transfer formats as defined by the CPHA bit Two waveforms are shown for SCK one for CPOL 0 and the other for CPOL 1 The dia grams may be interpreted as master or slave timing diagrams since the SCK MISO and MOSI pins are direc...

Page 817: ...en CPHA 0 the slave select line SPISS must be inactive high between each serial transfer This is controlled automatically by the SPI hardware logic When CPHA 1 SPISS may either remain active low between successive transfers or be inactive high This must be controlled by the software through manipulation of the SPI_FLG register Figure 18 5 SPI Modes of Operation CLOCK PHASE CPHA CLOCK POLARITY CPOL...

Page 818: ...SCK starts toggling at the beginning of the data transfer SIZE 0 and LSBF 0 Figure 18 6 SPI Transfer Protocol for CPHA 0 Figure 18 7 SPI Transfer Protocol for CPHA 1 SPISS TO SLAVE SCK CPOL 0 SCK CPOL 1 MOSI FROM MASTER MISO FROM SLAVE 1 2 3 4 8 5 6 7 CLOCK CYCLE NUMBER UNDEFINED MSB LSB 6 5 4 3 2 1 MSB LSB 6 5 4 3 2 1 SPISS TO SLAVE SCK CPOL 0 SCK CPOL 1 MOSI FROM MASTER MISO FROM SLAVE 1 2 3 4 8...

Page 819: ...of a single master and a single slave CPHA 1 and the slave select input of the slave is always tied low In this case the slave is always selected and data corruption can be avoided by enabling the slave only after both the master and slave devices are configured In a multimaster or multislave SPI system the data output pins MOSI and MISO can be configured to behave as open drain outputs which prev...

Page 820: ...onnected together and all SCK pins are con nected together For a multislave environment the processor can make use of up to seven programmable flags that are dedicated SPI slave select signals for the SPI slave devices At reset the SPI is disabled and configured as a slave Clock Signals The SCK signal is a gated clock that is only active during data transfers for the duration of the transferred wo...

Page 821: ... data interrupt is generated when the SPI_TDBR regis ter is ready to be written to TIMOD b 01 or when the SPI_RDBR register is ready to be read from TIMOD b 00 An SPI error interrupt is generated in a master when a mode fault error occurs in both DMA and non DMA modes An error interrupt can also be generated in DMA mode when there is an underflow TXE when TIMOD b 11 or an overflow RBSY when TIMOD ...

Page 822: ...riate word length transfer format baud rate and other nec essary information 4 If the CPHA bit in the SPI_CTL register 1 the core activates the desired slaves by clearing one or more of the SPI flag bits FLGx of SPI_FLG 5 The TIMOD bits in SPI_CTL determine the SPI transfer initiate mode The transfer on the SPI link begins upon either a data write by the core to the SPI_TDBR register or a data rea...

Page 823: ... empty If GM 1 and the receive buffer is full the device continues to receive new data from the MISO pin overwriting the older data in the SPI_RDBR regis ter If GM 0 and the receive buffer is full the incoming data is discarded and SPI_RDBR is not updated Transfer Initiation From Master Transfer Modes When a device is enabled as a master the initiation of a transfer is defined by the two TIMOD bit...

Page 824: ...r com pleted Interrupt is active when the receive buffer is full Read of SPI_RDBR clears interrupt b 01 Transmit and receive Initiate new single word trans fer upon write to SPI_TDBR and previous transfer com pleted Interrupt is active when the transmit buffer is empty Writing to SPI_TDBR clears interrupt b 10 Receive with DMA Initiate new multiword trans fer upon enabling SPI for DMA mode Individ...

Page 825: ... until the slave has received the proper number of clock cycles 6 The slave device continues to receive transmit with each new fall ing edge transition on SPISS and or SCK clock edge See Table 18 8 on page 18 30 for additional information If the transmit buffer remains empty or the receive buffer remains full the device operates according to the states of the SZ and GM bits in SPI_CTL If SZ 1 and ...

Page 826: ...MOD At the start of the transfer the enabled slave select outputs are driven active low However the SCK signal remains inactive for the first half of the first cycle of SCK For a slave with CPHA 0 the transfer starts as soon as the SPISS input goes low For CPHA 1 a transfer starts with the first active edge of SCK for both slave and master devices For a master device a transfer is considered Table...

Page 827: ... software compatibility with other SPI devices the SPIF bit is also available for polling This bit may have a slightly different behavior from that of other commercially available devices For a slave device SPIF is cleared shortly after the start of a transfer SPISS going low for CPHA 0 first active edge of SCK on CPHA 1 and is set at the same time as RXS For a master device SPIF is cleared shortl...

Page 828: ... software should manually assert the required slave select signal before starting the transaction After all data has been transferred software typically releases the slave select again If the SPI slave device requires the slave select line to be asserted for the complete transfer this can be done in the SPI interrupt service routine only when operating in TIMOD b 00 or TIMOD b 10 mode With TIMOD b...

Page 829: ...PI DMA FIFO and writes to memory If configured for transmit the SPI requests a DMA read from memory Upon a DMA grant the DMA engine reads a word from memory and writes to the SPI DMA FIFO As the SPI writes data from the SPI DMA FIFO into the SPI_TDBR register it initiates a transfer on the SPI link 6 The SPI then generates the programmed clock pulses on SCK and simultaneously shifts data out of MO...

Page 830: ...ister is not updated While performing receive DMA the transmit buffer is assumed to be empty and TXE is set If SZ 1 the device repeatedly transmits zeros on the MOSI pin If SZ 0 it repeatedly transmits the contents of the SPI_TDBR register The TXE underrun condition cannot generate an error interrupt in this mode For transmit DMA operations the master SPI initiates a word transfer only when there ...

Page 831: ...to transmit or receive data the start of a transfer is triggered by a transition of the SPISS signal to the active low state or by the first active edge of SCK depending on the state of CPHA The following steps illustrate the SPI receive or transmit DMA sequence in an SPI slave in response to a master command 1 The core writes to the appropriate port register s to properly con figure the SPI for s...

Page 832: ...elect input is active the slave starts receiving and transmitting data on SCK edges The value in the SPI_TDBR register is loaded into the shift register at the start of the transfer 5 In receive mode as long as there is data in the SPI DMA FIFO FIFO not empty the SPI slave continues to request a DMA write to memory The DMA engine continues to read a word from the SPI DMA FIFO and writes to memory ...

Page 833: ...t stream the transmit port operates according to the state of the SZ bit If SZ 1 and the DMA FIFO is empty the device repeatedly transmits zeros on the MISO pin If SZ 0 and the DMA FIFO is empty it repeatedly transmits the last word it transmitted before the DMA buffer became empty All aspects of SPI receive operation should be ignored when configured in transmit DMA mode including the data in the...

Page 834: ...RE SPI HARDWARE AND ENABLE SPI PORT Y N WRITE SPI_FLG TO SELECT SLAVE S USING FLGx BITS WRITE SPI_TBDR WITH DATA TO SEND OVER SPI Y N READ SPI_RDBR TO START TRANSFER WAIT FOR TRANSFER COMPLETE LAST TRANSFER Y N TIMOD 01 Y N READ NEW DATA FROM SPI_RDBR CPHA 1 AND MSTR 1 N Y WRITE SPI_FLG TO DESELECT SLAVE S USING FLGx BITS WRITE SPI_CTL TO DISABLE SPI PORT WRITE TO PORT REGISTERS TO ENABLE AND SELE...

Page 835: ...G TO CONFIGURE DMA ENGINE 0x4 ARRAY 0x6 SMALL LIST 0x7 LARGE LIST 0x0 STOP 0x1 AUTOBUFFER POPULATE DESCRIPTORS IN MEMORY WRITE DMA REGISTERS DMA7_START_ADDR DMA7_X_COUNT DMA7_X_MODIFY DMA7_CONFIG S NDSIZE FIELD DETERMINES WHICH DMA REGISTERS TO INITIALIZE STATICALLY DMA7_CONFIG FLOW 0x6 SMALL LIST 0x7 LARGE LIST 0x4 ARRAY SET DMA7_CURR_DESC_PTR TO ADDRESS OF FIRST DESCRIPTOR SET DMA7_NEXT_DESC_PTR...

Page 836: ...MA7_Y_COUNT DMA7_Y_MODIFY MASTER MULTI SLAVE SUPPORT N A SLAVE MSTR 0 Y WRITE SPI_FLG TO SET APPROPRIATE FLSx BITS WRITE SPI_BAUD TO SET DESIRED SPI BIT RATE MSTR 1 WRITE SPI_CTL TO CONFIGURE SPI PORT CPHA 1 AND MSTR 1 Y N WRITE SPI_FLG TO SELECT SLAVE S USING FLGx BITS WRITE DMA7_CONFIG TO ENABLE DMA WRITE SPI_CTL TO ENABLE SPI B WRITE TO PORT REGISTERS TO ENABLE SLAVES ...

Page 837: ...RUPT BY WRITING THE DMA_DONE BIT IN DMA7_IRQ_STATUS N TX OR RX DMA TX B Y N WRITE DMA7_CONFIG TO ENABLE DMA AGAIN WAIT FOR DMA_RUN 0 IN DMA7_IRQ_STATUS WAIT FOR TWO STRAIGHT READS OF TXS 0 IN SPI_STAT WAIT FOR SPIF 1 IN SPI_STAT CPHA 1 AND MSTR 1 Y N WRITE SPI_FLG TO DESELECT SLAVE S VIA FLGx BITS WRITE SPI_CTL TO DISABLE SPI PORT WRITE DMA7_CONFIG TO DISABLE DMA FLOW STOP Y RX ...

Page 838: ...ers Figure 18 12 through Figure 18 18 provide details Table 18 3 SPI Register Mapping Register Name Function Notes SPI_BAUD SPI port baud control Value of 0 or 1 disables the serial clock SPI_CTL SPI port control SPE and MSTR bits can also be modified by hardware when MODF is set SPI_FLG SPI port flag Bits 0 and 8 are reserved SPI_STAT SPI port status SPIF bit can be set by clearing SPE in SPI_CTL...

Page 839: ...ng a value of 0 or 1 to the register disables the serial clock Therefore the maximum serial clock rate is one fourth the system clock rate Table 18 4 lists several possible baud rate values for SPI_BAUD Table 18 4 SPI Master Baud Rate Example SPI_BAUD Decimal Value SPI Clock SCK Divide Factor Baud Rate for SCLK at 100 MHz 0 N A N A 1 N A N A 2 4 25 MHz 3 6 16 7 MHz 4 8 12 5 MHz 65 535 0xFFFF 131 0...

Page 840: ...ion When set to b 01 the transaction is initiated when the transmit buffer is written A value of b 10 selects DMA receive mode and the first transaction is initiated by enabling the SPI for DMA receive mode Subse quent individual transactions are initiated by a DMA read of the SPI_RDBR register A value of 11 selects DMA transmit mode and the transaction is initiated by a DMA write of the SPI_TDBR ...

Page 841: ...d when SPI_TDBR is empty 0 Send last word 1 Send zeros GM Get More Data When SPI_RDBR is full get data or discard incoming data 0 Discard incoming data 1 Get more data overwrite previous data PSSE Slave Select Enable 0 Disable 1 Enable EMISO Enable MISO 0 MISO disabled 1 MISO enabled Reset 0x0400 SPE SPI Enable 0 Disabled 1 Enabled WOM Write Open Drain Master 0 Normal 1 Open drain MSTR Master Sets...

Page 842: ... 2 0 SPISSEL2 disabled 1 SPISSEL2 enabled FLS3 Slave Select Enable 3 0 SPISSEL3 disabled 1 SPISSEL3 enabled FLS4 Slave Select Enable 4 0 SPISSEL4 disabled 1 SPISSEL4 enabled FLS5 Slave Select Enable 5 0 SPISSEL5 disabled 1 SPISSEL5 enabled FLS6 Slave Select Enable 6 0 SPISSEL6 disabled 1 SPISSEL6 enabled FLS7 Slave Select Enable 7 0 SPISSEL7 disabled 1 SPISSEL7 enabled FLG7 Slave Select Value 7 SP...

Page 843: ...iate FLGx bits For example setting FLS3 in the SPI_FLG register drives the SPISSEL3 pin as a slave select Then clearing FLG3 in the SPI_FLG register drives the pin low and setting FLG3 drives it high The pin can be cycled high and low between transfers by setting and clearing FLG3 Otherwise the pin remains active low between transfers If CPHA 0 the SPI hardware sets the output value and the FLGx b...

Page 844: ...t write a 1 to bit 2 of SPI_STAT to clear the TXE error condition This allows the user to read SPI_STAT without changing its value Sticky bits are cleared on a reset but are not cleared on an SPI disable See Figure 18 15 for more information Figure 18 15 SPI Status Register 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset 0x0001 SPIF SPI Finished RO Set when SPI single w...

Page 845: ...ODF bit is cleared the SPI cannot be re enabled even as a slave Hardware prevents the user from setting either SPE or MSTR while MODF is set When MODF is cleared the interrupt is deactivated Before attempting to re enable the SPI as a master the state of the SPISS input pin should be checked to make sure the pin is high Otherwise once SPE and MSTR are set another mode fault error condition immedia...

Page 846: ...he GM bit in the SPI_CTL register determines whether SPI_RDBR is updated with the newly received data The RBSY bit is sticky W1C Transmit Collision Error TXCOL The TXCOL flag is set in SPI_STAT when a write to SPI_TDBR coincides with the load of the shift register The write to SPI_TDBR can be by software or the DMA The TXCOL bit indicates that corrupt data may have been loaded into the shift regis...

Page 847: ...zero under certain circumstances If multiple writes to SPI_TDBR occur while a transfer is already in progress only the last data written is transmitted None of the intermediate values written to SPI_TDBR are transmitted Multiple writes to SPI_TDBR are pos sible but not recommended SPI Receive Data Buffer SPI_RDBR Register The SPI_RDBR register is a 16 bit read only register At the end of a data tr...

Page 848: ...occurs the RXS bit in SPI_STAT is cleared and an SPI transfer may be initiated if TIMOD b 00 in SPI_CTL No such hardware action occurs when the SPI_SHADOW register is read The SPI_SHADOW register is read only Figure 18 17 SPI Receive Data Buffer Register Figure 18 18 SPI RDBR Shadow Register 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset 0x0000 Receive Data Buffer 15 0...

Page 849: ...ple shows how to initial ize the hardware signal the start of a transfer handle the interrupt and issue the next transfer and generate a stop condition Initialization Sequence Before the SPI can transfer data the registers must be configured as follows Listing 18 1 SPI Register Initialization SPI_Register_Initialization P0 H hi SPI_FLG P0 L lo SPI_FLG R0 W P0 Z BITSET R0 0x7 FLS7 W P0 R0 Enable sl...

Page 850: ...Is Master WOM 13 0 Normal MOSI MISO Data Output No Open Drain SPE 14 1 SPI Module Is Enabled 15 0 RESERVED P0 H hi SPI_CTL P0 L lo SPI_CTL R0 0x5908 W P0 R0 L ssync Enable SPI as MASTER Starting a Transfer After the initialization procedure in the given master mode a transfer begins following a dummy read of SPI_RDBR Typically known data which is desired to be transmitted to the slave is preloaded...

Page 851: ... SPI_RDBR P0 L lo SPI_RDBR R0 W P0 z Dummy read of SPI_RDBR kicks off transfer Post Transfer and Next Transfer Following the transfer of data the SPI generates an interrupt which is ser viced if the interrupt is enabled during initialization In the interrupt routine software must write the next value to be transmitted prior to reading the byte received This is because a read of the SPI_RDBR initia...

Page 852: ...a transfer to end after the user has transferred all data the following code can be used to stop the SPI Note that this is typically done in the interrupt handler to ensure the final data has been sent in its entirety Listing 18 4 Stopping SPI Stopping_SPI P0 H hi SPI_CTL P0 L lo SPI_CTL R0 W P0 BITCLR R0 14 Clear SPI enable bit W P0 R0 L ssync Disable SPI DMA Based Transfer The following DMA driv...

Page 853: ...acro indicating the number of elements being sent Listing 18 5 DMA Initialization Initialize_DMA Assume DMA7 as the channel for SPI DMA P0 H hi DMA7_CONFIG P0 L lo DMA7_CONFIG R0 0x1084 z Autobuffer mode IRQ on complete linear 16 bit mem read w P0 R0 P0 H hi DMA7_START_ADDR P0 L lo DMA7_START_ADDR p0 p1 Start address of TX buffer P0 H hi DMA7_X_COUNT P0 L lo DMA7_X_COUNT R0 NUM_SAMPLES w p0 R0 Num...

Page 854: ...te to SPI baud rate register W P0 R0 L ssync If SCLK 133MHz SPI clock 8kHz Setup SPI Control Register TIMOD 1 0 11 Transfer on DMA TDBR write SZ 2 0 Send last word when TDBR is empty GM 3 1 Discard incoming data if RDBR is full PSSE 4 0 Disables slave select as input master EMISO 5 0 MISO disabled for output master 7 and 6 0 RESERVED SIZE 8 1 16 Bit word length select LSBF 9 0 Transmit MSB first C...

Page 855: ... 7 Starting a Transfer Initiate_Transfer P0 H hi DMA7_CONFIG P0 L lo DMA7_CONFIG R2 w P0 z BITSET R2 0 Set DMA enable bit w p0 R2 L Enable TX DMA P4 H hi SPI_CTL P4 L lo SPI_CTL R2 w p4 z BITSET R2 14 Set SPI enable bit w p4 R2 Enable SPI Stopping a Transfer In order for a data transfer to end after the DMA has transferred all required data the following code is executed in the SPI DMA interrupt h...

Page 856: ...f the last word has been shifted out At that point it is safe to shut down the SPI port and the DMA engine Listing 18 8 Stopping a Transfer SPI_DMA_INTERRUPT_HANDLER P0 L lo DMA7_IRQ_STATUS P0 H hi DMA7_IRQ_STATUS R0 1 W P0 R0 Clear DMA interrupt Wait for DMA to complete P0 L lo DMA7_IRQ_STATUS P0 H hi DMA7_IRQ_STATUS R0 DMA_RUN 0x08 CHECK_DMA_COMPLETE Poll for DMA_RUN bit to clear R3 W P0 Z R1 R3...

Page 857: ...0 IF CC JUMP Check_TXS Wait for final word to transmit from SPI Final_Word R0 W P0 Z R2 SPIF 0x01 R0 R0 R2 CC R0 0 IF CC JUMP Final_Word Disable_SPI P0 L lo SPI_CTL P0 H hi SPI_CTL R0 W P0 Z BITCLR R0 0xe Clear SPI enable bit W P0 R0 Disable SPI Disable_DMA P0 L lo DMA7_CONFIG P0 H hi DMA7_CONFIG R0 W P0 Z BITCLR R0 0x0 Clear DMA enable bit W P0 R0 Disable DMA RTI Exit Handler ...

Page 858: ...Unique Information for the ADSP BF50x Processor 18 54 ADSP BF50x Blackfin Processor Hardware Reference Unique Information for the ADSP BF50x Processor None ...

Page 859: ...F ADSP BF506F Embedded Processor Data Sheet For SPORT DMA channel assignments refer to Table 7 7 on page 7 105 in Chapter 7 Direct Memory Access For SPORT interrupt vector assignments refer to Table 4 3 on page 4 19 in Chapter 4 System Interrupts To determine how each of the SPORTs is multiplexed with other func tional pins refer to Table 9 1 on page 9 4 through Table 9 3 on page 9 6 in Chapter 9 ...

Page 860: ... such as ADCs or codecs without external glue logic With support for high data rates independent transmit and receive channels and dual data paths the SPORT interface is a perfect choice for direct serial interconnection between two or more processors in a multiprocessor system Many processors provide compati ble interfaces including processors from Analog Devices and other manufacturers Each SPOR...

Page 861: ...the SPORT Provides two synchronous transmit and two synchronous receive data signals and buffers to double the total supported datastreams Performs A law and law hardware companding on transmitted and received words See Companding on page 19 29 for more information Internally generates serial clock and frame sync signals in a wide range of frequencies or accepts clock and frame sync input from an ...

Page 862: ... provides an I O interface to a wide variety of peripheral serial devices SPORTs provide synchronous serial data transfer only Each SPORT has one group of signals primary data secondary data clock and frame sync for transmit and a second set of signals for receive The receive and transmit functions are programmed separately A SPORT is a full duplex device capable of simultaneous data transfer in b...

Page 863: ...gister and then into the RX FIFO where it is available to the processor Table 19 1 shows the signals for each SPORT Table 19 1 SPORT Signals Pin Description DTxPRI Transmit Data Primary DTxSEC Transmit Data Secondary TSCLKx Transmit Clock TFSx Transmit Frame Sync DRxPRI Receive Data Primary DRxSEC Receive Data Secondary RSCLKx Receive Clock RFSx Receive Frame Sync ...

Page 864: ...serial data word or stream of serial words Figure 19 1 SPORT Block Diagram1 2 3 1 All wide arrow data paths are 16 or 32 bits wide depending on SLEN for SLEN 2 to 15 a 16 bit data path with 8 deep fifo is used for SLEN 16 to 31 a 32 bit data path with 4 deep fifo is used 2 TX register is the bottom of the TX fifo RX register is the top of the RX fifo 3 In multichannel mode the TFS pin acts as tran...

Page 865: ...ormation about DAGs see the Data Address Generators chapter in Blackfin Processor Pro gramming Reference Similarly for TX data should be written to the TX register in an alternating manner first primary then secondary then pri mary then secondary and so on This is easily accomplished with the processor s powerful DAGs In addition to the serial clock signal data must be signalled by a frame synchro...

Page 866: ... TDV output See Multichannel Op eration on page 19 15 2 Although shown as an external connection the TSCLK1 RSCLK1 connection is internal in multi channel mode See Multichannel Operation on page 19 15 RSCLK0 TSCLK0 TFS0 RFS0 SPORT0 DT0SEC DR0SEC DR0PRI DT0PRI TFS1 TDV1 TSCLK1 RSCLK1 RFS1 DT1SEC DR1SEC DR1PRI DT1PRI BLACKFIN SPORT1 SERIAL DEVICE 1 SERIAL DEVICE B SECONDARY SERIAL DEVICE A PRIMARY S...

Page 867: ...ORTs If connections on the data clock or frame sync lines are longer than six inches consider using a series termination for strip lines on point to point connections This may be necessary even when using low speed serial clocks because of the edge rates Figure 19 3 Stereo Serial Connection DBCLK DLRCLK DSDATA1 ALRCLK ABCLK DSDATA3 DSDATA2 ASDATA1 ASDATA2 AD1836 STEREO SERIAL DEVICE BLACKFIN RSCLK...

Page 868: ...tes the transmit interrupt or requests a DMA transfer as long as there is space in the TX FIFO As a SPORT receives bits they accumulate in an internal receive register When a complete word has been received it is written to the SPORT FIFO register and the receive interrupt for that SPORT is generated or a DMA transfer is initiated Interrupts are generated differently if DMA block transfers are per...

Page 869: ...llowed Setting SPORT Modes SPORT configuration is accomplished by setting bit and field values in configuration registers A SPORT must be configured prior to being enabled Once the SPORT is enabled further writes to the SPORT con figuration registers are disabled except for SPORT_RCLKDIV SPORT_TCLKDIV and multichannel mode channel select registers To change values in all other SPORT configuration ...

Page 870: ... the trans mit portion of the SPORT A control field which may be either set or cleared depending on the user s needs without changing the standard is indicated by an X ADSP BF50x SPORTs are designed such that in I2S master mode LRCLK is held at the last driven logic level and does not transition to provide an edge after the final data word is driven out There fore while transmitting a fixed number...

Page 871: ...nce setting RFSDIV or TFSDIV 31 produces an LRCLK that transitions every 32 serial clock cycles and has a period of 64 serial clock cycles The LRFS bit determines the polarity of the RFS or TFS frame sync pin for the channel that is considered a right channel Thus setting LRFS 0 meaning that it is an active high signal indicates that the frame sync is high for the right channel thus implying that ...

Page 872: ...hare a single clock in some designs See Figure 19 3 which shows multiple stereo serial connections being made between the processor and an AD1836 codec Figure 19 4 SPORT Stereo Serial Modes Transmit1 2 3 1 DSP mode does not identify channel 2 TFS normally operates at fS except for DSP mode which is 2 x fS 3 TSCLK frequency is normally 64 x TFS but may be operated in burst mode TFS TSCLK DTPRI TFS ...

Page 873: ... channels while ignoring the others Up to 128 channels are available for transmitting or receiving each SPORT can receive and transmit data selectively from any of the 128 channels These 128 channels can be any 128 out of the 1024 Figure 19 5 SPORT Stereo Serial Modes Receive1 2 3 1 DSP mode does not identify channel 2 RFS normally operates at fS except for DSP mode which is 2 x fS 3 RSCLK frequen...

Page 874: ...ltichannel mode and an inactive time slot occurs In multichannel mode RSCLK can either be provided externally or gener ated internally by the SPORT and this signal is used for both transmit and receive functions Leave TSCLK disconnected if the SPORT is used only in multichannel mode If RSCLK is externally or internally provided the signal is internally distributed to both the receiver and transmit...

Page 875: ...l data is sent or received on different channels sharing the same serial bus Can independently select transmit and receive channels RFS signals start of frame TFS is used as transmit data valid for external logic true only dur ing transmit channels Receive on channels 0 and 2 transmit on channels 1 and 2 Multichannel frame delay is set to 1 See Timing Examples on page 19 39 for more examples Figur...

Page 876: ... in multichannel mode When in multichannel mode do not enable the stereo serial frame sync modes or the late frame sync feature as these features are incompatible with multichannel mode Table 19 3 shows the dependencies of bits in the SPORT configuration register when the SPORT is in multichannel mode Table 19 3 Multichannel Mode Configuration SPORT_RCR1 or SPORT_RCR2 SPORT_TCR1 or SPORT_TCR2 Note...

Page 877: ...airs in SPORT_RCR1 and SPORT_TCR1 and in SPORT_RCR2 and SPORT_TCR2 should always be programmed identically with the possible exception of the RXSE and TXSE pair and the RDTYPE and TDTYPE pair This is true even if SPORT_RX operation is not enabled In multichannel mode RFS timing similar to late alternative frame mode is entered automatically the first bit of the transmit data word is available and ...

Page 878: ... previous frame This is acceptable and the frame sync is not ignored as long as the delayed channel 0 starting point falls outside the complete frame In multichannel mode the RFS signal is used for the block or frame start reference after which the word transfers are performed continuously with no further RFS signals required Therefore internally generated frame syncs are always data independent T...

Page 879: ...rame has been received because blocks of data occur back to back Window Size The window size WSIZE 3 0 defines the number of channels that can be enabled disabled by the multichannel select registers This range of words is called the active window The number of channels can be any value in the range of 0 to 15 corresponding to active window size of 8 to 128 in increments of 8 the default value of ...

Page 880: ...hat permits using all 128 channels As an example a program could define an active window with a window size of 8 WSIZE 0 and an offset of 93 WOFF 93 This 8 channel window would reside in the range from 93 to 100 Neither the window offset nor the window size can be changed while the SPORT is enabled If the combination of the window size and the window offset would place any portion of the window ou...

Page 881: ...e SPORT_MRCSn and SPORT_MTCSn multichannel select registers are used to enable and disable individual channels the SPORT_MRCSn registers spec ify the active receive channels and the SPORT_MTCSn registers specify the active transmit channels Four registers make up each multichannel select register Each of the four registers has 32 bits corresponding to 32 channels Setting a bit enables that channel...

Page 882: ...more information about companding Multichannel DMA Data Packing Multichannel DMA data packing and unpacking are specified with the MCDTXPE and MCDRXPE bits in the SPORT_MCMC2 multichannel configuration register If the bits are set indicating that data is packed the SPORT expects the data contained by the DMA buffer corresponds only to the enabled SPORT channels For example if an MCM frame contains...

Page 883: ...e following SPORT parameters must be set to support this standard Set for external frame sync Frame sync generated by external bus master TFSR RFSR set frame syncs required LTFS LRFS set active low frame syncs Set for external clock MCMEN set multichannel mode selected MFD 0 no frame delay between frame sync and first data bit SLEN 7 8 bit words FSDR 1 set for H 100 configuration enabling half clo...

Page 884: ...quency SCLK and the value of the 16 bit serial clock divide modulus registers SPORT_TCLKDIV and SPORT_RCLKDIV TSCLK frequency SCLK frequency 2 SPORT_TCLKDIV 1 RSCLK frequency SCLK frequency 2 SPORT_RCLKDIV 1 If the value of SPORT_TCLKDIV or SPORT_RCLKDIV is changed while the internal serial clock is enabled the change in TSCLK or RSCLK frequency takes effect at the start of the drive edge of TSCLK...

Page 885: ... frequency SPORT_RFSDIV 1 The frame sync would thus be continuously active for transmit if TFSDIV 0 or for receive if RFSDIV 0 However the value of TFSDIV or RFSDIV should not be less than the serial word length minus 1 the value of the SLEN field in SPORT_TCR2 or SPORT_RCR2 A smaller value could cause an external device to abort the current operation or have other unpredictable results If a SPORT...

Page 886: ...lues from 2 to 31 are allowed Continuous operation when the last bit of the current word is immediately followed by the first bit of the next word is restricted to word sizes of 4 or longer so SLEN 3 Bit Order Bit order determines whether the serial word is transmitted MSB first or LSB first Bit order is selected by the RLSBIT and TLSBIT bits in the SPORT_RCR1 and SPORT_TCR1 registers When RLSBIT ...

Page 887: ...alid data in the SPORT_RX register is the right justified expanded value of the eight LSBs received and sign extended to 16 bits A write to SPORT_TX causes the 16 bit value to be compressed to eight LSBs sign extended to the width of the transmit word and written to the internal transmit register Although the com panding standards support only 13 bit A law or 14 bit law maximum word lengths up to ...

Page 888: ...nerated internally by the processor and the TSCLK or RSCLK pin is an output The clock frequency is determined by the value of the serial clock divisor in the SPORT_RCLKDIV register When IRCLK or ITCLK 0 the clock signal is accepted as an input on the TSCLK or RSCLK pins and the serial clock divisors in the SPORT_TCLKDIV SPORT_RCLKDIV registers are ignored The externally gener ated serial clocks do...

Page 889: ...ive frame sync required select control bits determine whether frame sync sig nals are required These bits are located in the SPORT_TCR1 and SPORT_RCR1 registers When TFSR 1 or RFSR 1 a frame sync signal is required for every data word To allow continuous transmitting by the SPORT each new data word must be loaded into the SPORT_TX hold register before the previous word is shifted out and transmitt...

Page 890: ...s reception Active low or active high frame syncs are selected with the LTFS and LRFS bits of the SPORT_TCR1 and SPORT_RCR1 registers See Timing Examples on page 19 39 for more timing examples Internal Versus External Frame Syncs Both transmit and receive frame syncs can be independently generated internally or can be input from an external source The ITFS and IRFS bits of the SPORT_TCR1 and SPORT...

Page 891: ... either active high or active low in other words inverted The LTFS and LRFS bits of the SPORT_TCR1 and SPORT_RCR1 regis ters determine frame sync logic levels When LTFS 0 or LRFS 0 the corresponding frame sync signal is active high When LTFS 1 or LRFS 1 the corresponding frame sync signal is active low Active high frame syncs are the default The LTFS and LRFS bits are initial ized to 0 after a pro...

Page 892: ...s Note externally generated data and frame sync signals should change state on the opposite edge than that selected for sampling For example for an externally generated frame sync to be sampled on the rising edge of the clock TCKFE 1 in the SPORT_TCR1 regis ter the frame sync must be driven on the falling edge of the clock The transmit and receive functions of two SPORTs connected together should ...

Page 893: ... the transmit data word is available and the first bit of the receive data word is sampled in the serial clock cycle after the frame sync is asserted and the frame sync is not checked again until the entire word has been transmitted or received In multichannel operation this corresponds to the case when multichannel frame delay is 1 If data transmission is continuous in early framing mode in other...

Page 894: ...gnal is only checked during the first bit of each word Internally generated frame syncs remain asserted for the entire length of the data word in late framing mode Externally generated frame syncs are only checked during the first bit Figure 19 12 illustrates the two modes of frame signal timing In summary For the LATFS or LARFS bits of the SPORT_TCR1 or SPORT_RCR1 regis ters LATFS 0 or LARFS 0 fo...

Page 895: ...tion allows data to be transmitted only when it is available When DITFS 1 the internally generated TFS is output at its programmed interval regardless of whether new data is available in the SPORT_TX buffer Whatever data is present in SPORT_TX is transmitted again with each asser tion of TFS The TUVF transmit underflow status bit in the SPORT_STAT register is set when this occurs and old data is r...

Page 896: ...ssor core to continue running until the entire block of data is transmitted or received Interrupt service routines ISRs can then operate on the block of data rather than on single words significantly reducing overhead SPORT RX TX and Error Interrupts The SPORT RX interrupt is asserted when RSPEN is enabled and any words are present in the RX FIFO If RX DMA is enabled the SPORT RX interrupt is turn...

Page 897: ...ions Framed Versus Unframed on page 19 31 Early Versus Late Frame Syncs Normal Versus Alternate Timing on page 19 35 and Frame Syncs in Multichannel Mode on page 19 19 This section con tains additional examples to illustrate other possible combinations of the framing options These timing examples show the relationships between the signals but are not scaled to show the actual timing parameters of ...

Page 898: ...tic of an internally generated frame sync Note the output meets the input timing requirement therefore with two SPORT channels used one SPORT channel could provide RFS for the other SPORT channel Figure 19 13 SPORT Receive Normal Framing Figure 19 14 SPORT Continuous Receive Normal Framing B3 B3 B2 B1 B0 B2 B1 B0 SPORT CONTROL REGISTER BOTH INTERNAL FRAMING OPTION AND EXTERNAL FRAMING OPTION SHOWN...

Page 899: ... This mode is appropriate for multiword bursts continuous reception Figure 19 15 SPORT Receive Alternate Framing Figure 19 16 SPORT Continuous Receive Alternate Framing B3 B3 B2 B1 B0 B2 B1 B0 SPORT CONTROL REGISTER BOTH INTERNAL FRAMING OPTION AND EXTERNAL FRAMING OPTION SHOWN DR REPRESENTS DRPRI AND OR DRSEC DEPENDING ON DESIRED CONFIGURATION RSCLK RFS OUTPUT DR RFS INPUT RSCLK RFS OUTPUT RFS IN...

Page 900: ...les between words Figure 19 21 and Figure 19 22 show non continuous and continuous transmission in the alternate framing mode As noted previously for the receive timing dia grams the RFS output meets the RFS input timing requirement Figure 19 17 SPORT Receive Unframed Mode Normal Framing Figure 19 18 SPORT Receive Unframed Mode Alternate Framing RSCLK RFS DR B3 B2 B1 B0 B3 B2 B1 B0 B2 B3 DR REPRES...

Page 901: ...AND EXTERNAL FRAMING OPTION SHOWN DT REPRESENTS DTPRI AND OR DTSEC DEPENDING ON DESIRED CONFIGURATION B2 B1 B0 B3 B2 B1 B0 B3 B3 B2 TSCLK TFS OUTPUT TFS INPUT TR SPORT CONTROL REGISTER BOTH INTERNAL FRAMING OPTION AND EXTERNAL FRAMING OPTION SHOWN DT REPRESENTS DTPRI AND OR DTSEC DEPENDING ON DESIRED CONFIGURATION B2 B1 B0 B3 B2 B1 B0 B3 SPORT CONTROL REGISTER BOTH INTERNAL FRAMING OPTION AND EXTE...

Page 902: ...e 19 22 SPORT Continuous Transmit Alternate Framing Figure 19 23 SPORT Transmit Unframed Mode Normal Framing Figure 19 24 SPORT Transmit Unframed Mode Alternate Framing B2 B1 B0 B3 B0 B3 B2 B1 TSCLK TFS OUTPUT TFS INPUT TR SPORT CONTROL REGISTER BOTH INTERNAL FRAMING OPTION AND EXTERNAL FRAMING OPTION SHOWN DT REPRESENTS DTPRI AND OR DTSEC DEPENDING ON DESIRED CONFIGURATION TSCLK TFS DT B3 B3 B0 B...

Page 903: ...ed if external frame sync mode is selected SPORT_TX Transmit data register See description of FIFO buffering at SPORT Transmit Data SPORT_TX Register on page 19 57 SPORT_RCR1 Primary receive configuration register Bits 15 1 can only be written if bit 0 0 SPORT_RCR2 Secondary receive configuration register SPORT_RCLK_DIV Receive clock divider register Ignored if external SPORT clock mode is selecte...

Page 904: ...isters After a write to a SPORT register while the SPORT is disabled any changes to the control and mode bits generally take effect when the SPORT is re enabled Most configuration registers can only be changed while the SPORT is disabled TSPEN RSPEN 0 Changes take effect after the SPORT is re enabled The only exceptions to this rule are the TCLKDIV RCLKDIV registers and multichannel select registe...

Page 905: ...register is set to 1 This bit is cleared during either a hard reset or a soft reset disabling all SPORT transmission When the SPORT is enabled to transmit TSPEN set corresponding SPORT configuration register writes are not allowed except for SPORT_TCLKDIV and multichannel mode channel select registers Writes to disallowed registers have no effect While the SPORT is enabled SPORT_TCR1 is not writte...

Page 906: ...k Falling Edge Select 0 External transmit clock selected 1 Internal transmit clock selected 00 Normal operation 01 Reserved 10 Compand using law 11 Compand using A law 0 Transmit MSB first 1 Transmit LSB first Reset 0x0000 0 External TFS used 1 Internal TFS used 0 Drive data and internal frame syncs with rising edge of TSCLK Sample external frame syncs with falling edge of TSCLK 1 Drive data and i...

Page 907: ...are used DMA control should be con figured correctly before setting TSPEN Set all DMA control registers before setting TSPEN Clearing TSPEN causes the SPORT to stop driving data TSCLK and frame sync pins it also shuts down the internal SPORT circuitry In low power applications battery life can be extended by clearing TSPEN whenever the SPORT is not in use Figure 19 26 SPORT Transmit Configuration ...

Page 908: ...he data words transmitted over the SPORT Serial word length select SLEN The serial word length the num ber of bits in each word transmitted over the SPORTs is calculated by adding 1 to the value of the SLEN field Serial Word Length SLEN 1 The SLEN field can be set to a value of 2 to 31 0 and 1 are illegal values for this field Three common settings for the SLEN field are 15 to transmit a full 16 b...

Page 909: ... generates a data independent TFS sync at selected interval or a data dependent TFS sync when data is present in SPORT_TX for the case of internal frame sync select ITFS 1 The DITFS bit is ignored when external frame syncs are selected The frame sync pulse marks the beginning of the data word If DITFS is set the frame sync pulse is issued on time whether the SPORT_TX register has been loaded or no...

Page 910: ...e falling edge TxSec enable TXSE This bit enables the transmit secondary side of the SPORT if set Stereo serial enable TSFSE This bit enables the stereo serial oper ating mode of the SPORT if set By default this bit is cleared enabling normal clocking and frame sync Left Right order TRFST If this bit is set the right channel is transmitted first in stereo serial operating mode By default this bit ...

Page 911: ...led 1 Receive enabled IRFS Internal Receive Frame Sync Select IRCLK Internal Receive Clock Select RDTYPE 1 0 Data Formatting Type Select RLSBIT Receive Bit Order RSPEN Receive Enable LRFS Low Receive Frame Sync Select LARFS Late Receive Frame Sync 0 Early frame syncs 1 Late frame syncs RCKFE Clock Falling Edge Select 0 External receive clock selected 1 Internal receive clock selected 00 Zero fill ...

Page 912: ...ting RSPEN also generates DMA requests if DMA is enabled and data is received Set all DMA control registers before setting RSPEN Clearing RSPEN causes the SPORT to stop receiving data it also shuts down the internal SPORT receive circuitry In low power applications battery life can be extended by clearing RSPEN when ever the SPORT is not in use Figure 19 28 SPORT Receive Configuration 2 Register 1...

Page 913: ...rder of the data words received over the SPORTs Serial word length select SLEN The serial word length the num ber of bits in each word received over the SPORTs is calculated by adding 1 to the value of the SLEN field The SLEN field can be set to a value of 2 to 31 0 and 1 are illegal values for this field The frame sync signal is controlled by the SPORT_TFSDIV and SPORT_RFSDIV registers not by SLE...

Page 914: ... rising edge If cleared internally generated frame syncs are driven on the rising edge and data and externally generated frame syncs are sampled on the fall ing edge RxSec enable RXSE This bit enables the receive secondary side of the SPORT if set Stereo serial enable RSFSE This bit enables the stereo serial oper ating mode of the SPORT if set By default this bit is cleared enabling normal clockin...

Page 915: ...han 16 bits When transmit is enabled data from the FIFO is assembled in the TX Hold register based on TXSE and SLEN and then shifted into the primary and secondary shift registers From here the data is shifted out serially on the DTPRI and DTSEC pins Figure 19 29 SPORT Transmit FIFO Data Ordering 0 15 0 15 0 15 0 15 PRIMARY PRIMARY PRIMARY PRIMARY PRIMARY PRIMARY PRIMARY PRIMARY W7 W6 W5 W4 W3 W2 ...

Page 916: ...ky write 1 to clear W1C bit and is also cleared by disabling the SPORT writing TSPEN 0 If software causes the core processor to attempt a write to a full TX FIFO with a SPORT_TX write the new data is lost and no overwrites occur to data in the FIFO The TOVF status bit is set and a SPORT error interrupt is asserted The TOVF bit is a sticky bit it is only cleared by disabling the SPORT TX To find ou...

Page 917: ... shared by both primary and secondary receive data The order for reading using peripheral bus DMA reads is important since data is stored in differently depending on the setting of the SLEN and RXSE configuration bits Data storage and data ordering in the FIFO are shown in Figure 19 31 The SPORT_RX register is shown in Figure 19 32 Figure 19 30 SPORT Transmit Data Register SPORT Transmit Data Regi...

Page 918: ...ARY PRIMARY PRIMARY PRIMARY PRIMARY PRIMARY PRIMARY PRIMARY PRIMARY PRIMARY PRIMARY PRIMARY PRIMARY PRIMARY PRIMARY PRIMARY W7 0 PRIMARY AND SECONDARY ENABLED DATA LENGTH 16 BITS PRIMARY AND SECONDARY ENABLED DATA LENGTH 16 BITS 15 W6 W5 W4 W3 W2 W1 W0 W3 LOW 0 15 W3 HIGH W2 LOW W2 HIGH W1 LOW W1 HIGH W0 LOW W0 HIGH SECONDARY W3 0 15 PRIMARY PRIMARY PRIMARY PRIMARY PRIMARY PRIMARY PRIMARY PRIMARY ...

Page 919: ...is disabled To determine if the core can access the RX registers without causing this error first read the RX FIFO status RXNE in the SPORT_STAT register The RUVF status bit is updated even when the SPORT is disabled The ROVF status bit is set in the SPORT_STAT register when a new word is assembled in the RX shift register and the RX hold register has not moved the data to the FIFO The previously ...

Page 920: ...e DITFS control bit in the SPORT_TCR1 reg ister The TUVF status bit is a sticky write 1 to clear W1C bit and is also cleared by disabling the SPORT writing TSPEN 0 For continuous transmission TFSR 0 TUVF is set at the end of a trans mitted word if no new word is available in the TX hold register The TOVF bit is set when a word is written to the TX FIFO when it is full It is a sticky W1C bit and is...

Page 921: ...vider Register 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 SPORT Status Register SPORT_STAT 0 Disabled 1 Enabled RUVF Sticky Receive Under flow Status W1C RXNE Receive FIFO Not Empty Status ROVF Sticky Receive Over flow Status W1C TUVF Sticky Transmit Underflow Status W1C 0 Disabled 1 Enabled 0 Empty 1 Data present in FIFO Reset 0x0040 0 Disabled 1 Enabled TOVF Sticky Tra...

Page 922: ...cycles applies to either internally or externally generated serial clocks These registers are shown in Figure 19 36 and Figure 19 37 Figure 19 35 SPORT Receive Serial Clock Divider Register Figure 19 36 SPORT Transmit Frame Sync Divider Register SPORT Receive Serial Clock Divider Register SPORT_RCLKDIV 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Serial Clock Divide Modulu...

Page 923: ...rame Sync Divider Register Figure 19 38 SPORT Multichannel Configuration Register 1 SPORT Receive Frame Sync Divider Register SPORT_RFSDIV 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Frame Sync Divider 15 0 Reset 0x0000 Number of receive clock cycles counted before generating RFS pulse 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SPORT Multichanne...

Page 924: ...ronization delays between RSCLK and the processor clock the channel register value is approximate It is never ahead of the channel being served but it may lag behind See Figure 19 40 Figure 19 39 SPORT Multichannel Configuration Register 2 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SPORT Multichannel Configuration Register 2 SPORT_MCMC2 0x Bypass mode 10 Recover 2 MHz cl...

Page 925: ...r example set ting bit 0 selects word 0 setting bit 12 selects word 12 and so on Setting a particular bit in the SPORT_MRCSn register causes the SPORT to receive the word in that channel s position of the datastream the received word is loaded into the RX buffer When the secondary receive side is enabled by the RXSE bit both inputs are processed on enabled channels Clearing the bit in the SPORT_MR...

Page 926: ... transmit side is enabled by the TXSE bit both sides transmit a word on the enabled channel Clearing the bit in the SPORT_MTCSn register Figure 19 41 SPORT Multichannel Receive Select Registers For all bits 0 Channel disabled 1 Channel enabled so SPORT selects that word from multi ple word block of data 31 31 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 63 0 32 31 95 0 64...

Page 927: ...eric labels for the content of the SPORT s configuration registers SPORT_RCRn Figure 19 42 SPORT Multichannel Transmit Select Registers SPORT Multichannel Transmit Select Registers SPORT_MTCSn For all bits 0 Channel disabled 1 Channel enabled so SPORT selects that word from multiple word block of data 31 31 0 0 31 63 0 32 31 95 0 64 31 127 0 96 Reset 0x0000 0000 Reset 0x0000 0000 Reset 0x0000 0000...

Page 928: ...n Sequence The SPORT s receiver and transmitter are configured but they are not enabled yet Listing 19 1 SPORT Initialization Program_SPORT_TRANSMITTER_Registers Set P0 to SPORT0 Base Address P0 h hi SPORT0_TCR1 P0 l lo SPORT0_TCR1 Configure Clock speeds R1 SPORT_TCLK_CONFIG Divider SCLK TCLK value 0 to 65535 W P0 SPORT0_TCLKDIV SPORT0_TCR1 R1 TCK divider register number of Bitclocks between Frame...

Page 929: ... h hi SPORT0_RCR1 P0 l lo SPORT0_RCR1 Configure Clock speeds R1 SPORT_RCLK_CONFIG Divider SCLK RCLK value 0 to 65535 W P0 SPORT0_RCLKDIV SPORT0_RCR1 R1 RCK divider register number of Bitclock between FrameSyncs 1 value SPORT_SLEN to 65535 R1 SPORT_RFSDIV_CONFIG W P0 SPORT0_RFSDIV SPORT0_RCR1 R1 RFSDIV register Receive configuration Configuration register 2 for instance 0x000E for 16 bit wordlength...

Page 930: ...the DMA channels can be enabled at the end of the configura tion since the SPORT is not enabled yet However if preferred the user can enable the DMA later immediately before enabling the SPORT The only requirement is that the DMA channel be enabled before the associ ated peripheral is enabled to start the transfer Listing 19 2 DMA Initialization Program_DMA_Controller Receiver DMA channel 3 Set P0...

Page 931: ...DMA3_CONFIG R1 BITSET R0 0 R0 still contains value of CONFIG register set bit 0 W P0 R0 enable DMA channel SPORT not enabled yet Transmitter DMA channel 4 Set P0 to DMA Base Address P0 l lo DMA4_CONFIG P0 h hi DMA4_CONFIG Configuration for instance 0x1088 for Autobuffer 32 bit wide transfers R0 DMA_TRANSMIT_CONF z W P0 R0 configuration register tx_buf Buffer in Data memory divide count by four bec...

Page 932: ...t 0 W P0 R0 enable DMA channel SPORT not enabled yet Interrupt Servicing The receive channel and the transmit channel will each generate an inter rupt request if so programmed The following code fragments show the minimum actions that must be taken Not shown is the programming of the core and system event controllers Listing 19 3 Servicing an Interrupt RECEIVE_ISR SP RETI nesting of interrupts cle...

Page 933: ...rti Starting a Transfer After the initialization procedure outlined in the previous sections the receiver and transmitter are enabled The core may just wait for interrupts Listing 19 4 Starting a Transfer Enable Sport0 RX and TX P0 h hi SPORT0_RCR1 P0 l lo SPORT0_RCR1 R1 W P0 Z BITSET R1 0 W P0 R1 ssync Enable Receiver set bit 0 P0 h hi SPORT0_TCR1 P0 l lo SPORT0_TCR1 R1 W P0 Z BITSET R1 0 W P0 R1...

Page 934: ...for the ADSP BF50x Processor 19 76 ADSP BF50x Blackfin Processor Hardware Reference dummy wait loop do nothing but waiting for interrupts wait_forever jump wait_forever Unique Information for the ADSP BF50x Processor None ...

Page 935: ...F504 ADSP BF504F ADSP BF506F Embedded Processor Data Sheet For PPI DMA channel assignments refer to Table 7 7 on page 7 105 in Chapter 7 Direct Memory Access For PPI interrupt vector assignments refer to Table 4 3 on page 4 19 in Chapter 4 System Interrupts To determine how each of the PPIs is multiplexed with other functional pins refer to Table 9 1 on page 9 4 through Table 9 3 on page 9 6 in Ch...

Page 936: ... samples can be packed as a single 16 bit word In such a case the earlier sample is placed in the 8 least significant bits LSBs Features The PPI includes these features Half duplex bidirectional parallel port Supports up to 16 bits of data Programmable clock and frame sync polarities ITU R 656 support Interrupt generation on overflow and underrun Typical peripheral devices that can be interfaced t...

Page 937: ...X and TX modes there may be at least 2 cycles latency before valid data is received or transmitted The PPI_CLK not only supplies the PPI module itself but it also can clock one or more GP Timers to work synchronously with the PPI Depending on PPI operation mode the PPI_CLK can either equal or invert the TMRCLK input For more information see the General Purpose Timers chapter Figure 20 1 PPI Block ...

Page 938: ... 0 11 11 0 or 1 0 or 1 1 RX mode 1 exter nal frame sync 1 0 00 11 0 or 1 0 or 1 0 RX mode 2 or 3 external frame syncs 3 0 10 11 0 or 1 0 or 1 0 RX mode 2 or 3 internal frame syncs 3 0 01 11 0 or 1 0 or 1 0 RX mode ITU R 656 active field only embed ded 0 00 00 0 or 1 0 0 or 1 RX mode ITU R 656 vertical blank ing only embed ded 0 00 10 0 or 1 0 0 RX mode ITU R 656 entire field embed ded 0 00 01 0 or...

Page 939: ...r 525 60 NTSC and 625 50 PAL sys tems The processor supports only the bit parallel mode of ITU R 656 Both 8 and 10 bit video element widths are supported In this mode the horizontal H vertical V and field F signals are sent as an embedded part of the video datastream in a series of bytes that form a control word The start of active video SAV and end of active video EAV signals indicate the beginni...

Page 940: ... denotes an even field Progressive video makes no distinc tion between field 1 and field 2 whereas interlaced video requires each field to be handled uniquely because alternate rows of each field combine to create the actual video image Figure 20 2 ITU R 656 8 Bit Parallel Data Stream for NTSC PAL Systems 4 268 280 FOR PAL 4 1440 F F 0 0 0 0 X Y 8 0 1 0 8 0 1 0 8 0 1 0 F F 0 0 0 0 X Y C B Y C R Y ...

Page 941: ...it definitions are as follows F 0 for field 1 F 1 for field 2 Figure 20 3 Typical Video Frame Partitioning for NTSC PAL Systems for ITU R BT 656 4 LINE 4 FIELD 1 ACTIVE VIDEO FIELD 1 ACTIVE VIDEO FIELD 2 ACTIVE VIDEO FIELD 2 ACTIVE VIDEO FIELD 1 FIELD 2 LINE 266 LINE 313 LINE 625 LINE 3 LINE 1 EAV SAV EAV SAV 1 20 264 283 525 1 23 311 336 624 625 LINE NUMBER LINE NUMBER F H SAV H EAV H SAV H EAV F...

Page 942: ...enough to accommodate different row and field lengths In general as long as the incoming video has the proper EAV SAV codes the PPI can read it in In other words a CIF image could be formatted to be 656 compliant where EAV and SAV values define the range of the image for each line and the V and F codes can be used to delimit fields and frames Table 20 2 Control Byte Sequences for 8 Bit and 10 Bit ...

Page 943: ...g bitstream is read in through the PPI This includes active video as well as control byte sequences and ancillary data that may be embedded in horizontal and vertical blanking intervals Data transfer starts immediately after synchronization to field 1 occurs Figure 20 4 ITU R 656 Input Modes Figure 20 5 ITU R 656 Input Submodes PPIx PPI_CLK PPI CLK 656 COMPATIBLE VIDEOSOURCE ITU R 656 INPUT MODE 8...

Page 944: ...etween EAV and SAV as well as all data present when V 1 In this mode the control byte sequences are not stored to memory they are filtered out by the PPI After synchronizing to the start of field 1 the PPI ignores incoming samples until it sees an SAV In this mode the user specifies the number of total active plus ver tical blanking lines per frame in the PPI_FRAME MMR Vertical Blanking Interval V...

Page 945: ...is could be performed in a number of ways For instance one line of blanking H V could be stored in a buffer and sent out N times by the DMA controller when appropriate before proceeding to DMA active video Alternatively one entire field with control codes and blanking can be set up statically in a buffer while the DMA engine transfers only the active video region into the buffer on a frame by fram...

Page 946: ...in General Purpose PPI Modes The general purpose PPI modes are intended to suit a wide variety of data capture and transmission applications Table 20 3 summarizes these modes If a particular mode shows a given PPI_FSx frame sync not being used this implies that the pin is available for its alternate multiplexed functions Table 20 3 General Purpose PPI Modes GP PPI Mode PPI_FS1 Direction PPI_FS2 Di...

Page 947: ...ple counter reinitial izes to 0 and starts to count up to PPI_COUNT again This situation can cause the DMA channel configuration to lose synchronization with the PPI transfer process The bottom of Figure 20 6 shows an example of TX mode one internal frame sync After PPI_FS1 is asserted there is a latency of one PPI_CLK cycle and then there is a delay for the number of PPI_CLK cycles pro grammed in...

Page 948: ...ration to lose synchronization with the PPI transfer process Data Input RX Modes The PPI supports several modes for data input These modes differ chiefly by the way the data is framed Refer to Table 20 1 on page 20 4 for infor mation on how to configure the PPI for each mode Figure 20 6 General Flow for GP Modes Assumes Positive Assertion of PPI_FS1 INPUT OUTPUT PPI_COUNT PPI_COUNT 1 CYCLE DELAY P...

Page 949: ...EL 1 and PORT_CFG b 11 All subsequent data manipulation is handled via DMA For example an arrangement could be set up between alternating 1K byte memory buffers When one fills up DMA continues with the second buffer at the same time that another DMA operation is clearing the first memory buffer for reuse Due to clock domain synchronization in RX modes with no frame syncs there may be a delay of at...

Page 950: ...pported by not enabling the PPI_FS3 pin See the Product Specific Implementation section for information on how this is achieved on this processor 2 or 3 Internal Frame Syncs This mode can be useful for interfacing to video sources that can be slaved to a master processor In other words the processor controls when to read from the video source by asserting PPI_FS1 and PPI_FS2 and then reading data ...

Page 951: ...troller are sent out through the PPI with no framing That is once the DMA channel is con figured and enabled and the PPI is configured and enabled data transfers will take place immediately synchronized to PPI_CLK See Figure 20 9 for an illustration of this mode In this mode there is a delay of up to 16 SCLK cycles for 8 bit data or 32 SCLK cycles for 8 bit data between enabling the PPI and transm...

Page 952: ...ustrates the 2 sync mode There is a mandatory delay of 1 5 PPI_CLK cycles plus the value programmed in PPI_DELAY between assertion of the external frame sync s and the transfer of valid data out through the PPI Figure 20 9 TX Mode 0 Frame Syncs Figure 20 10 TX Mode 1 or 2 External Frame Syncs CLK PPIx PPI_CLK RECEIVER 8 TO 16 BIT DATA DATA RECEIVER DATA RECEIVER PPIx CLK CLK PPI_CLK PPI_FS1 PPI_FS...

Page 953: ...plicitly supported by leaving PPI_FS3 unconnected in this case Frame Synchronization in GP Modes Frame synchronization in general purpose modes operates differently in modes with internal frame syncs than in modes with external frame syncs Modes With Internal Frame Syncs In modes with internal frame syncs PPI_FS1 and PPI_FS2 link directly to the pulsewidth modulation PWM circuits of general purpos...

Page 954: ...nherent programmability To program PPI_FS1 and or PPI_FS2 for operation in an internal frame sync mode 1 Configure and enable DMA for the PPI See DMA Operation on page 20 22 2 Configure the width and period for each frame sync signal via the appropriate TIMER_WIDTH and TIMER_PERIOD registers 3 Set up the appropriate TIMER_CONFIG register s for PWM_OUT mode This includes setting CLK_SEL to 1 and TI...

Page 955: ... refer to the General Purpose Timers chapter In RX mode with 3 external frame syncs the start of frame detec tion occurs where a PPI_FS2 assertion is followed by an assertion of PPI_FS1 while PPI_FS3 is low This happens at the start of field 1 Note that PPI_FS3 only needs to be low when PPI_FS1 is asserted not when PPI_FS2 asserts Also PPI_FS3 is only used to synchro nize to the start of the very ...

Page 956: ...ight bits only one element can be clocked in per PPI_CLK cycle and this results in reduced bandwidth since no packing is possible The highest throughput is achieved with 8 bit data and PACK_EN 1 packing mode enabled Note for 16 bit packing mode there must be an even number of data elements Configuring the PPI s DMA channel is a necessary step toward using the PPI interface It is the DMA engine tha...

Page 957: ...20 YCOUNT 2 and DI_SEL 1 causes an interrupt when half of the frame has been transferred and again when the whole frame has been transferred The general procedure for setting up DMA operation with the PPI follows 1 Configure DMA registers as appropriate for desired DMA operat ing mode 2 Enable the DMA channel for operation 3 Configure appropriate PPI registers 4 Enable the PPI by writing a 1 to bi...

Page 958: ...Y_MODIFY START Enable necessary PPI pins through PORT_MUX and PORT_FER registers GP Y N PROGRAM PPI_FRAME FS N PROGRAM PPI_DELAY EXTERNAL TRIGGER N Y PROGRAM PPI_COUNT INTERNAL FS N Y PROGRAM TIMER S LINKED WITH FS Y WRITE DMA_CONFIG TO ENABLE DMA WRITE PPI_CONTROL TO ENABLE PPI INTERNAL FS N Y WRITE TIMER_ENABLE TO ENABLE TIMERS END ...

Page 959: ...the PPI_CLK and PPI_FS1 PPI_FS2 signals respectively This provides a mechanism to connect to data sources and receivers with a wide array of control signal polarities Often the remote data source receiver also offers configurable signal polarities so the POLC and POLS bits simply add increased flexibility The DLEN 2 0 field is programmed to specify the width of the PPI port in any mode Note any wi...

Page 960: ...elds 1 and 2 In RX mode with external frame sync when PORT_CFG 11 0 External trigger 1 Internal trigger 0 PPI_FS1 and PPI_FS2 are treated as rising edge asserted 1 PPI_FS1 and PPI_FS2 are treated as falling edge asserted SKIP_EN Skip Enable SKIP_EO Skip Even Odd In ITU R 656 and GP Input modes 0 Skip odd numbered elements 1 Skip even numbered elements In ITU R 656 and GP Input modes 0 Skipping dis...

Page 961: ...ncs The PACK_EN bit only has meaning when the PPI port width selected by DLEN 2 0 is eight bits Every PPI_CLK initiated event on the DMA bus that is an input or output operation handles 16 bit entities In other words an input port width of ten bits still results in a 16 bit input word for every PPI_CLK the upper 6 bits are 0s Likewise a port width of eight bits also results in a 16 bit input word ...

Page 962: ...PACK_EN cleared This is DMA ed to the PPI 0xFACE 0xCAFE This is transferred out through the PPI configured for an 8 bit port width 0xCE 0xFE The FLD_SEL bit is used primarily in the active field only ITU R 656 mode The FLD_SEL bit determines whether to transfer in only field 1 of each video frame or both fields 1 and 2 Thus it allows a savings in DMA bandwidth by transferring only every other fiel...

Page 963: ...be configured before this happens Refer to Frame Synchroniza tion in GP Modes on page 20 19 for more information PPI Status Register PPI_STATUS The PPI_STATUS register shown in Figure 20 14 contains bits that pro vide information about the current operating state of the PPI The ERR_DET bit is a sticky bit that denotes whether or not an error was detected in the ITU R 656 control word preamble The ...

Page 964: ...0 0 0 0 0 0 0 0 0 0 0 0 PPI Status Register PPI_STATUS 0 Field 1 1 Field 2 FT_ERR Frame Track Error W1C OVR FIFO Overflow W1C FLD Field Indicator ERR_DET Error Detected W1C Used only in ITU R 656 modes 0 No preamble error detected 1 Preamble error detected ERR_NCOR Error Not Corrected W1C 0 No interrupt 1 Frame Track Error interrupt occurred Reset 0x0000 Used only in ITU R 656 modes 0 No uncorrect...

Page 965: ...error has occurred These bits are valid for RX modes with recurring frame syncs only If one of these bits is set the programmed number of samples in PPI_COUNT did not match up with the actual number of samples counted between assertions of PPI_FS1 for general purpose modes or start of active video SAV codes for ITU R 656 modes If the PPI error interrupt is enabled in the SIC_IMASK register an inte...

Page 966: ...des except RX mode with 0 frame syncs external trigger and TX mode with 0 frame syncs For RX modes this register holds the number of sam ples to read into the PPI per line minus one For TX modes it holds the number of samples to write out through the PPI per line minus one The register itself does not actually decrement with each transfer Thus at the beginning of a new line of data there is no nee...

Page 967: ...ned as the data bounded between PPI_FS2 assertions regardless of the state of PPI_FS3 A line is defined as a complete PPI_FS1 cycle In these modes PPI_FS3 is used only to determine the original frame start each time the PPI is enabled It is ignored on every subsequent field and frame and its state high or low is not important except during the original frame start If the start of a new frame or fi...

Page 968: ...erted not when PPI_FS2 asserts Also PPI_FS3 is only used to synchronize to the start of the very first frame after the PPI is enabled It is subsequently ignored When using RX mode with three external frame syncs and only two syncs are needed configure the PPI for 3 frame sync operation and provide an external pull down to GND for the PPI_FS3 pin Programming Examples The PPI can be configured to re...

Page 969: ...hannel 0 DMA0_START_ADDR R0 L rx_buffer R0 H rx_buffer P0 L lo DMA0_START_ADDR P0 H hi DMA0_START_ADDR P0 R0 DMA0_CONFIG R0 L DI_EN WNR P0 L lo DMA0_CONFIG P0 H hi DMA0_CONFIG W P0 R0 L DMA0_X_COUNT R0 L 256 P0 L lo DMA0_X_COUNT P0 H hi DMA0_X_COUNT W P0 R0 L DMA0_X_MODIFY R0 L 0x0001 P0 L lo DMA0_X_MODIFY P0 H hi DMA0_X_MODIFY W P0 R0 L ssync config_dma END RTS ...

Page 970: ...PPI_CONTROL P0 L lo PPI_CONTROL P0 H hi PPI_CONTROL R0 L 0x0004 W P0 R0 L ssync config_ppi END RTS Listing 20 3 Enable DMA DMA0_CONFIG P0 L lo DMA0_CONFIG P0 H hi DMA0_CONFIG R0 L W P0 bitset R0 0 W P0 R0 L ssync Listing 20 4 Enable PPI PPI_CONTROL P0 L lo PPI_CONTROL P0 H hi PPI_CONTROL R0 L W P0 bitset R0 0 W P0 R0 L ssync ...

Page 971: ...ference 20 37 Parallel Peripheral Interface Listing 20 5 Clear DMA Completion Interrupt DMA0_IRQ_STATUS P2 L lo DMA0_IRQ_STATUS P2 H hi DMA0_IRQ_STATUS R2 L W P2 BITSET R2 0 W P2 R2 L ssync Unique Information for the ADSP BF50x Processor None ...

Page 972: ...Unique Information for the ADSP BF50x Processor 20 38 ADSP BF50x Blackfin Processor Hardware Reference ...

Page 973: ...iew ADSP BF50x Blackfin processors provide an RSI interface for multimedia cards MMC secure digital memory cards SD secure digital input out put cards SDIO and consumer electronic ATA devices CE ATA All of these storage solutions use similar interface protocols The main difference between MMC and SD support is the initialization sequence The main difference between SD and SDIO support is the use o...

Page 974: ...n Signal recognition and disable for CE ATA device support High capacity card support such as SDHC implemented within software 512 bit transmit receive FIFO DMA channel with 32 bit DMA Access Bus Interface Overview The RSI interface handles the multimedia and secure digital card func tions This includes clock generation power management command transfer and data transfer The bus interface converts...

Page 975: ...TAT flags are enabled by setting the corresponding bit in the RSI_EMASK register and are sent to the SIC via IRQ10 The 32 bit DAB bus allows for efficient transfer of data both to and from internal memory via DMA channel 4 that is shared with the SPORT0 TX The peripheral used by this DMA channel is determined by the peripheral that is enabled via the pin multiplexing The RSI Figure 21 1 is a 10 pi...

Page 976: ... or 8 bit Although multiple MMC cards may be bused together to the single RSI interface it is not possible to bus together an MMC card with an SD or SDIO such that they share the command and or data sig nals Multiple MMC cards bused together respond to CMD1 and CMD2 commands simultaneously using the open drain drivers For other card types broadcast commands with a response must not be issued if th...

Page 977: ...ed Dat6 Bi dir RSI_DATA7 Not Used Not Used Dat7 Not Used Dat7 Bi dir RSI_DATA6 Not Used Not Used Dat6 Not Used Dat6 Bi dir RSI_DATA5 Not Used Not Used Dat5 Not Used Dat5 Bi dir RSI_DATA4 Not Used Not Used Dat4 Not Used Dat4 Bi dir RSI_DATA3 Not Used Card Detect Dat3 Card Detect Dat3 Card Detect Dat3 Dat3 Bi dir RSI_DATA2 Not Used Dat2 Dat2 Dat2 Dat2 Bi dir RSI_DATA1 Not Used Dat1 Dat1 Dat1 Dat1 Bi...

Page 978: ...21 2 RSI Protocol Interface Signal Name SD 1 bit SD 4 bit SDIO 1 bit SDIO 4 bit Direction RSI_DATA7 Not Used Not Used Not Used Not Used Bidirectional RSI_DATA6 Not Used Not Used Not Used Not Used Bidirectional RSI_DATA5 Not Used Not Used Not Used Not Used Bidirectional RSI_DATA4 Not Used Not Used Not Used Not Used Bidirectional RSI_DATA3 Not Used Card Detect Dat3 Card Detect Not Used Card Detect D...

Page 979: ... RSI_CLK Commands responses and data transfers are protected from transmission errors with the use of cyclic redundancy codes CRC A CRC7 code is generated for every command sent by the host and for almost every response returned by the card on the RSI_CMD signal A CRC16 code is used to protect block data transfers sent over the RSI_DATAx signals In 4 and 8 bit bus configurations the CRC16 is calcu...

Page 980: ...identify further supported features such as supported bus widths maximum supported clock frequency and the device capacity At this point the bus width may then be altered and the supplied clock frequency increased Data may be written to the device or read from the device using the following two methods Stream reads and writes Block reads and writes Stream transfers result in a continual stream of ...

Page 981: ... Clock Configuration The RSI is a fast synchronous peripheral with a programmable clock fre quency that is supplied via the RSI_CLK signal The interface between the RSI and the PAB DAB busses operates at SCLK frequency Communica tion between the clock domain that is supplied externally from the RSI on the RSI_CLK signal and the internal RSI access to the PAB and DAB busses is accomplished using sy...

Page 982: ... mode During the card identification mode this signal operates in open drain configuration however upon the cards entry to data transfer mode the signal is then configured to push pull mode The internal pull up resistor of the RSI_CMD signal is only intended to keep the signal from floating The internal pull up resistor is not sufficient during the card identification phase when the MMC card RSI_C...

Page 983: ...t this card detection can be performed SD and SDIO cards use an internal pull up resistor on the RSI_DATA3 line as a card detect signal to indicate to the host that a card is present In order to use the RSI_DATA3 signal for card detection an external pull down resistor should be added to the pin in order to pull the pin low during the time a card is not inserted When a card is inserted into the sl...

Page 984: ...MMC devices may not implement the card detect pull up resistor on the RSI_DATA3 signal Once a card is detected the GPIO pin can have the interrupt level inverted to then generate an interrupt on card removal The final approach to detecting the insertion and removal of a card is to simply use software polling Software would poll the slot periodically using the card identification commands for the s...

Page 985: ...rface RSI_CLK RSI_CMD RSI_DATA0 RSI_DATA1 RSI_DATA2 RSI_DATA3 RSI_DATA4 RSI_DATA5 RSI_DATA6 RSI_DATA7 RSI INTERFACE GPIO GPIO SD MMC SOCKET CLK CMD DATA0 DATA1 DATA2 DATA3 DATA4 DATA5 DATA6 DATA7 CARD DETECT WRITE PROTECT 3 3V REQUIRED FOR MMC CARD SUPPORT REQUIRED ONLY IF USING CARD DETECTION VIA DATA3 SIGNAL ...

Page 986: ...ignal can be enabled or disabled via CLK_EN in the RSI_CLK_CONTROL register and a power save fea ture is implemented via PWR_SV_EN that allows for the disabling of the RSI_CLK output when there are no transfers taking place on the RSI inter face providing additional power saving options Table 21 3 RSI Power Saving Configurations CLKS_EN CLK_EN PWR_SV_E RSI State RSI_CLK output 0 0 0 Disabled No cl...

Page 987: ...e or use the argument field based on the command that is received The argument sent with the command is provided via the RSI_ARGUMENT register see RSI Argument Register RSI_ARGUMENT on page 21 57 All command transfers are protected by a 7 bit cyclic redundancy check CRC code more commonly referred to as a CRC7 checksum This allows for transmission errors to be detected and the command to be re iss...

Page 988: ...t bit 46 1 0 Transmitter bit 45 40 6 Command index or check bits1 1 Responses that do not contain the command index have a check bits field that contains 111111 39 8 32 Card status register contents or argument field 7 1 7 CRC7 checksum or check bits2 2 Responses that do not contain a CRC7 checksum have a check bits field that contains 1111111 0 1 1 End bit Table 21 6 RSI Long Response Format Bit ...

Page 989: ...9 of the response corresponds to bit 31 of RSI_RESPONSE0 and bit 8 of the response to bit 0 of RSI_RESPONSE0 Bits 45 40 of the response are stored to the RESP_CMD field of the RSI_RESP_CMD register For a long response bits 127 1 of the response are stored in RSI_RESPONE0 3 where bit 31 of RSI_RESPONSE0 contains the most significant bit bit 127 of the response and bit 0 of RSI_RESPONSE3 contains bi...

Page 990: ...N CMD_EN RSI_CLK_EN CMD_EN CMD_PEND_EN PEND DAT_END SEND CMD_RSP RSI_CLK_EN RSI_RST RSI_CLK_EN RSI_RST CMD_SENT RSI_CLK_EN RSI_RST CMD_TIMEOUT RSI_CLK_EN RSI_RST CMD_CRC_FAIL CMD_RESP_END RSI_CLK_EN RSI_RST CEATA_INT_DET CEATA_INT_DIS CEATA_TX_CCSD CEATA_INT_WAIT CEATA_EN CEATA_INT_EN RECEIVE CMD_TIMEOUT CMD_INT_EN INTERRUPT REQUEST FROM CARD WAIT ...

Page 991: ...is sampled by the card and the host on the rising edge of RSI_CLK The following sections describes the RSI command path states Table 21 7 RSI Command Path Status Flags RSI_STATUS Flag Description State Flag Set in CMD_ACT Command transfer is in progress WAIT_S CMD_SENT Command without response sent successfully SEND CMD_TIMEOUT Response timeout occurred 64 RSI_CLK cycles WAIT_S CMD_CRC_FAIL Respon...

Page 992: ...er to allow the card to complete the current operation Only after the eight RSI_CLK cycles have passed will the state machine leave the IDLE state if enabled again PEND State The PEND state is entered if the CMD_PEND_EN bit is set within RSI_COMMAND The state machine remains in the PEND state until it is notified by the data path sub block that a data transfer has completed This is indicated by th...

Page 993: ...ed by the 0 start bit on the RSI_CMD signal the RSI transitions to the RECEIVE state to receive a 48 or 136 bit response The WAIT state is also capable of detecting card interrupts This is an optional feature that applies only to MMC cards This feature is enabled by setting the CMD_INT_EN bit within RSI_COMMAND When CMD_INT_EN is set the timeout timer that is normally started upon entry to the WAI...

Page 994: ... indicated by the device sending a 0 on the RSI_CMD signal Upon detection of the command completion sig nal the CMD_ACT flag is cleared and the CEATA_INT_DET flag of the RSI_ESTAT register is set Alternatively the command completion signal of the CE ATA device can be disabled by the RSI This action is performed by setting the CEATA_TX_CCSD bit of the RSI_CEATA_CONTROL register at which point the s...

Page 995: ...ents field for the long response format Note that the start bit transmitter bit and the six check bits are not used in the CRC calculation for the long response The command and response CRC checksum is a 7 bit value that is calculated as follows with and for a short response or for a long response RSI Data Data transfers both to and from the RSI take place over the RSI data bus signals RSI_DATA7 0...

Page 996: ...ency The state machine becomes enabled and leaves the IDLE state when the DATA_EN field of RSI_DATA_CONTROL is set enabling the data transfer The state entered upon leaving the IDLE state is determined by DATA_DIR The data path state machine is shown in Figure 21 5 Figure 21 5 RSI Data Path State Machine IDLE DATA_EN DATA_DIR DATA_EN DATA_DIR WAIT_S WAIT_R START_BIT_ERR DAT_TIMEOUT RX_DAT_ZERO DAT...

Page 997: ...if CRC token indicates failure Data block CRC failed on receive RECEIVE DAT_TIMEOUT Transmit timeout occurred before card deasserted busy signal on RSI_DATA0 BUSY Receive timeout error occurred before start bit of data detected WAIT_R DAT_END All data sent SEND All data received RECEIVE START_BIT_ERR Start bit not detected on all RSI_DATAx signals WAIT_R TX_FIFO_STAT Transmit FIFO is half empty SE...

Page 998: ...FO becomes empty and data is not available in the FIFO by the time the next transfer is due to take place the TX_UNDERRUN flag is set before returning to the IDLE state In block transfer mode DATA_BLK_LGTH bytes are transmitted as specified during the write to RSI_DATA_CONTROL each byte transferred also results in the decrementing of RSI_DATA_CNT Upon completion of the block trans fer the RSI appe...

Page 999: ...where it then either returns to IDLE if all data has been sent or it moves back to the SEND state to start another block transfer If the RSI timeout counter expires before the RSI_DATA0 signal is detected high the RSI sets the DAT_TIMEOUT flag and returns to the IDLE state RSI Data Receive Path The receive path consists of the WAIT_R and the RECEIVE states Before enabling the data path state machi...

Page 1000: ...f the receive FIFO the RX_DAT_ZERO flag is set and the state transitions to the IDLE state If at any time during the receive state the data FIFO becomes full and data has not been read from the FIFO prior to the next byte being written to the FIFO the RX_OVERRRUN flag is set and the state transitions to the WAIT_R state then onto the IDLE state In block transfer mode the received data is packed in...

Page 1001: ...alue calculates as follows with where RSI Data FIFO The data FIFO is a 32 bit wide 16 word deep data buffer with transmit and receive logic The FIFO is configuration depends on the state of the TX_ACT and RX_ACT flags If TX_ACT is set the FIFO operates as a transmit FIFO supplying data to the RSI for transfer to the card The RX_ACT flag configures the FIFO as a receive FIFO whereby the RSI writes ...

Page 1002: ...ng the data transfer the receive logic maintains the receive FIFO status flags shown in Table 21 10 Table 21 9 RSI Transmit FIFO Status Flags RSI_STATUS Flag Description TX_FIFO_STAT Transmit FIFO is half empty TX_FIFO_FULL Transmit FIFO is full TX_FIFO_EMPTY Transmit FIFO is empty TX_UNDERRUN Transmit FIFO under run error TX_DAT_RDY Valid data available in the transmit FIFO Table 21 10 RSI Receiv...

Page 1003: ...ue operations The SDIO device sends an interrupt request to the RSI by asserting the RSI_DATA1 signal low The interrupt status is indicated by the SDIO_INT_DET bit of the RSI_ESTAT register The status can be configured to generate an interrupt on the processor via the SDIO_INT_DET_MASK bit of the RSI_EMASK register When the RSI is configured for a 1 bit bus width the interrupt may be generated by ...

Page 1004: ...quency must be no greater than 400 kHz SD Card Identification Procedure The SD card identification procedure is as follows 1 Issue the IDLE command to the card via the RSI_COMMAND register 2 Issue the SEND_IF command to the card via the RSI_COMMAND reg ister supplying the host supply voltage and a check pattern via the RSI_ARGUMENT register The command expects an R7 response type If a valid respon...

Page 1005: ...rts high capacity cards verify whether the response in RSI_RESPONSE0 indicates the card capacity status CCS bit is set If CCS is set an SD Version 2 00 or later high capacity SD memory card is present proceed to step 6 If the CCS bit is cleared the card is an SD Version 2 00 or later standard capacity memory card proceed to step 6 5 Issue the RSI_SEND_OP_COND command via the RSI_COMMAND regis ter ...

Page 1006: ...RSI_COMMAND register supplying the operating voltage window that the host is compatible with and the access mode that the host supports byte or sector via the RSI_ARGUMENT register The RSI expects an R3 type response This allows the host to reject the card if it is not compatible with the supply voltage or if the access mode is not sup ported by the host software If the card returns an indication ...

Page 1007: ...be configured for the same block size at all times The block length of the RSI is configured via the DATA_BLK_LGTH field of the RSI_DATA_CONTROL register It is important to pay attention as to when the data path state machine is enabled and when data is written to the FIFO for trans fer to the card Write transactions require that data be written after the response has completed for the WRITE_BLOCK...

Page 1008: ..._STATUSCL register 4 Ensure that the device is not busy and no errors occurred by verifying the response contained in RSI_RESPONSE0 5 Write the number of bytes to be transferred to the RSI_DATA_LGTH register This will be 512 bytes for a single block 6 Write the appropriate timeout value for a write operation to the RSI_DATA_TIMER register 7 Write the destination start address to the RSI_ARGUMENT r...

Page 1009: ...e FIFO is not full or write data in blocks of eight 32 bit words if polling on the TX_FIFO_STAT bit indicating the transmit FIFO is half empty Con tinue until all 128 32 bit words 512 bytes have been transferred 12 Wait for the card to respond with the CRC token by waiting for the DAT_BLK_END flag to be set DAT_END will also be set at this time if the RSI_DATA_LGTH register was set to 512 bytes in...

Page 1010: ...be transferred to the RSI_DATA_LGTH register This will be 512 bytes for a single block 7 Write the appropriate timeout value for a write operation to the RSI_DATA_TIMER register 8 Write the destination start address to the RSI_ARGUMENT register The address supplied must be aligned to a 512 byte boundary if misaligned accesses are not enabled and the card is not a high capacity SD card or sector ad...

Page 1011: ...support other block lengths or the default block length as specified in the CID register is not 512 the block length of the RSI must be configured accordingly The block length of the card and the block length of the RSI must be configured for the same block size at all times The block length of the RSI is configured via the DATA_BLK_LGTH field of the RSI_DATA_CONTROL register It is important to pa...

Page 1012: ... Core The procedure is as follows 1 Write the RSI_ARGUMENT register with the cards RCA The 16 bit RCA should be written to the upper 16 bits of the RSI_ARGUMENT register 2 Write the RSI_COMMAND register with the SELECT DESELECT_CARD command configuring the command path state machine to expect a short response by setting CMD_RESP and clearing CMD_L_RESP The response type is R1b 3 Wait for the CMD_R...

Page 1013: ...ing CMD_RESP and clearing CMD_L_RESP The response type is R1 10 In order to meet some timing restrictions related to block read operations it is advisable to not wait for the CMD_RESP_END indica tion within the RSI_STATUS register but instead move immediately on the next step This is due to the card being able to send data before a response can completed on the RSI_CMD signal moving immediately on...

Page 1014: ...red by verifying the response contained in RSI_RESPONSE0 5 Configure the DMA channel assigned to the RSI controller Write DMAx_START_ADDR with the address of the first byte of where the received data is to be stored The DMAx_X_COUNT register should be set to 128 and the DMAx_X_MODIFY register to 4 The DMAx_CONFIG register should be set for DMA enable a word size of 32 bits and direction set to mem...

Page 1015: ...ected via the RSI_STATUSCL register The DMA controller enabled in step 5 will ensure any data sent to the receive FIFO prior to the CMD_RESP_END flag being set is received correctly 12 Wait for the DAT_BLK_END flag to indicate that the data was received correctly and passed the CRC check The DAT_END flag may also be set depending on the value written to RSI_DATA_LGTH 13 Clear the DAT_BLK_END and D...

Page 1016: ...CL register 4 Ensure that the device is not busy and no errors occurred by verifying the response contained in RSI_RESPONSE0 5 Write the number of bytes to be transferred to the RSI_DATA_LGTH register For example write 4096 to write eight blocks of 512 bytes 6 Write the appropriate timeout value for a write operation to the RSI_DATA_TIMER register 7 Write the destination start address to the RSI_A...

Page 1017: ...f the RSI_STATUS register Continue to write data to the FIFO as long as the FIFO is not full or write data in blocks of eight 32 bit words if polling on the TX_FIFO_STAT bit indicating the transmit FIFO is half empty Con tinue until all 128 32 bit words 512 bytes have been transferred 12 Wait for the card to respond with the CRC token by waiting for the DAT_BLK_END flag to be set 13 Clear the DAT_...

Page 1018: ...sure that the device is not busy and no errors occurred by verifying the response contained in RSI_RESPONSE0 5 Configure the DMA channel assigned to the RSI controller Write DMAx_START_ADDR with the address of the first byte of data to be written to the card The DMAx_X_COUNT register should be set to the overall number of 32 bit words to be written for example write 1024 to transfer 4096 bytes The...

Page 1019: ...DATA_CONTROL register with DATA_BLK_LGTH set to 9 for a 512 byte block DATA_EN and DATA_DMA_EN should also be set to enable the data path state machine and to allow the DMA control ler to access the transmit FIFO All other fields of the RSI_DATA_CONTROL register should be zero 12 Poll for the DAT_END flag or alternatively poll for each instance of the DAT_BLK_END flag that will be set on successfu...

Page 1020: ... the RSI_ARGUMENT register with the cards RCA The 16 bit RCA should be written to the upper 16 bits of the RSI_ARGUMENT register 2 Write the RSI_COMMAND register with the SELECT DESELECT_CARD command configuring the command path state machine to expect a short response by setting CMD_RESP and clearing CMD_L_RESP The response type is R1b 3 Wait for the CMD_RESP_END indication within the RSI_STATUS ...

Page 1021: ...mand path state machine to expect a short response by setting CMD_RESP and clearing CMD_L_RESP The response type is R1 10 In order to meet some timing restrictions related to block read operations it is advisable to not wait for the CMD_RESP_END indica tion within the RSI_STATUS register but instead move immediately on the next step This is due to the card being able to send data before a response...

Page 1022: ...e written to the upper 16 bits of the RSI_ARGUMENT register 2 Write the RSI_COMMAND register with the SELECT DESELECT_CARD command configuring the command path state machine to expect a short response by setting CMD_RESP and clearing CMD_L_RESP The response type is R1b 3 Wait for the CMD_RESP_END indication within the RSI_STATUS register and clear the status bit once detected via the RSI_STATUSCL ...

Page 1023: ...ard 9 Enable the data path state machine by writing to the RSI_DATA_CONTROL register with DATA_BLK_LGTH set to 9 for a 512 byte block DATA_EN DATA_DIR and DATA_DMA_EN should also be set to enable the data path state machine Set the transfer direc tion from card to controller and allow the DMA controller access to the receive FIFO All other fields of the RSI_DATA_CONTROL regis ter should be zero 10...

Page 1024: ... The response type is R1 14 Clear the DAT_END and CMD_RESP_END flags via the RSI_STATUSCL register Also clear the DMA_DONE bit of the DMAx_IRQ_STATUS register if applicable RSI Registers Table 21 11 summarizes the RSI registers together with their function memory mapped address type and access Table 21 11 RSI Module Registers Register Name Function Address Type Access RSI_PWR_CONTROL RSI power con...

Page 1025: ...atus register on page 21 65 0xFFC03834 R 32 bit RSI_STATUSCL RSI status clear register on page 21 68 0xFFC03838 W1A 16 bit RSI_MASK0 RSI_MASK1 RSI IRQ0 mask registers on page 21 70 0xFFC0383C 0xFFC03840 R W 32 bit RSI_FIFO_CNT RSI FIFO counter register on page 21 73 0xFFC03848 R 16 bit RSI_CEATA_CONTROL RSI CE ATA control register on page 21 74 0xFFC0384C R W1A W 16 bit RSI_FIFO RSI data FIFO regi...

Page 1026: ...f operation is push pull After a data write data cannot be written to this register for a five SCLK cycles RSI_RD_WAIT_EN RSI read wait enable register on page 21 80 0xFFC038CC R W1A W 16 bit RSI_PID0 RSI_PID1 RSI_PID2 RSI_PID3 RSI peripheral identifica tion registers on page 21 81 0xFFC038D0 0xFFC038D4 0xFFC038D8 0xFFC038DC R 16 bit Figure 21 6 RSI Power Control Register Table 21 11 RSI Module Re...

Page 1027: ...d without dis abling the entire RSI interface via the CLK_EN bit additionally the PWR_SV_EN bit when set results in the RSI_CLK signal only been driven when the RSI is performing a transfer either to or from the card In addi tional to clock control functionality the data bus width of the RSI interface is also controlled from this register Table 21 12 RSI_PWR_CONTROL Register Bit Name Function Type...

Page 1028: ...RSI_CLK always driven 1 Enabled RSI_CLK only enabled when bus is active R W 0 10 CLKDIV_BYPASS Bypass clock divisor 0 Disabled do not bypass clock divisor 1 Enabled RSI_CLK derived directly from SCLK R W 0 12 11 BUS_MODE Data bus width 00 1 bit data bus 01 4 bit data bus 10 8 bit data bus 11 Reserved R W 0 15 13 Reserved Reserved RO 0 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 ...

Page 1029: ...ling the command path state machine The CMD_IDX field contains the index of the command to be issued via the RSI as part of the command message If the command requires a response this is indicated via CMD_RSP_EN The length of the response short or long is controlled with CMD_LRSP_EN The command path state machine becomes active once the CMD_EN bit is set and is disabled if this bit is cleared Figu...

Page 1030: ...DX Command index 0x3F 0x00 Command number to be issued R W 0 6 CMD_RSP_EN Wait for response 0 Disabled 1 Enabled R W 0 7 CMD_LRSP_EN Long response enable 0 Disabled short response expected 1 Enabled long response expected R W 0 8 CMD_INT_EN Command interrupt enable 0 Disabled timeout after 64 RSI_CLK cycles 1 Enabled disable timeout counter and wait for interrupt R W 0 Reserved 15 14 13 12 11 10 9...

Page 1031: ... likely contain 0x3F which is the value of the reserved field of the response 9 CMD_PEND_EN Pend enable 0 Disabled send command immediately 1 Enabled wait for DAT_END before sending command R W 0 10 CMD_EN Command enable 0 Disable command path state machine 1 Enable command path state machine R W 0 15 11 Reserved Reserved RO 0 Figure 21 10 RSI Response Command Register Table 21 14 RSI_COMMAND Regi...

Page 1032: ...SE0 register Bit 0 of RSI_RESPONSE3 is always zero Table 21 16 shows the RSI response reg isters contents for the two types of responses Table 21 15 RSI_RESP_CMD Register Bit Name Function Type Default 5 0 RESP_CMD Command index of last received response 0x3F 0x00 command index RO 0 15 6 Reserved Reserved RO 0 Figure 21 11 RSI Response Registers RSI Response 15 0 RSI Response 31 16 0 31 30 29 28 2...

Page 1033: ...ior to starting a data transfer via the RSI_DATA_CONTROL register Table 21 16 RSI Response Registers Content Response Register Short Response Long Response RSI_RESPONSE0 Response bits 31 0 Response bits 127 96 RSI_RESPONSE1 Not used Response bits 95 64 RSI_RESPONSE2 Not used Response bits 63 32 RSI_RESPONSE3 Not used Response bits 31 1 1 1 Bits 31 1 of the long response are stored in bits 30 0 of ...

Page 1034: ...is determined by DATA_DIR If the DMA channel is to be used for the data transfer the DATA_DMA_EN bit must be set otherwise the RSI FIFO is only accessible via the core For block transfers the block length must be specified via DATA_BLK_LGTH where the block length is 2DATA_BLK_LGTH Two bits CEATA_CCS_EN and CEATA_EN in this register configure the behavior of the command path state machine for commu...

Page 1035: ...I R W 0 2 DATA_MODE Data transfer mode 0 Block transfer 1 Stream transfer R W 0 3 DATA_DMA_EN Data DMA enable 0 Disabled use core to read write RSI_FIFO 1 Enabled use DMA controller to read write RSI_FIFO R W 0 7 4 DATA_BLK_LGTH Data block length 0x0 0xC data block length 20 to 212 R W 0 8 CEATA_EN CE ATA mode enable 0 Disabled 1 Enabled R W 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 ...

Page 1036: ...the IDLE state and the DAT_END flag of the RSI_STATUS register is set 9 CEATA_CCS_EN Command completion signal enable 0 Disabled 1 Enabled wait for command completion signal R W 0 15 10 Reserved Reserved R W 0 Figure 21 15 RSI Data Counter Register Table 21 19 RSI_DATA_CNT Register Bit Name Function Type Default 15 0 DATA_COUNT Number of bytes still to be trans ferred RO 0 Table 21 18 RSI_DATA_CON...

Page 1037: ...pending on the state of the FIFO and whether the FIFO is currently enabled for a transmit or receive operation Figure 21 16 RSI Status Register 0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 0 1 0 1 0 1 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RX_FIFO_STAT RSI Status Register RSI_STATUS CMD_CRC_FAIL Read Reset 0x0000 0000 0xFFC0 3834 RX_ACT TX_FIFO...

Page 1038: ...mand timeout 0 Command response not timed out 1 Command response timed out RO 0 3 DAT_TIMEOUT Data timeout 0 Data not timed out 1 Data timed out RO 0 4 TX_UNDERRUN Transmit FIFO underrun error 0 No error 1 Underrun error RO 0 5 RX_OVERRUN Receive FIFO overrun error 0 No error 1 Overrun error RO 0 6 CMD_RESP_END Command response received 0 No response received 1 Response received and CRC passed RO ...

Page 1039: ...nsmit in progress 1 Data transmit in progress RO 0 13 RX_ACT Data receive active 0 No data receive in progress 1 Data receive in progress RO 0 14 TX_FIFO_STAT Transmit FIFO watermark 0 No FIFO watermark detected 1 Transmit FIFO half empty RO 0 15 RX_FIFO_STAT Receive FIFO watermark 0 No FIFO watermark detected 1 Receive FIFO half full RO 0 16 TX_FIFO_FULL Transmit FIFO full 0 Not full 1 Transmit F...

Page 1040: ...1 Data available in transmit FIFO RO 0 21 RX_FIFO_RDY Receive data available 0 No data 1 Data available in receive FIFO RO 0 31 22 Reserved Reserved RO 0 Figure 21 17 RSI Status Clear Register Table 21 20 RSI_STATUS Register Cont d Bit Name Function Type Default 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reserved RSI Status Clear Register RSI_STATUSCL CMD_CRC_FAIL_STAT W...

Page 1041: ...CMD_TIMEOUT W1A 0 3 DAT_TIMEOUT_STAT Clear data timeout 0 No effect 1 Clear DAT_TIMEOUT W1A 0 4 TX_UNDERRUN_STAT Clear transmit FIFO underrun error 0 No effect 1 Clear TX_UNDERRUN W1A 0 5 RX_OVERRUN_STAT Clear receive FIFO overrun error 0 No effect 1 Clear RX_OVERRUN W1A 0 6 CMD_RESP_END_STAT Clear command response received 0 No effect 1 Clear CMD_RSEP_END W1A 0 7 CMD_SENT_STAT Clear command sent ...

Page 1042: ...ailable RSI interrupts An interrupt is enabled by setting the corresponding bit in the RSI_MASKx register to 1 Interrupts enabled in the RSI_MASK0 register will result in an IRQ being sent via the IRQ0 signal of the RSI and interrupts enabled in the RSI_MASK1 register generate an IRQ on the IRQ0 signal of the RSI 10 DAT_BLK_END_STAT Clear data block end 0 No effect 1 Clear DAT_BLK_END W1A 0 15 11 ...

Page 1043: ...4 23 22 21 20 19 18 17 16 0 0 1 0 1 0 1 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RX_FIFO_STAT_MASK RSI Interrupt Mask Registers RSI_MASKx CMD_CRC_FAIL_MASK Read Write Reset 0x0000 0000 RX_ACT_MASK TX_FIFO_STAT_MASK DAT_CRC_FAIL_MASK CMD_TIMEOUT_MASK DAT_TIMEOUT_MASK TX_UNDERRUN_MASK TX_ACT_MASK CMD_ACT_MASK DAT_BLK_END_MASK START_BIT_ERR_MASK DAT_END_MA...

Page 1044: ...W 0 7 CMD_SENT_MASK Command sent 0 Disable interrupt 1 Enable interrupt R W 0 8 DAT_END_MASK End of data 0 Disable interrupt 1 Enable interrupt R W 0 9 START_BIT_ERR_MASK Start bit error 0 Disable interrupt 1 Enable interrupt R W 0 10 DAT_BLK_END_MASK Data block end 0 Disable interrupt 1 Enable interrupt R W 0 11 CMD_ACT_MASK Command active 0 Disable interrupt 1 Enable interrupt R W 0 12 TX_ACT_MA...

Page 1045: ...t 1 Enable interrupt R W 0 15 RX_FIFO_STAT_MASK Receive FIFO watermark 0 Disable interrupt 1 Enable interrupt R W 0 16 TX_FIFO_FULL_MASK Transmit FIFO full 0 Disable interrupt 1 Enable interrupt R W 0 17 RX_FIFO_FULL_MASK Receive FIFO full 0 Disable interrupt 1 Enable interrupt R W 0 18 TX_FIFO_ZER W_MASK Transmit FIFO empty 0 Disable interrupt 1 Enable interrupt R W 0 19 RX_DAT_ZER W_MASK Receive...

Page 1046: ...ne the CCSD signal will automatically be sent after the response is received from the CE ATA device and the command path state machine will return to the IDLE state Figure 21 19 RSI FIFO Counter Register Table 21 23 RSI_FIFO Register Bit Name Function Type Default 14 0 FIFO_COUNT Number of 32 bit words remain ing RO 0 15 Reserved Reserved RO 0 Figure 21 20 RSI CE_ATA Control Register 15 14 13 12 1...

Page 1047: ...I_EMASK register All bits in this register are write 1 to clear bits The SDIO interrupt is an interrupt generated by SDIO cards on the RSI_DATA1 signal The SD_CARD_DET bit is set when a Table 21 24 RSI_CEATA_CONTROL Register Bit Name Function Type Default 0 CEATA_TX_CCSD Transmit command comple tion signal disable 0 No action 1 Send command comple tion signal disable sequence R W1A W 0 15 Reserved...

Page 1048: ...1 22 RSI Exception Status Register Table 21 25 RSI_ESTAT Register Bit Name Function Type Default 0 Reserved Reserved RO 0 1 SDIO_INT_DET SDIO interrupt detect 0 No interrupt detected 1 Interrupt detected R W1C 0 3 2 Reserved Reserved RO 0 4 SD_CARD_DET Card detect interrupt 0 No interrupt detected 1 Interrupt detected R W1C 0 5 CEATA_INT_DET Command completion signal detect 0 No CCS detected 1 CCS...

Page 1049: ...ult 0 Reserved Reserved R W 0 1 SDIO_INT_DET_MASK SDIO interrupt enable 0 Interrupt disabled 1 Interrupt enabled R W 0 3 2 Reserved Reserved R W 0 4 SD_CARD_DET_MASK Card detect interrupt enable 0 Interrupt disabled 1 Interrupt enabled R W 0 5 CEATA_INT_DET_MASK Command completion signal detect enable 0 Interrupt disabled 1 Interrupt enabled R W 0 15 6 Reserved Reserved RO 0 15 14 13 12 11 10 9 8 ...

Page 1050: ...nly when the corresponding GPIO pins are configured for RSI functionality via the pin multiplexing For exam ple if only the 4 bit data bus is enabled in the pin multiplexing setting PU_DAT will only enable the pull up resistors on the signals that are config ured for RSI use The RSI_CONFIG register also provides additional functionality for SDIO support To enable SDIO 4 bit mode in addition to set...

Page 1051: ...le SDIO 4 bit mode R W 0 3 MW_EN SDIO interrupt moving window enable 0 Disabled 1 Enabled required when using SDIO multi ple block read operations R W 0 4 RSI_RST RSI reset 0 No action 1 Reset the RSI R W 0 5 PU_DAT Pull up enable 0 Disable pull up resistor on RSI_DATA7 4 and RSI_DATA2 0 1 Enable pull up resistor on RSI_DATA7 4 and RSI_DATA2 0 R W 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 ...

Page 1052: ...l up resistor on RSI_DATA3 R W 0 7 PD_DAT3 RSI_DATA3 pull down enable 0 Disable pull down resistor on RSI_DATA3 1 Enable pull down resistor on RSI_DATA3 For more system flexibility no internal pull down resistor is present An external pull down resistor is required for card detection capability on the RSI_DATA3 signal R W 0 15 8 Reserved Reserved RO 0 Figure 21 25 RSI Read Wait Enable Register Tab...

Page 1053: ...four registers are listed in Table 21 30 Table 21 28 RSI_RD_WAIT_EN Register Bit Name Function Type Default 0 SDIO_RWR RSI read wait request enable 0 Normal operation 1 Issue read wait request to SDIO device R W1A W 0 15 1 Reserved Reserved RO 0 Figure 21 26 RSI Peripheral ID Registers Table 21 29 RSI_PIDx Registers Bit Name Function Type Default 7 0 RSI_PID Peripheral ID RO 0 15 8 Reserved Reserv...

Page 1054: ...RSI Registers 21 82 ADSP BF50x Blackfin Processor Hardware Reference Table 21 30 Peripheral IDs RSI Peripheral ID Register RSI_PID Value RSI_PID0 0x80 RSI_PID1 0x11 RSI_PID2 0x04 RSI_PID3 0x00 ...

Page 1055: ...r SPORT1 ADSP BF50x processors do not sup port ACM operation with SPI The traditional approach to sampling has the following limiting factors ADC sampling instances are not precisely controlled due to vari able interrupt latencies or instruction execution cycles Consumption of processor MIPS can be prohibitive especially for high frequency of conversion related events The ACM avoids the limitation...

Page 1056: ...2 2 observe that the con nections differ between ADSP BF50x processors that include an internal ADC versus the processors that do not include an internal ADC Figure 22 1 ADSP BF504F ACM Connections for External ADC SPORTx DRxSEC DRxPRI RCLKx RFSx ADC EXTERNAL DOUTB DOUTA SCLK CS RANGE SGL DIFF A 2 0 ACM CS ACLK ACM_RANGE ACM_SGLDIFF ACM_A 2 0 TRIGGER 3 0 ADSP BF504 ADSP BF504F SPORT SELECT MUX ...

Page 1057: ...al of 16 event register pairs determine the ADC controls and timing for each ADC sampling interval Each event register pair consists of an event control register ACM_ERx and an event time register ACM_ETx The ACM_ERx register enables a particular event and determines settings for the ADC controls A 2 0 RANGE SGL DIFF and others for that particular ADC conversion The ACM_ETx register determines the...

Page 1058: ... ADC Channel Select 3 bit ADC Channel select signal ACM_RANGE O Range Selector ACM_SGLDIFF O Mode Single Ended Differential Mode selector TRIGGER 3 0 I Trigger Inputs Generated from external trigger events CS O Start of Conversion Chip select for ADC and connected as Frame Sync for SPORT ACLK O ADC Clock Clock output for ADC and SPORT ...

Page 1059: ...ACM Figure 22 3 shows the ACM Block diagram Figure 22 3 ACM Block Diagram Event Registers Event Registers ACMTMR0 32 Bit ACMTMR1 32 Bit 16 Time Comparators Pending Event FIFO Timing Generation Unit CLK Divider A 2 0 CS RANGE SGLDIFF ACLK SCLK Triggers TRIG_SEL0 TRIG_SEL1 2 2 ...

Page 1060: ...he same time the ACM_ER0 7 and ACM_ET0 7 event register pairs are associated with ACMTMR0 and the ACM_ER8 15 and ACM_ET8 15 event register pairs are associated with ACMTMR1 If only one timer is enabled all of the event registers are associ ated with that particular timer For example if only ACMTMR1 is enabled if ACMTMR0EN 0 and ACMTMR1EN 1 the ACM_ER0 15 and ACM_ET0 15 event register pairs are ass...

Page 1061: ...TRIGGER2 Port F GPIO at PF10 or TMR2 When the Port F PF10 pin is configured in function mode non GPIO mode then the ACM trigger input 2 is sourced from the output of TMR2 When the Port F PF10 pin is configured in GPIO mode then the ACM trigger input 2 is sourced from the GPIO signal at PF10 The source of the GPIO signal may be either internal or external depending on the GPIO direction configura t...

Page 1062: ...ns the minimum pulse width for such trigger sources needs to be 1 SCLK period 1 ns Figure 22 4 ACM Trigger Logic ACM PWM0 PWM1 TMR GPIO Is PG5 or PF10 configured in output GPIO mode Is PG5 or PF10 configured in input GPIO mode Is PG5 or PF10 configured in timer function mode Is PWM1 configured for internal sync generation Is PWM0 configured for internal sync generation 0 0 PG5 and PF10 pin inputs ...

Page 1063: ...mine when an enabled event should happen The comparators compare the event time with the corre sponding timer count If the time value matches the comparators signal an active event signal to the timing generation unit If more than one event is active during the same SCLK cycle only the highest priority event is processed and all other events are missed even if there was space in the pending event ...

Page 1064: ...ated only after the entire event completes externally for example when CS goes inactive TH period and TZ periods are completed for that particular event The ACM_ES register provides the status of each event indicating which event created the interrupt and the event completion interrupt can be cleared by writing to the relevant W1C bit in the ACM_ES register The ACM_MS register provides the status ...

Page 1065: ...C power down mode of the inter nal ADC and external ADCs that support a similar power down mechanism may be achieved by issuing a dummy ADC event or events after appropriately programming the TCSW field in the ACM_TC register Single Shot Sequencing Mode Emulation In single shot sequencing mode all enabled events are sequentially issued one after the other on the occurrence of an ACM trigger The se...

Page 1066: ...events and program the event time values as Event 0 time X Event 1 time X Y Event 2 time X 2Y where X ETIME0 the initial time offset from trigger if needed Y TH TCSW TS TZ Where TH is the hold time TZ is the zero t time and TS is the setup time for more information see ACM External Pin Timing on page 22 20 and Figure 22 9 on page 22 20 Y has to be slightly less than the above value to ensure that ...

Page 1067: ...quent triggers after the first active edge of the trigger are neglected Figure 22 6 shows an example of continuous sequencing mode with only two events event 0 event 1 enabled Figure 22 6 does not exactly reflect exact internal ACM operation It shows the user requirement to sample the ADC based on events in a particular sequence Figure 22 6 Continuous Sequencing Mode Requirement SCLK Trigger ACM_T...

Page 1068: ...imer time period N Y where N number of enabled events Y TH TCSW TS TZ Y should be exactly equal here For more information on ACM triggers refer to Interface Overview on page 22 3 Continuous sequencing may also be implemented without the use of the general purpose timers TMR2 or TMR7 but through the use of general purpose I O GPIO pin This may be achieved by using a GPIO as a trig ger and by enabli...

Page 1069: ...ent time ACM_ETx for an event associated with the timer the compara tors generate an event signal to the timing generation unit to start the ADC access The counter continues counting and for each matching and enabled event the ACM gives an event signal to the timing generation unit Figure 22 7 shows the ACM operation where only two events event 0 and event 3 are enabled In Figure 22 7 the line lab...

Page 1070: ...me event time values for example the value in ACM_ET0 is equal to the value in ACM_ET3 the events are processed accord ing to their priorities Event 0 has the highest priority So when event 0 and event 3 share the same event time value the timing generation unit processes event 0 while event 3 is missed The event 3 missed EM3 sta tus bit is set in the missed event status register ACM_MS and the EM...

Page 1071: ...ents that are triggered by both timers ACMTMR0 and ACMTMR1 occurs simultaneously the events triggered by ACMTMR0 are given higher priority For example when an ACMTMR0 event one of events 0 through 7 and ACMTMR1 event one of events 8 through 15 occur simultaneously the ACMTMR0 event is processed by the timing generation unit or is queued in the pending event FIFO before the processing or the queuin...

Page 1072: ...programmed in ACM_TC register TED 1 SCLK This predictable latency is applies only when the timing generation unit is idle If the timing generation unit was processing a prior sampling event the new event will be held in the pending event FIFO and the latency will increase by the duration that the new event is held in the pending event FIFO The latency between the occurrence of an external trigger ...

Page 1073: ...FIFO is Total Latency TTRIG TED TPD TS Where TPD is the delay programmed in the Event Time ACM_ETx register See Figure 22 8 Figure 22 8 shows latency details from occurrence of external triggers to assertion to ADC sampling events Figure 22 8 Trigger to Event Latency 00 SCLK Trigger ACMTMR0 CS ACMET3 0x00000002 ADC Controls Event 3 5h00 Event 0 ACMET0 0x000000EF 01 02 03 04 05 06 07 EF EE ED EC 00...

Page 1074: ...e of SCLK As a result these signals are not syn chronous to ACLK The setup hold and other timing parameters of the ADC controls CS and the frequency of ACLK can be configured in the ACM timing configuration registers ACM_TCx The polarity of CS and ACLK can be configured in the ACM control register ACM_CTL The tim ing parameters of the ADC controls ACM_A 2 0 ACM_RANGE and ACM_SGLDIFF cannot be indi...

Page 1075: ...fied in terms of SCLK To achieve accurate timing relationship between CS and ACLK which is a free running clock the ACLK signal is re aligned with the active edge of CS This realignment of ACLK ensures that the setup time of the first active edge of ACLK with respect to the active edge of CS is at least 1 ACLK cycle The figures in the following sections Case 1 Chip Select Asserted During the High ...

Page 1076: ...hen CS is asserted during the high phase of ACLK The first edge of ACLK after the assertion of CS is the falling edge The two reference clock signals Ref ACLK1 and Ref ACLK2 are shown to illustrate how the ACLK signal can be generated from a free running clock Ref ACLK1 in order to meet the timing requirements between ACLK and CS Ref ACLK2 is based on the free running clock Ref ACLK1 but is adjust...

Page 1077: ...ed during the low phase of ACLK as shown in Figure 22 11 ACLK is immediately pulled high causing a duty cycle vari ation It is important to ensure that systems interfacing with the ACM can tolerate such duty cycle variation In this case similar to case 1 the time from the active edge of CS to the falling edge of ACLK is 1 ACLK period Figure 22 11 ACLK Adjustment for the Case of CS Assertion During...

Page 1078: ... ensures that the time from the active edge of CS to the falling edge of ACLK is constant at a period of 1 ACLK cycle Notice that this suppression of ACLK falling edge leads to duty cycle variation It is important to ensure that systems interfacing with the ACM can tolerate such duty cycle variation Figure 22 12 ACLK Adjustment for the Case of CS Assertion Right Before the Falling Edge of ACLK CLK...

Page 1079: ...is extension ensures that the time from the active edge of CS to the fall ing edge of ACLK is constant at a period of 1 ACLK cycle Notice that this leads to duty cycle variation It is important to ensure that systems interfacing with the ACM can tolerate such duty cycle variation Figure 22 13 ACLK Adjustment for the Case of CS Assertion Right Before the Rising Edge of ACLK CLKPOL 0 SCLK Ref ACLK1 ...

Page 1080: ...14 shows an example diagram of the case where CLKPOL 1 ACM Timing Specifications The AC timings of ACM signals are specified in ADSP BF504 ADSP BF504F ADSP BF506F Embedded Processor Data Sheet When trigger sources external to the processor are used for triggering the ACM for example external signals on the GPIO timer or PWM sync pins the minimum pulsewidth for such trigger sources needs to be 1 SC...

Page 1081: ...g to the ADC device For capturing the data from the ADC use either SPORT0 or SPORT1 on the receiver side of the processor The ACM should be enabled before the SPORT controller is enabled however the SPORT can be configured before the ACM is enabled The SPORT receiver should be configured in slave mode external clock IRCLK 0 and external frame sync IRFS 0 External ADC timing determines the settings...

Page 1082: ...trol registers to define the ACM clock frequency chip select signal width and setup and hold and zero time of ACM control signals Configure the event register pairs Event Control and Event Time registers to create required ACM events The Timer Enabled TMRENx bits should be programmed together only after the ACM is enabled but once the bits are programmed it should not be changed modifying the enab...

Page 1083: ...not triggered the ECOM bit goes low when the ACM receives either the ACMTMR0 or ACMTMR1 trigger Therefore if the ACMTMR1 trigger occurs late or not at all the ECOM bit shows completion as soon as ACMTMR0 related events are over without waiting for the ACMTMR1 events Because ACLK is an external clock relative to the SPORT peripheral any SPORT requirements for a minimum number of stable exter nal cl...

Page 1084: ... following Figure 22 15 SPORT and ACM Bit Settings for ADC Applications Bit Setting Description SPORTx_RCR1 IRCLK 0 External serial clock mode SPORTx_RCR1 IRFS 0 External frame sync mode SPORTx_RCR1 RFSR 1 Frame sync required mode SPORTx_RCR1 RLSBIT 0 MSB bit first format SPORTx_RCR1 RCKFE 0 Sample data and external frame sync with rising edge of RSCLK SPORTx_RCR1 LRFS 1 Active low frame sync SPOR...

Page 1085: ... event status register ACM_ES ACM interrupt mask register ACM_IMSK ACM missed event status register ACM_MS ACM event missed interrupt mask register ACM_EMSK ACM event control registers ACM_ERx and ACM event time registers ACM_ETx Descriptions and bit diagrams for each of these MMRs are provided in the following sections ACM_TC0 SC Setup cycles should be programmed accord ing to acquisition time re...

Page 1086: ...1 Select PWM_SYNC1 10 Select PF10 GPIO or TMR2 11 Select PG5 GPIO or TMR7 TRGSEL0 Trigger Select 0 Timer1 external trigger select 00 Select PWM_SYNC0 01 Select PWM_SYNC1 10 Select PF10 GPIO or TMR2 11 Select PG5 GPIO or TMR7 TRGSEL1 Trigger Select 1 Timer0 trigger polarity select 0 Rising edge trigger 1 Falling edge trigger TRGPOL0 Trigger Polarity 0 Timer1 trigger polarity select 0 Rising edge tr...

Page 1087: ...es that all enabled events are completed for the current trigger The ECOM bit gets cleared with each trigger If both the timers are enabled ECOM is set only after completion of all events for both Figure 22 17 ACM Status ACM_STAT Register 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ACM Status Register ACM_STAT 0 Pending incomplete events 1 All enabled events for current t...

Page 1088: ...rsion 1 Event 2 conversion done ES3 Event 3 Status W1C 0 No Event 3 conversion 1 Event 3 conversion done ES4 Event 4 Status W1C 0 No Event 4 conversion 1 Event 4 conversion done ES5 Event 5 Status W1C 0 No Event 5 conversion 1 Event 5 conversion done ES6 Event 6 Status W1C 0 No Event 6 conversion 1 Event 6 conversion done ES7 Event 7 Status W1C 0 No Event 7 conversion 1 Event 7 conversion done ES1...

Page 1089: ...s IRQ Enable 0 Disable mask interrupt 1 Enable unmask interrupt IE4 Evt4 Status IRQ Enable 0 Disable mask interrupt 1 Enable unmask interrupt IE5 Evt5 Status IRQ Enable 0 Disable mask interrupt 1 Enable unmask interrupt IE6 Evt6 Status IRQ Enable 0 Disable mask interrupt 1 Enable unmask interrupt IE7 Evt7 Status IRQ Enable 0 Disable mask interrupt 1 Enable unmask interrupt IE15 Evt15 Status IRQ En...

Page 1090: ...ed W1C 0 No event missed 1 Event missed EM2 Event 2 Missed W1C 0 No event missed 1 Event missed EM3 Event 3 Missed W1C 0 No event missed 1 Event missed EM4 Event 4 Missed W1C 0 No event missed 1 Event missed EM5 Event 5 Missed W1C 0 No event missed 1 Event missed EM6 Event 6 Missed W1C 0 No event missed 1 Event missed EM7 Event 7 Missed W1C 0 No event missed 1 Event missed EM15 Event 15 Missed W1C...

Page 1091: ...3 Evt3 Missed IRQ Enable 0 Disable mask interrupt 1 Enable unmask interrupt MIE4 Evt4 Missed IRQ Enable 0 Disable mask interrupt 1 Enable unmask interrupt MIE5 Evt5 Missed IRQ Enable 0 Disable mask interrupt 1 Enable unmask interrupt MIE6 Evt6 Missed IRQ Enable 0 Disable mask interrupt 1 Enable unmask interrupt MIE7 Evt7 Missed IRQ Enable 0 Disable mask interrupt 1 Enable unmask interrupt MIE15 Ev...

Page 1092: ...nt occurs Selection of EPFx values are based on the type of ADC usage mode and other items To prevent incorrect results the ACM_ER register should not be pro grammed when an event is active Program the ACM_ER before providing a trigger and re program it after all the events complete ECOM bit in the ACM_STAT register is set Figure 22 22 ACM Event Control ACM_ERx Registers 15 14 13 12 11 10 9 8 7 6 ...

Page 1093: ...he events are complete ECOM bit in the ACM_STAT register is set ACM Timing Configuration ACM_TCx Registers The ACM has two External Timing Configuration registers Timing Configuration 0 ACM_TC0 and Timing Configuration 1 ACM_TC1 For information relating to signal timing and operation of the ACM_TCx regis ters see ACM External Pin Timing on page 22 20 For timing specifications see the ADSP BF504 AD...

Page 1094: ...llows ACLK frequency SCLK frequency 2 x CKDIV 1 The maximum ACLK frequency is SCLK 2 and the minimum ACLK fre quency is SCLK 512 So for a 100 MHz SCLK the ACLK range is from 195 KHz to 50 MHz Figure 22 24 ACM Timing Configuration 0 ACM_TC0 Register 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ACM Timing Configuration 0 Register ACM_TC0 CKDIV Clock Divisor 8 bit serial cloc...

Page 1095: ... to use the ACM in conjunction with a SPORT Figure 22 25 ACM Timing Configuration 1 ACM_TC1 Register 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ACM Timing Configuration 1 Register ACM_TC1 CSW CS Width Active duration of active CS in ACLK cycles 0000 0000 1 ACLK cycle 0000 0001 2 ACLK cycles 0000 1111 16 ACLK cycle 1111 1111 256 ACLK cycle Reset 0x0000 HC Hold Cycles Hold...

Page 1096: ... set to rising edge Trigger 0 polarity set to rising edge Trigger 1 select set to PWM_SYNC1 Trigger 0 select set to PWM_SYNC0 ACMTMR1 enabled ACMTMR0 enabled ACM disabled write ACM_CTL 0x4026 16bit Timing configurations 1 register CS width Tcsw d10 Hold cycles Th d15 Zero cycles Tz d2 write ACM_TC1 0x2f0a 16bit Timing configurations 0 register Clock divisor CKDIV d1 Setup cycles Ts d0 write ACM_TC...

Page 1097: ...A 2 0 h7 ACM_RANGE 1 ACM_SGLDIFFS 1 Event 5 enabled write ACM_ER5 0x3f 16bit Event 14 ETIME h00000001 write ACM_ET14 0x00000001 32bit ACM signal settings for event 14 ACM_A 2 0 h5 ACM_RANGE 1 ACM_SGLDIFFS 1 Event 14 enabled write ACM_ER14 0x3b 16bit All ACM event misses generate an interrupt write ACM_EMSK 0xffff 16bit All ACM events generate interrupts write ACM_IMSK 0xffff 16bit Enable the ACM b...

Page 1098: ... a trigger to initiate sampling ensure that any SPORT requirements around a minimum number of stable external clock cycles before assertion of the first SPORT frame sync are observed refer to Programming Model set_trig Wait for all events to complete wait Disable the SPORT disable_sport1 Finally disable the ACM write ACM_CTL 0x0000 16bit ...

Page 1099: ...ADC specification and system design for performance information see ADSP BF504 ADSP BF504F ADSP BF506F Embedded Processor Data Sheet ADC Architecture The ADSP BF506F processor includes an ADC All internal ADC signals are connected out to package pins to enable maximum flexibility in mixed signal applications The internal ADC is a dual 12 bit high speed low power successive approximation ADC that o...

Page 1100: ...up to 2 MSPS Specified for VDD of 2 7 V to 5 25 V Figure 23 1 ADC Internal Functional Block Diagram 12 BIT SUCCESSIVE APPROXIMATION ADC DOUTA OUTPUT DRIVERS CONTROL LOGIC T H BUF VA1 VA2 VA3 VA4 VA5 VA6 MUX REF ADC VDRIVE REF SELECT DCAPA AVDD DVDD BUF DOUTB OUTPUT DRIVERS 12 BIT SUCCESSIVE APPROXIMATION ADC T H VB1 VB2 VB3 VB4 VB5 VB6 MUX AGND AGND AGND DCAPB DGND DGND CS ADSCLK RANGE SGL DIFF A0...

Page 1101: ...is determined by the ADSCLK frequency There are no pipelined delays associated with the part The internal ADC uses advanced design techniques to achieve very low power dissipation at high throughput rates The part also offers flexible power throughput rate management when operating in normal mode as the quiescent current consumption is so low The analog input range for the part can be selected to ...

Page 1102: ...s connected to the serial port of the processor the maxi mum sampling rate achievable depends on the timing specifications of both the ADC and the processor peripherals involved in the connectivity The following sections describe two commonly used interface options that can support maximum sampling rates Interfacing the ADC With the ACM and the SPORT As shown in Figure 22 1 on page 22 2 ADSP BF504...

Page 1103: ...heoretic sampling rate See the ADSP BF504 ADSP BF504F ADSP BF506F Embedded Processor Data Sheet for the actual value of the parameters necessary for the above calculations In practice various factors such as board delays and maximum frequency ratings can reduce the maximum achievable sampling rate Fore example assuming the following values TSDR 7 ns T4 27 ns TQUIET 30 ns NB 14 bits and board delay...

Page 1104: ...timing specifications apply DRxPRI DRxSEC minimum setup before external clock TSDRE Data access time after ADSCLK falling edge VDD 5 V T4 Assuming board delays of no more than 3 ns the maximum sampling rate of 2 MSPS can be supported for VDD 5 V and ADSCLK 31 25 MHz Figure 23 2 ADC TMR and SPORT Connections SPORTx DRxSEC DRxPRI RCLKx RFSx ADC INTERNAL DOUTB DOUTA ADSCLK CS RANGE SGL DIFF A 2 0 TIM...

Page 1105: ...the on chip boot ROM at address 0xEF00 0000 The internal boot ROM includes a small boot kernel that loads applica tion data from an external memory or host device The application data is expected to be available in a well defined format called the boot stream A boot stream consists of multiple blocks of data and special commands that instruct the boot kernel how to initialize on chip L1 memories a...

Page 1106: ...m internal parallel flash1 in synchronous burst mode In this mode fast timing parameters are used to communicate with the flash device The boot ker nel configures the flash device for synchronous burst communication and boots from the flash syn chronously 011 Boot from external serial SPI memory After an initial device detection routine the kernel boots from either 8 bit 16 bit 24 bit or 32 bit ad...

Page 1107: ...st the bit rate 1 This mode is only available for products containing flash memory Table 24 2 Resets Reset Source Result Hardware reset The RESET pin causes a hard ware reset Resets both the core and the peripherals includ ing the dynamic power management controller DPMC Resets bits 15 4 of the SYSCR register For more information see System Reset Configuration SYSCR Register on page 24 61 Wakeup f...

Page 1108: ...modes The SWRST or the SYSCR register can be read to determine whether the reset source was the watchdog timer Core double fault reset A core double fault occurs when an exception happens while the exception handler is executing If the core enters a double fault state and the Core Double Fault Reset Enable bit DOUBLE_FAULT is set in the SWRST register then a software reset will occur Resets both t...

Page 1109: ...control pins No other functions are shared with these pins and they may be permanently strapped by tying them directly to either VDDEXT or GND The pins and the corresponding bits in the SYSCR register configure the boot mode that is employed after hardware reset or system software reset See Blackfin Processor Program ming Reference for further information Software Resets A software reset may be in...

Page 1110: ...et SYSRST bit in the core debug control register DBGCTL DBGCTL is not visible to the memory map through emulation software through the JTAG port A software reset only affects the state of the core The boot kernel immedi ately issues a system reset to keep consistency with the system domain On a hardware reset the boot kernel initializes the EVT1 register to 0xFFA0 0000 When the booting process com...

Page 1111: ... and Booting Figure 24 1 Global Boot Flow START at 0xEF00 0000 Issue System Reset SWRST 0x0007 RESET ELSE HARDWARE BCODE JUMP TO EVT1 VECTOR BCODE_NOBOOT PREPARE ALLBOOT BFLAG_WAKEUP 0 PREPARE QUICKBOOT BFLAG_WAKEUP 1 WAKEUP BCODE BCODE_QUICKBOOT ELSE ELSE BOOT KERNEL ...

Page 1112: ...r a programming example see Example System Reset on page 24 82 Listing 24 1 and Listing 24 2 on page 24 83 show code examples that handle the reset event See Blackfin Processor Programming Reference for details on user and supervisor modes Systems that do not work in an operating system environment may not enter user mode Typically the interrupt level needs to be degraded down to IVG15 Listing 24 ...

Page 1113: ...ta Each block begins with a block header The header contains control words such as the destination address and data length information As Figure 24 2 illustrates your development tools suite features a loader utility elfloader exe The loader utility parses the input executable file dxe segments the application data into multiple blocks and creates the header information for each block The output i...

Page 1114: ...g into scratchpad memory 0xFFB0 0000 0xFFB0 0FFF is not supported If booting to scratchpad memory is attempted the processor hangs within the on chip boot ROM Similarly booting into the upper 16 bytes of L1 data bank A 0xFF80 7FF0 0xFF80 7FFF by default is not supported These memory loca tions are used by the boot kernel for intermediate storage of block header information These memory regions can...

Page 1115: ...rce code for any addi tional questions not covered in this manual Note that minor maintenance work may be done to the content of the boot ROM when silicon is updated Block Headers A boot stream consists of multiple boot blocks as shown in Figure 24 3 Every block is headed by a 16 byte block header However every block does not necessarily have a payload as shown in Figure 24 4 Figure 24 3 Booting P...

Page 1116: ... four 32 bit words the BLOCK CODE the TARGET ADDRESS the BYTE COUNT and the ARGUMENT fields Figure 24 4 Boot Stream Headers BLOCK 0 HEADER BLOCK 0 PAYLOAD BLOCK 1 HEADER BLOCK 2 HEADER BLOCK 2 PAYLOAD BLOCK CODE TARGET ADDRESS BYTE COUNT ARGUMENT OFFSET 0X0000 OFFSET 0X0004 OFFSET 0X0008 OFFSET 0X000C 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 ...

Page 1117: ...in case of memory boot modes this field is interrogated by the boot kernel to differentiate the 8 bit 16 bit and 32 bit cases Figure 24 5 Block Code 31 0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 1 0 1 1 0 1 0 0 0 0 0 0 0 1 0 HDRCHK Header XOR Checksum Block Code 31 16 HDRSGN Header Sign Block Code 15 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BFLAG_FINAL BFLAG...

Page 1118: ...IU3 3 Applicable only to memory boot modes 4 8 bit 8 Zero padded 8 bit boot from 64 bit EBIU4 4 Not supported by ADSP BF50x Blackfin products 5 8 bit 16 Zero padded 8 bit boot from 128 bit EBIU4 6 16 bit 2 Default 16 bit boot from 16 bit source 7 16 bit 4 Zero padded 16 bit boot from 32 bit EBIU3 8 16 bit 8 Zero padded 16 bit boot from 64 bit EBIU4 9 16 bit 16 Zero padded 16 bit boot from 128 bit ...

Page 1119: ... and byte count must be divisible by four 9 BFLAG_QUICKBOOT Processes the block for full boot only Does not process this block for a quick boot warm boot 10 BFLAG_CALLBACK Calls a subfunction that may reside in on chip or off chip ROM or is loaded by an initcode in advance Often used with the BFLAG_INDIRECT switch If BFLAG_CALLBACK is set for any block an initcode must register the callback functi...

Page 1120: ...he source address pointer In slave boot modes the boot kernel actively loads and changes the payload of the block In slave modes the byte count must be a positive value 13 BFLAG_INDIRECT Boots to an intermediate storage place allowing for calling an optional callback function before booting to the destination This flag is used when the boot source does not have DMA support and either the destinati...

Page 1121: ...t kernel jumps at the end of the boot process This address will also be stored in the EVT1 register The elf loader utility sets this value to 0xFFA0 0000 for compatibility with other Blackfin products The target address should be divisible by four because the boot kernel uses 32 bit DMA for certain operations The target address must point to valid on chip memory locations When booting through peri...

Page 1122: ... that should be divisible by four Zero val ues are allowed in all block types Most boot modes are based upon DMA operation which are only 16 bit words for Blackfin processors The boot kernel may therefore start multiple DMA work units for large boot blocks This enables a single block to fill to zero the memory for example result ing in compact boot streams The HWAIT signal may toggle for each work...

Page 1123: ... this purpose The signal polarity of the HWAIT strobe is programmable by an external resistor in the 10 k range A pull up resistor instructs the HWAIT signal to be active high In this case the host is permitted to send header and footer data when HWAIT is low but should pause while HWAIT is high This is the mode used in SPI slave boot on other Blackfin products Similarly a pull down resistor progr...

Page 1124: ...sor is in an active mode or a power down mode For example the HWAIT signal can be used to signal when the processor is in hibernate mode Using HWAIT as Reset Indicator While the HWAIT signal is mandatory in some boot modes it is optional in others If using a pull up resistor the HWAIT signal is driven low for the rest of the boot process and beyond If using a pull down resistor HWAIT is driven hig...

Page 1125: ...UD UARTx_DLH and UARTx_DLL remain unchanged so that settings obtained during the booting process are not lost Single Block Boot Streams The simplest boot stream consists of a single block header and one contig uous block of instructions With appropriate flag instructions the boot kernel loads the block to the target address and immediately terminates by executing the loaded block Table 24 5 shows ...

Page 1126: ...ictable processor behavior due to the boot mem ory not being programmed with valid data yet The boot kernel first loads the first block header and checks it for consistency If the block header is corrupted the boot kernel goes into a safe idle state and does not start code execution If the initial block header checks good the boot kernel interrogates the block flags If the block has the BFLAG_FINA...

Page 1127: ...r multi DXE boot streams Figure 24 9 on page 24 42 shows a linked list of initial blocks that represent different applications Advanced Boot Techniques The following sections describe advanced boot techniques These tech niques are useful for customers developing custom boot routines Table 24 6 Initial Header for Direct Code Execution in BMODE 001 Field Value Comments BLOCK CODE 0xAD7B D006 0xAD00 ...

Page 1128: ...mbly The expected prototype is void initcode ADI_BOOT_DATA pBootStruct The header files define the ADI_BOOT_INITCODE_FUNC type typedef void ADI_BOOT_INITCODE_FUNC ADI_BOOT_DATA Optionally the initcode routine can interrogate the formatting structure and customize its own behavior or even manipulate the regular boot pro cess A pointer to the structure is passed in the R0 register Assembly coders mu...

Page 1129: ...zero Then the only purpose of the block may be to instruct the boot kernel to issue the CALL instruction Initcode routines can be very different in nature They might reside in ROM or SRAM They might be called once during the booting process or multiple times They might be volatile and be overwritten by other boot blocks after executing or they might be permanently available after boot time The boo...

Page 1130: ... 4 Boot data code into memory 5 Continue program execution with block n Although initcode dxe files are built as CCES or VisualDSP projects they differ from standard projects Initcodes provide only a callable sub function so they look more like a library than an application Never theless unlike library files DLB file extension the symbol addresses have already been resolved by the linker An initco...

Page 1131: ...n Code Execution Boot Blackfin Processor Header for Init Block Init Block Flash PROM or SPI Device L1 Memory Init Block 0xEF00 0000 On Chip Boot ROM Header for L1 Block L1 Block Header for Block n Block n Flash PROM or SPI Device Init Block L1 Block Blackfin Processor Header for Init Block Init Block Header for L1 Block L1 Block Header for Block n Block n On Chip Boot ROM 0xEF00 0000 After Init Co...

Page 1132: ... for a software boot See the flowchart in Figure 24 1 on page 24 7 The BFLAG_WAKEUP bit in the dFlag word of the ADI_BOOT_DATA structure indicates that the final decision was to perform a quick boot If the boot kernel is called from the application then the application can control the boot kernel behavior by setting the BFLAG_WAKEUP flag accordingly See the dFlags variable on Figure 24 27 on page ...

Page 1133: ...ories In some advanced booting scenarios the core needs to access the boot data during the booting process for example in processing decompression decryption and checksum algorithms at boot time The indirect booting option helps speed up and simplify such sce narios Software accesses off chip memory less efficiently and cannot access data directly if it resides in L1 instruction SRAM Indirect boot...

Page 1134: ...ple individual initcodes it can have just one callback routine In the standard boot scenario the callback routine has to be registered by an initcode prior to the first block that has the BFLAG_CALLBACK flag set The purpose of the callback routine is to apply standard processing to the block data Typically callback routines contain checksum decryption decompression or hash algorithms Checksum or h...

Page 1135: ..._DATA pBootStruct ADI_BOOT_BUFFER pCallbackStruct s32 dCbFlags The header file defines the ADI_BOOT_CALLBACK_FUNC type the following way typedef s32 ADI_BOOT_CALLBACK_FUNC ADI_BOOT_DATA ADI_BOOT_BUFFER s32 The pBootStruct argument is passed in R0 and points to the ADI_BOOT_DATA structure used by the boot kernel These are handled by the pTempBuffer and dTempByteCount variables as well as the pHeade...

Page 1136: ...the BFLAG_INDIRECT bit is not active so that the callback routine will only be called once per block When the CBFLAG_DIRECT flag is set the CBFLAG_FIRST and CBFLAG_FINAL flags are also set define CBFLAG_FINAL 0x0008 define CBFLAG_FIRST 0x0004 define CBFLAG_DIRECT 0x0001 A callback routine also has a boolean return parameter in register R0 If the return value is non zero the subsequent memory DMA d...

Page 1137: ... pointer The registration principle is similar to the XOR checksum exam ple shown in Programming Examples on page 24 82 Load Functions All boot modes are processed by a common boot kernel algorithm The major customization is done by a subroutine that must be registered to the pLoadFunction pointer in the ADI_BOOT_DATA structure Its simple proto type is as follows void LoadFunction ADI_BOOT_DATA pB...

Page 1138: ...Destination pointers must be properly updated In slave boot modes the boot kernel uses the address of the dArgument field in the pHeader block as the destination for the required dummy DMAs when payload data is consumed from BFLAG_IGNORE blocks If the load function requires access to the block s ARGUMENT word it should be read early in the function The most useful load functions BFROM_MDMA and BFR...

Page 1139: ...ler and Library Manual for Blackfin Processors for details Debugging the Boot Process If the boot process fails very little information can be gained by watching the chip from outside In master boot modes the interface signals can be observed In slave boot modes only the HWAIT or the RTS signals tell about the progress of the boot process However by using the emulator there are many possibilities ...

Page 1140: ...to ignore the error and to continue the boot process by clearing the ASTAT register while the emulator steps over the subse quent IF CC JUMP 0 instruction _bootrom bootmenu If the emulator hits a hardware breakpoint at the _bootrom bootmenu address this indicates that a valid boot mode is being used _bootrom bootkernel entry If the emulator hits a hardware breakpoint at the _bootrom bootkernel ent...

Page 1141: ...FFFA always marks the last entry in the log file Most of the data structures used by the boot kernel reside on the stack in scratchpad memory While executing the boot kernel routine excluding subroutines the P5 points to the ADI_BOOT_DATA structure Type ADI_BOOT_DATA P5 in the IDE s expression view or window to see the structure content Boot Management Blackfin processor hardware platforms may be ...

Page 1142: ...ittle impact to the Blackfin processor since the intelligence is provided by the host device Booting a Different Application The boot ROM provides a set of user callable functions that help to boot a new application or a fraction of an application Usually there is no need for the boot manager to deal with the format details of the boot stream These functions are BFROM_MEMBOOT discussed in Flash Bo...

Page 1143: ...boot image by default The second boot stream is appended immediately to the first one Since the utility updates the ARGUMENT field of all BFLAG_FIRST blocks the ARGUMENT field of a BFLAG_FIRST block is called next DXE pointer NDP The next DXE pointer of the first DXE boot stream points relatively to the start address of the second DXE boot stream A multi DXE boot image can be seen as a linked list...

Page 1144: ...000 ARGUMENT 0x0000 1000 BLOCK CODE 0xADB4 5006 First block of initcode DXE BFLAG_FIRST BFLAG_IGNORE Start address of application Size of optional bubble Next DXE pointer Bubble to be ignored by kernel BFLAG_INIT BFLAG_FINAL not set to continue boot processing Target address of initcode Size of initcode Not used Initcode First block of first application DXE BFLAG_FIRST BFLAG_IGNORE Start address o...

Page 1145: ...le to multi DXE boot streams The same scheme as shown in Figure 24 9 can be applied to direct code executions of multiple applications See Direct Code Execu tion on page 24 22 for more information The example shows a linked list of initial block headers that instruct the boot kernel to terminate Figure 24 8 LdrViewer Screen Shot ...

Page 1146: ...s and direct code execution blocks Figure 24 9 Multi DXE Direct Code Execution Arrangement Example TARGET ADDRESS 0x2000 0100 BYTE COUNT 0x0000 0010 ARGUMENT 0x0000 0010 BLOCK CODE 0xAD5A D006 Optional 16 byte bubble TARGET ADDRESS 0x2001 0000 BYTE COUNT 0x0000 0000 ARGUMENT 0x0000 0000 BLOCK CODE 0xAD5A D006 TARGET ADDRESS 0x2002 0000 BYTE COUNT 0x0000 0000 ARGUMENT 0x0000 0000 BLOCK CODE 0xAD59 ...

Page 1147: ...M_SPIBOOT etc are called they create an instance of the ADI_BOOT_DATA structure on the stack and fill the items with default values If the BFLAG_HOOK is set the boot kernel invokes a callback routine which was passed as the fourth argument of the ROM routines after the default values have been filled The hook routine can be used to overwrite the default values Every hook routine should fit the pro...

Page 1148: ...the slave boot modes awakens from hibernate it cannot boot by its own control A feed back mechanism has to be implemented at the system level to inform the host device whether the processor is in hibernate state or not The HWAIT strobe is an important primitive in such systems In the master boot modes the Blackfin processor usually does not need to be synchronized and can load the boot data by its...

Page 1149: ...o the emulation interrupt and can be debugged in the normal manner The no boot mode is not the same as the bypass mode featured by the ADSP BF53x Blackfin processor To simulate that bypass mode feature using BMODE 000 see Direct Code Execution on page 24 22 and Example Direct Code Execution on page 24 88 Flash Boot Modes These booting modes are intended to boot from internal parallel synchro nous ...

Page 1150: ...ading the rest of the first block header and processes the boot stream Hardware configuration is shown in Table 6 1 on page 6 2 The chip select is always controlled by the AMS0 strobe This maps the boot stream to the Blackfin processor s address 0x2000 0000 Internal parallel flash provides write protection mechanisms which can be activated during the power up and reset cycles of the Blackfin proce...

Page 1151: ...ress words are supported Standard SPI memories are read using either the standard 0x03 SPI read command or the 0x0B SPI fast read command Unlike other Blackfin processors the ADSP BF50x Blackfin pro cessors have no special support for DataFlash devices from Atmel Nevertheless DataFlash devices can be used for booting and are sold as standard 24 bit addressable SPI memories They also sup port the f...

Page 1152: ... TIMOD 2 the receive DMA mode is selected Clearing both the CPOL and CPHA bits results in SPI mode 0 The boot kernel does not allow SPI0 hardware to control the SPI0_SSEL1 pin Instead this pin is toggled in GPIO mode by software Initialization code is allowed to manipulate the uwSsel variable in the ADI_BOOT_DATA structure to extend the boot mecha nism to a second SPI memory connected to another G...

Page 1153: ... finished the boot kernel interrogates the data received on the MISO line If it does not equal 0xFF usually a DMACODE value of 0x01 is expected then an 8 bit addressable device is assumed If the received value equals 0xFF it is assumed that the memory device has not driven its data output yet and that the 0xFF value is due to the pull up resistor Thus another zero byte is transmitted and the recei...

Page 1154: ...evice detection has completed and the boot kernel re issues a 0x00 address to load the boot stream Figure 24 11 SPI Device Detection Principle Figure 24 12 Typical SPI Master Boot Waveforms 0x00 0x00 0x03 0x0B 0x00 0x00 0x00 0x00 0x01 0xFF 0xFF 0xFF 0xFF 0xFF 0x01 0xFF 0xFF 0xFF 0xFF 0x01 0xFF 0xFF 0xFF 0xFF 0xFF 0x01 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0x01 MOSI MISO MISO MISO MISO MISO STANDARD 8 BIT ...

Page 1155: ... byte transferred or remain low during the entire procedure 8 bit data is expected The 16 bit mode is not supported In SPI slave boot mode the boot kernel sets the CPHA bit and clears the CPOL bit in the SPI0_CTL register Therefore the MOSI pin is latched on the falling edge of the SPI_SCK pin For details see Chapter 18 SPI Compat ible Port Controller In SPI slave boot mode HWAIT functionality is ...

Page 1156: ... the host can send boot data The SPI module does not provide very large receive FIFOs so the host must test the HWAIT Figure 24 14 SPI Program Flow on Host Device HWAIT Start Pulse RESET low Asserted Assert SPI SS Deasserted HWAIT Asserted Send Next Byte Deasserted More Bytes Yes No EXIT Release SPI SS ...

Page 1157: ...AIT it gracefully finishes the transmission of the on going word Then it pauses transmission until HWAIT releases again PPI Boot Mode The ADSP BF50x processors feature a 16 bit PPI boot mode BMODE 101 The PPI is a half duplex bidirectional port consisting of up to 16 data lines 3 frame synchronization signals and a clock signal In PPI boot mode the PPI mode of operation is configured as follows Re...

Page 1158: ...nal This configuration lets the processor inform the host when the processor is ready to receive data and also how much data is expected This feature removes the need for the host to process the actual contents of the boot stream to identify the size of the data transfer The PPI host can synchronize the PPI_FS2 signal to PPI_CLK signal and initiate all data transfers accordingly The PPI_FS2 signal...

Page 1159: ...ore any fur ther PPI_FS2 TMR1 assertions until the currently pending transaction that was delayed has completed If the master is not capable of ignoring further PPI_FS2 TMR1 assertions the master must ensure that the DMA completes allowing for the PWM_OUT timer to be disabled prior to the com pletion of the timer pulse period of 0xFFFFFFFF PPI_CLK cycles After PPI boot completion the PPI interface...

Page 1160: ...ur bytes 0xBF UARTx_DLL UARTx_DLH 0x00 The host is requested to not send further bytes until it has received the complete acknowledge string Once the 0x00 byte is received the host can send the entire boot stream The host should know the total byte count of the boot stream but it is not required to have any knowledge about the content of the boot stream Further information regarding auto baud dete...

Page 1161: ... RTS output of UART0 Then the use of HWAIT becomes optional At boot time the Blackfin processor does not evaluate RTS signals driven by the host and the UART0 UA0_CTS input is inactive Since the UA0_RTS is in a high impedance state when the Blackfin processor is in reset or while executing preboot an external pull up resistor to VDDEXT is recommended Figure 24 19 and Figure 24 20 show the initial ...

Page 1162: ...ot it is not obvious on how to change the PLL by an initcode routine This is because the UARTx_DLL and UARTx_DLH registers have to be updated to keep the required bit rate constant after the SCLK frequency has changed It must be ensured that the host does not send data while the PLL is changing The initcode examples provided along with the CCES or VisualDSP tools installation demonstrate how this ...

Page 1163: ...st time SWRST was read Bit 14 indicates the software watchdog timer has generated the software reset Bit 13 indicates the core double fault has generated the software reset Bits 15 13 are read only and cleared when the register is read Reading the SWRST also clears bits 15 13 in the SYSCR register Bits 3 0 are read write Only writing to bits 2 0 resets only the modules in the SCLK domain It does n...

Page 1164: ...o not generate reset on core double fault 1 Generate reset on core double fault RESET_SOFTWARE Software Reset Status RO 0 No SW reset since last SWRST read 1 SW reset occurred since last SWRST read RESET_WDOG Software Watchdog Timer Source Read only 0 Software reset not generated by watchdog 1 Software reset generated by watchdog RESET_DOUBLE Core Double Fault Reset RO 0 SW reset not generated by ...

Page 1165: ...boot directly jump to EVT1 vector 0010 BCODE_QUICKBOOT Ignore WURESET always perform quick boot 0100 BCODE_ALLBOOT Ignore WURESET do not perform quick boot 0110 BCODE_FULLBOOT Ignore WURESET do not perform quick boot Update power management 1xxx reserved X 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 X X Reset dependent on pin values System Reset Configuration Register SYSCR X state...

Page 1166: ...er the hardware reset sequence Software can modify only bits 7 4 in this register to customize boot processing upon a software reset The WURESET indicates whether there was a wake up from hibernate since the last hardware reset The bit cannot be cleared by software The bits 15 13 are exact copies of the same bits in the SWRST register Unlike the SWRST register SYSCR can be read without clearing th...

Page 1167: ...040 Boot Code Revision BK_REVISION Word 31 16 Bit 31 24 BK_ID Boot Kernel Identifier Reads as 0xAD Boot Code Revision BK_REVISION Word 15 0 0xEF00 0040 BK_VERSION Boot Kernel Version Global boot kernel version number BK_UPDATE Boot Kernel Update Enhancements Bug fix version specifically made for the specific project Refer to the specific processor anomaly sheet for the version control of a specifi...

Page 1168: ...the build date as shown in Figure 24 24 Figure 24 24 Boot Code Date Code BK_DATECODE 0xEF00 0050 Boot Code Date Code BK_DATECODE Word 31 16 Bit 31 16 BK_YEAR Boot Code Date Code BK_DATECODE Word 15 0 0xEF00 0050 BK_MONTH BK_DAY 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 ...

Page 1169: ... 0xEF00 0048 which always reads as 0x0000 000 as shown in Figure 24 25 Figure 24 25 Zero Word BK_ZEROS 0xEF00 0048 Zero Word BK_ZEROS 31 16 Read only Zero Word BK_ZEROS 15 0 0xEF00 0048 Read only 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 ...

Page 1170: ...cture within the initcode routines This section uses C language definitions for documentation purposes Developers can use these structures directly in assembly programs by using the IMPORT direc tive The structures are supplied by the bfrom h header file in your CCES or VisualDSP installation directory Figure 24 26 Ones Word BK_ONES 0xEF00 004C Ones Word BK_ONES 31 16 Read only Ones Word BK_ONES 1...

Page 1171: ...lock header is loaded to L1 data memory location 0xFF80 7FF0 0xFF80 7FFF first or where pHeader points to There it is analyzed by the boot kernel ADI_BOOT_BUFFER typedef struct void pSource s32 dByteCount ADI_BOOT_BUFFER The structure ADI_BOOT_BUFFER is used for any kind of buffer For the user this structure is important when implementing advanced callback mechanisms ADI_BOOT_DATA typedef struct v...

Page 1172: ...BackFunction ADI_BOOT_HEADER pHeader void pTempBuffer void pTempCurrent s32 dTempByteCount s32 dBlockCount s32 dClock void pLogBuffer void pLogCurrent s32 dLogByteCount ADI_BOOT_DATA The structure ADI_BOOT_DATA is the main data structure A pointer to a ADI_BOOT_DATA structure is passed to most complex subroutines including load functions initcode and callback routines The structure has two parts W...

Page 1173: ...Ax_CONFIG register for the DMA channel in use dControlValue The lower 16 bits of this value are written to the pControlRegister location each time a DMA work unit is started dByteCount Number of bytes to be transferred dFlags The lower 16 bits of this variable hold the lower 16 bits of the current block code The upper 16 bits hold global flags See dFlags Word on page 24 72 uwDataWidth This instruc...

Page 1174: ...he pHeader pointer holds the address for intermediate storage of the block header By default this value is set to 0xFF80 7FF0 pTempBuffer This pointer tells the boot kernel what memory to use for intermediate storage when the BFLAG_INDIRECT flag is set for a given block The pointer defaults to 0xFF80 7F00 The value can be modified by the initcode routine but there would be some impact to the CCES ...

Page 1175: ...idual serial boot modes pLogBuffer Pointer to the circular log buffer By default the log buffer resides in L1 scratch pad memory at address 0xFFB0 0400 pLogCurrent Pointer to the next free entry of the circular log buffer dLogByteCount Size of the circular log buffer default is 0x400 bytes Table 24 10 Structure Variables ADI_BOOT_DATA Cont d Variable Description ...

Page 1176: ...0 BFLAG_TYPE3 three SPI address bytes 11 BFLAG_TYPE4 four SPI address bytes BFLAG_FASTREAD 0 normal SPI mode 1 SPI fast read operation BFLAG_ALTERNATE ADSP BF50x only 0 regular boot 1 alternate boot dFlags Word Bits 31 16 BFLAG_NONRESTORE 0 restore control registers on exit 1 do not restore control registers on exit BFLAG_RESET 0 do not issue system reset on exit 1 issue system reset on exit BFLAG...

Page 1177: ...o arguments C prototype void bfrom_FinalInit void The bfrom_FinalInit function never returns It only executes a JUMP to the address stored in EVT1 Figure 24 28 dFlags Word Bits 15 0 dFlags Word Bits 15 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BFLAG_FINAL BFLAG_FIRST BFLAG_INDIRECT BFLAG_IGNORE BFLAG_INIT BFLAG_CALLBACK BFLAG_QUICKBOOT BFLAG_FILL DMACODE DMA Coding BF...

Page 1178: ...om_PDma ADI_BOOT_DATA p This is the load function for peripherals such as SPI and UART that sup port DMA in their boot modes BFROM_MDMA Entry address 0xEF00 0006 Arguments pointer to ADI_BOOT_DATA in R0 C prototype void bfrom_MDma ADI_BOOT_DATA p This is the load function used for memory boot modes This routine is also reused when the BFLAG_FILL or the BFLAG_INDIRECT flags are specified ...

Page 1179: ...ling application the dFlags word is usually zero When done the routine does not return but jumps to the EVT1 vector address If the BFLAG_RETURN flag is set an RTS is executed instead and the routine returns to the parent function In this way fractions of an application can be loaded If the dBlockCount parameter is zero or a positive value all boot blocks are processed until the BFLAG_FINAL flag is...

Page 1180: ...stream DXE in a flash device is returned bfrom_MemBoot void 0x20000000 BFLAG_RETURN BFLAG_NEXTDXE 3 NULL In the above example the routine would return 0x2000 0000 when dBlockCount was set to 1 If the parameter dBlockCount is zero or posi tive when used along with the BFLAG_NEXTDXE command the kernel returns when the BFLAG_FIRST flag on a header in the next DXE chain is not set If the BFLAG_HOOK sw...

Page 1181: ...SPI0 controller The fourth argument pCallHook is passed over the stack It provides a hook to call a callback routine after the ADI_BOOT_DATA structure is filled with default values For example the pCallHook routine may overwrite the default value of the uwSsel value in the ADI_BOOT_DATA structure The coding follows the rules of uwHWAIT see Boot Host Wait HWAIT Feedback Strobe on page 24 19 A value...

Page 1182: ... not deal with port muxing at all When a part has been booted via SPI master mode after reset the port muxing configuration is typically already ready for a runtime call to the bfrom_SpiBoot routine Otherwise ensure that the SPI0MISO SPI0MOSI and SPI0SCK signals are properly activated in the PORTx_FER and PORTx_MUX registers The SPI0_SSEL1 signal requires however that the respective PORTx_FER bit ...

Page 1183: ...BOOT_DATA p This ROM entry provides access to the raw boot kernel routine It is the user s responsibility to initialize the items passed in the ADI_BOOT_DATA structure Pay particular attention that the function pointers pLoadFunction and pErrorFunction point to functional routines BFROM_CRC32 Entry address 0xEF00 0030 Arguments pointer to look up table in R0 pointer to data in R1 dByteCount in R2 ...

Page 1184: ...y the BFROM_CRC32CALLBACK routine The dInitial value is normally set to zero unless the CRC32 rou tine is called in multiple slices Then the dInitial parameter expects the result of the former run BFROM_CRC32POLY Entry address 0xEF00 0032 Arguments pointer to look up table in R0 polynomial in R1 updated block count returned in R0 C prototype s32 bfrom_Crc32Poly unsigned s32 pLut s32 dPolynomial Th...

Page 1185: ...nter to ADI_BOOT_BUFFER in R1 Callback Flags in R2 C prototype s32 bfrom_Crc32Callback ADI_BOOT_DATA pBS ADI_BOOT_BUFFER pCS s32 dCbFlags This is a wrapper function that ensures the BFROM_CRC32 subroutine fits into the boot process BFROM_CRC32INITCODE Entry address 0xEF00 0036 Arguments pointer to ADI_BOOT_DATA in R0 C prototype void bfrom_Crc32Initcode ADI_BOOT_DATA p ...

Page 1186: ...unction is called as an initcode during the boot process when the CRC calculation is desired See CRC Checksum Calculation on page 24 33 for details Programming Examples This section provides programming examples that demonstrate a number of system reset and booting techniques Example System Reset To perform a system reset use the code shown in Listing 24 1 or Listing 24 2 Listing 24 1 System Reset...

Page 1187: ...ng 24 3 Exiting Reset to User Mode _reset P1 L LO _usercode Point to start of user code P1 H HI _usercode RETI P1 Load address of _start into RETI RTI Exit reset priority _reset end _usercode Place user code here The reset handler most likely performs additional tasks not shown in the examples above Stack pointers and EVTx registers are initialized here Example Exiting Reset to Supervisor Mode To ...

Page 1188: ...t IVG15 bit P0 R0 write back to IMASK RAISE 15 generate IVG15 interrupt request IVG 15 is not served until reset handler returns P0 L LO _usercode P0 H HI _usercode RETI P0 RETI loaded with return address RTI Return from Reset Event _reset end _usercode Wait in user mode till IVG15 JUMP _usercode interrupt is serviced _isr_IVG15 IVG15 vectors here due to EVT15 Example Power Management with Initcod...

Page 1189: ...AGE SYSCTRL_PLLCTL SYSCTRL_PLLDIV SYSCTRL_LOCKCNT SYSCTRL_WRITE init_DPM NULL Listing 24 6 Changing PLL and Voltage Regulator in Assembly include blackfin h include bfrom h import bfrom h Load Immediate 32 bit value into data or address register define IMM32 reg val reg H hi val reg L lo val SECTION L1_code init_DPM link sizeof ADI_SYSCTRL_VALUES 2 SP R7 0 P5 5 SP 12 R0 L SET_MSEL 12 w FP sizeof A...

Page 1190: ... Example XOR Checksum Listing 24 7 illustrates how an initcode can be used to register a callback routine The routine is called after each boot block that has the BFLAG_CALLBACK flag set The calculated XOR checksum is compared against the block header ARGUMENT field When the checksum fails this example goes into idle mode Otherwise control is returned to the boot kernel Since this callback example...

Page 1191: ...ining bytes The boot kernel passes the dFlags parame ter so that the callback routines knows whether it is called the first time the last time or neither The dUserLong variable in the ADI_BOOT_DATA structure is used to store the intermediate results between function calls Listing 24 7 XOR Checksum s32 xor_callback ADI_BOOT_DATA pBS ADI_BOOT_BUFFER pCS s32 dFlags s32 i if pCS NULL pBS pHeader NULL ...

Page 1192: ... flash memory The ADSP BF50x processors provide a CRC32 checksum algorithm in the on chip L1 instruction ROM that can be used for booting under this scenario For more information see CRC Checksum Calculation on page 24 33 Example Direct Code Execution This code example illustrates how to instruct the CCES or VisualDSP tools to generate a flash image that causes the boot kernel to start code execut...

Page 1193: ... p0 RESOLVE _firstblock 0x20000000 RESOLVE start 0x20000020 KEEP start _firstblock SECTIONS flash INPUT_SECTION_ALIGN 4 INPUT_SECTIONS OBJECTS program LIBRARIES program INPUT_SECTIONS OBJECTS bootblock MEM_ASYNC0 To invoke the elfloader utility activate the meminit feature and use the command line switches romsplitter and maskaddr Refer to the appli cation note Running Programs from Flash on ADSP ...

Page 1194: ...Programming Examples 24 90 ADSP BF50x Blackfin Processor Hardware Reference ...

Page 1195: ... appears to the corresponding section of the text instead of repeating the discussion in this chapter Pin Descriptions Refer to the processor data sheet for pin information including pin numbers Managing Clocks Systems can drive the clock inputs with a crystal oscillator or a buffered shaped clock derived from an external clock oscillator The external clock connects to the processor s CLKIN pin It...

Page 1196: ...upts are available They include both core and periph eral interrupts The processor assigns default core priorities to system level interrupts However these system interrupts can be remapped via the sys tem interrupt assignment registers SIC_IARx For more information see the System Interrupts chapter The processor core supports nested and non nested interrupts as well as self nested interrupts For ...

Page 1197: ...until the store operation completes In multithreaded systems the TESTSET instruction is required to maintain semaphore consistency To ensure that the store operation is flushed through any store or write buffers issue an SSYNC instruction immediately after semaphore release The TESTSET instruction can be used to implement binary semaphores or any other type of mutual exclusion method The TESTSET i...

Page 1198: ...is nonzero Current thread could write thread_id to semaphore location to indicate current owner of resource R0 L THREAD_ID B P0 R0 When done using shared resource write a zero byte to P0 R0 0 B P0 R0 SSYNC NOTE Instead of busy idling in the QUERY loop one can use an operating system call to reschedule the current thread Data Delays Latencies and Throughput For detailed information on latencies and...

Page 1199: ...tra care should be taken with certain signals such as external memory read write and acknowledge strobes Use simple signal integrity methods to prevent transmission line reflec tions that may cause extraneous extra clock and sync signals Additionally avoid overshoot and undershoot that can cause long term damage to input pins Some signals are especially critical for short trace length and usually ...

Page 1200: ...alk Be sure to use lots of vias between the ground planes Keep critical signals such as clocks strobes and bus requests on a signal layer next to a ground plane and away from or laid out per pendicular to other non critical signals to reduce crosstalk Experiment with the board and isolate crosstalk and noise issues from reflection issues This can be done by driving a signal wire from a pulse gener...

Page 1201: ...es special attention Two things help power filtering above 100 MHz First capacitors should be physically small to reduce the inductance Surface mount capacitors of size 0402 give better results than larger sizes Secondly lower values of capacitance will raise the resonant frequency of the LC circuit While a cluster of 0 1 F is acceptable below 50 MHz a mix of 0 1 F 0 01 F 0 001 F and even 100 pF i...

Page 1202: ...ers are required on all other Blackfin pins to keep the pin voltage at or below absolute maximum ratings Test Point Access The debug process is aided by test points on signals such as CLKOUT or SCLK bank selects PPICLK and RESET If selection pins such as boot mode are connected directly to power or ground they are inaccessible under a BGA chip Use pull up and pull down resistors instead Oscillosco...

Page 1203: ... book is a technical reference that covers the problems encountered in state of the art high frequency digital circuit design It is an excellent source of information and practical ideas Topics covered in the book include High speed properties of logic gates Measurement techniques Transmission lines Ground planes and layer stacking Terminations Vias Power systems Connectors Ribbon cables Clock dis...

Page 1204: ...d not be connected directly to an R C time delay because such a circuit could be noise sensitive In addition to the hardware reset mode provided via the RESET pin the processor supports several software reset modes For detailed information on the various modes see Blackfin Processor Pro gramming Reference The processor state after reset is also described in the programming reference Recommendation...

Page 1205: ...e boot during boot and application pin usage Voltage Regulation Interface ADSP BF50x processors must use an external voltage regulator to power the VDDINT domain The EXT_WAKE and PG signals can facilitate commu nication with the external voltage regulator EXT_WAKE is high true for power up and low only when the processor is in the hibernate state EXT_WAKE may be connected directly to the low true ...

Page 1206: ...is can be accomplished with an external resistor divider from VDDEXT or any other fixed stable voltage A divider with impedance of 1M Ohm is sufficient to supply current to this PG input To save even more current during hibernation the EXT_WAKE signal may be used as the voltage source to the divider EXT_WAKE is low during hibernation but will go high before the VDDINT voltage is applied by the ext...

Page 1207: ...s described The diagrams show individual bit descrip tions for each register Table A 1 Register Tables in This Chapter Function Peripheral System Reset and Interrupt Control Registers on page A 4 DMA Memory DMA Control Registers on page A 5 Ports Registers on page A 8 Timer Registers on page A 11 Core Timer Registers on page A 3 Watchdog Timer Registers on page A 15 GP Counter Registers on page A ...

Page 1208: ...e whether a 16 bit or a 32 bit access is required All system MMR space that is not defined in this appendix is reserved for internal use only Processor Specific Memory Registers Processor specific memory registers 0xFFE0 0004 0xFFE0 0300 are listed in Table A 2 CAN Registers on page A 26 ACM Registers on page A 42 PWM Registers on page A 44 RSI Registers on page A 46 Table A 2 Processor Specific M...

Page 1209: ...L Stacked flash control register 0XFFC0 3290 FLASH_CONTROL_SET Stacked flash control set register 0XFFC0 3294 FLASH_CONTROL_CLEAR Stacked flash control clear register Table A 3 Core Timer Registers Memory Mapped Address Register Name For individual bits see this diagram 0xFFE0 3000 TCNTL Core Timer Control Register TCNTL on page 11 5 0xFFE0 3004 TPERIOD Core Timer Period Register TPERIOD on page 1...

Page 1210: ...rrupt Mask SIC_IMASK Regis ter on page 4 12 0xFFC0 0110 SIC_IAR0 System Interrupt Assignment SIC_IAR Reg ister on page 4 11 0xFFC0 0114 SIC_IAR1 System Interrupt Assignment SIC_IAR Reg ister on page 4 11 0xFFC0 0118 SIC_IAR2 System Interrupt Assignment SIC_IAR Reg ister on page 4 11 0xFFC0 011C SIC_IAR3 System Interrupt Assignment SIC_IAR Reg ister on page 4 11 0xFFC0 0150 SIC_IAR4 System Interrup...

Page 1211: ...m the Base Address As an example the DMA channel 0 Y_MODIFY register is called DMA0_Y_ MODIFY and its address is 0xFFC0 0C1C Likewise the memory DMA stream 0 source current address register is called MDMA_S0_CURR_ADDR and its address is 0xFFC0 0E64 0xFFC0 0124 SIC_IWR0 System Interrupt Wakeup Enable SIC_IWR Register on page 4 12 0xFFC0 0164 SIC_IWR1 System Interrupt Wakeup Enable SIC_IWR Register ...

Page 1212: ...1 0xFFC0 0EC0 DMA11_ MemDMA stream 0 destination 0xFFC0 0F00 MDMA_D0_ MemDMA stream 0 source 0xFFC0 0F40 MDMA_S0_ MemDMA stream 1 destination 0xFFC0 0F80 MDMA_D1_ MemDMA stream 1 source 0xFFC0 0FC0 MDMA_S1_ Table A 7 DMA Register Suffix and Offset Register Suffix Offset From Base For individual bits see this diagram NEXT_DESC_PTR 0x00 DMA Next Descriptor Pointer Registers DMAx_NEXT_ DESC_PTR MDMA_...

Page 1213: ...iptor Pointer Registers DMAx_CURR_ DESC_PTR MDMA_yy_CURR_DESC_PTR on page 7 82 CURR_ADDR 0x24 DMA Current Address Registers DMAx_CURR_ ADDR MDMA_yy_CURR_ADDR on page 7 76 IRQ_STATUS 0x28 DMA Interrupt Status Registers DMAx_IRQ_STA TUS MDMA_yy_IRQ_STATUS on page 7 72 PERIPHERAL_MAP 0x2C DMA Peripheral Map Registers DMAx_PERIPHERAL_ MAP MDMA_yy_PERIPHERAL_MAP on page 7 67 CURR_X_COUNT 0x30 DMA Curre...

Page 1214: ...SKA GPIO Mask Interrupt A Registers on page 9 35 0xFFC0 0714 PORTFIO_MASKA_CLEAR GPIO Mask Interrupt A Clear Registers on page 9 38 0xFFC0 0718 PORTFIO_MASKA_SET GPIO Mask Interrupt A Set Registers on page 9 36 0xFFC0 071C PORTFIO_MASKA_TOGGLE GPIO Mask Interrupt A Toggle Registers on page 9 40 0xFFC0 0720 PORTFIO_MASKB GPIO Mask Interrupt B Registers on page 9 35 0xFFC0 0724 PORTFIO_MASKB_CLEAR G...

Page 1215: ...sters on page 9 36 0xFFC0 151C PORTGIO_MASKA_TOGGLE GPIO Mask Interrupt A Toggle Registers on page 9 40 0xFFC0 1520 PORTGIO_MASKB GPIO Mask Interrupt B Registers on page 9 35 0xFFC0 1524 PORTGIO_MASKB_CLEAR GPIO Mask Interrupt B Clear Registers on page 9 39 0xFFC0 1528 PORTGIO_MASKB_SET GPIO Mask Interrupt B Set Registers on page 9 37 0xFFC0 152C PORTGIO_MASKB_TOGGLE GPIO Mask Interrupt B Toggle R...

Page 1216: ...IO Mask Interrupt B Registers on page 9 35 0xFFC0 1724 PORTHIO_MASKB_CLEAR GPIO Mask Interrupt B Clear Registers on page 9 39 0xFFC0 1728 PORTHIO_MASKB_SET GPIO Mask Interrupt B Set Registers on page 9 37 0xFFC0 172C PORTHIO_MASKB_TOGGLE GPIO Mask Interrupt B Toggle Registers on page 9 41 0xFFC0 1730 PORTHIO_DIR GPIO Direction Registers on page 9 30 0xFFC0 1734 PORTHIO_POLAR GPIO Polarity Register...

Page 1217: ...TERESIS Port G Hysteresis Register on page 9 25 0xFFC0 3248 PORTH_HYSTERESIS Port H Hysteresis Register on page 9 25 0xFFC0 3280 NONGPIO_DRIVE Drive Strength Control on page 9 26 0xFFC0 3288 NONGPIO_HYSTERESIS Non GPIO Hysteresis Register on page 9 26 Table A 9 Timer Registers Memory Mapped Address Register Name For individual bits see this diagram 0xFFC0 0600 TIMER0_CONFIG Timer Configuration Reg...

Page 1218: ...3 0xFFC0 0620 TIMER2_CONFIG Timer Configuration Register TIMER_ CONFIG on page 10 41 0xFFC0 0624 TIMER2_COUNTER Timer Counter Register TIMER_COUN TER on page 10 42 0xFFC0 0628 TIMER2_PERIOD Timer Period TIMER_PERIOD and Timer Width TIMER_WIDTH Registers on page 10 43 0xFFC0 062C TIMER2_WIDTH Timer Period TIMER_PERIOD and Timer Width TIMER_WIDTH Registers on page 10 43 0xFFC0 0630 TIMER3_CONFIG Tim...

Page 1219: ...0 43 0xFFC0 0650 TIMER5_CONFIG Timer Configuration Register TIMER_ CONFIG on page 10 41 0xFFC0 0654 TIMER5_COUNTER Timer Counter Register TIMER_COUN TER on page 10 42 0xFFC0 0658 TIMER5_PERIOD Timer Period TIMER_PERIOD and Timer Width TIMER_WIDTH Registers on page 10 43 0xFFC0 065C TIMER5_WIDTH Timer Period TIMER_PERIOD and Timer Width TIMER_WIDTH Registers on page 10 43 0xFFC0 0660 TIMER6_CONFIG ...

Page 1220: ...0xFFC0 0678 TIMER7_PERIOD Timer Period TIMER_PERIOD and Timer Width TIMER_WIDTH Registers on page 10 43 0xFFC0 067C TIMER7_WIDTH Timer Period TIMER_PERIOD and Timer Width TIMER_WIDTH Registers on page 10 43 0xFFC0 0680 TIMER_ENABLE Timer Enable Register TIMER_ENABLE on page 10 36 0xFFC0 0684 TIMER_DISABLE Timer Disable Register TIMER_DISABLE on page 10 37 0xFFC0 0688 TIMER_STATUS Timer Status Regi...

Page 1221: ... see this diagram 0xFFC0 0200 WDOG_CTL Watchdog Control WDOG_CTL Register on page 12 7 0xFFC0 0204 WDOG_CNT Watchdog Count WDOG_CNT Register on page 12 5 0xFFC0 0208 WDOG_STAT Watchdog Status WDOG_STAT Register on page 12 6 Table A 11 GP Counter 0 Registers Memory Mapped Address Register Name For individual bits see this diagram 0xFFC0 3500 CNT0_CONFIG Counter Configuration Register CNT_CON FIG on...

Page 1222: ...NFIG Counter Configuration Register CNT_CON FIG on page 13 19 0xFFC0 3304 CNT1_IMASK Counter Interrupt Mask Register CNT_ IMASK on page 13 20 0xFFC0 3308 CNT1_STATUS Counter Status Register CNT_STATUS on page 13 20 0xFFC0 330C CNT1_COMMAND Counter Status Register CNT_STATUS on page 13 20 0xFFC0 3310 CNT1_DEBOUNCE Counter Debounce Register CNT_ DEBOUNCE on page 13 23 0xFFC0 33514 CNT1_COUNTER Count...

Page 1223: ...FC0 0000 PLL_CTL PLL Control Register on page 8 21 0xFFC0 0004 PLL_DIV PLL Divide Register on page 8 20 0xFFC0 0008 VR_CTL Voltage Regulator Control Register on page 8 22 0xFFC0 000C PLL_STAT PLL Status Register on page 8 21 0xFFC0 0010 PLL_LOCKCNT PLL Lock Count Register on page 8 22 Table A 14 PPI Registers Memory Mapped Address Register Name For individual bits see this diagram 0xFFC0 1000 PPI_...

Page 1224: ...pped Address Register Name For individual bits see this diagram 0xFFC0 0500 SPI0_CTL SPI Control SPI_CTL Register on page 18 36 0xFFC0 0504 SPI0_FLG SPI Flag SPI_FLG Register on page 18 38 0xFFC0 0508 SPI0_STAT SPI Status SPI_STAT Register on page 18 40 0xFFC0 050C SPI0_TDBR SPI Transmit Data Buffer SPI_TDBR Regis ter on page 18 42 0xFFC0 0510 SPI0_RDBR SPI Receive Data Buffer SPI_RDBR Regis ter o...

Page 1225: ...page 18 38 0xFFC0 3408 SPI1_STAT SPI Status SPI_STAT Register on page 18 40 0xFFC0 340C SPI1_TDBR SPI Transmit Data Buffer SPI_TDBR Regis ter on page 18 42 0xFFC0 3410 SPI1_RDBR SPI Receive Data Buffer SPI_RDBR Regis ter on page 18 43 0xFFC0 3414 SPI1_BAUD SPI Baud Rate SPI_BAUD Register on page 18 35 0xFFC0 3418 SPI1_SHADOW SPI RDBR Shadow SPI_SHADOW Regis ter on page 18 44 Table A 17 SPORT0 Cont...

Page 1226: ... Receive Configuration SPORT_ RCR1 and SPORT_RCR2 Registers on page 19 52 0xFFC0 0828 SPORT0_RCLKDIV SPORT Transmit and Receive Serial Clock Divider SPORT_TCLKDIV and SPORT_ RCLKDIV Registers on page 19 63 0xFFC0 082C SPORT0_RFSDIV SPORT Transmit and Receive Frame Sync Divider SPORT_TFSDIV and SPORT_RFS DIV Registers on page 19 64 0xFFC0 0830 SPORT0_STAT SPORT Status SPORT_STAT Register on page 19...

Page 1227: ...ceive Selection SPORT_MRCSn Registers on page 19 67 0xFFC0 0858 SPORT0_MRCS2 SPORT Multichannel Receive Selection SPORT_MRCSn Registers on page 19 67 0xFFC0 085C SPORT0_MRCS3 SPORT Multichannel Receive Selection SPORT_MRCSn Registers on page 19 67 Table A 18 SPORT1 Controller Registers Memory Mapped Address Register Name For individual bits see this diagram 0xFFC0 0900 SPORT1_TCR1 SPORT Transmit C...

Page 1228: ...and Receive Serial Clock Divider SPORT_TCLKDIV and SPORT_ RCLKDIV Registers on page 19 63 0xFFC0 092C SPORT1_RFSDIV SPORT Transmit and Receive Frame Sync Divider SPORT_TFSDIV and SPORT_RFS DIV Registers on page 19 64 0xFFC0 0930 SPORT1_STAT SPORT Status SPORT_STAT Register on page 19 62 0xFFC0 0934 SPORT1_CHNL SPORT Current Channel SPORT_CHNL Register on page 19 66 0xFFC0 0938 SPORT1_MCMC1 SPORT M...

Page 1229: ...ltichannel Receive Selection SPORT_MRCSn Registers on page 19 67 0xFFC0 0954 SPORT1_MRCS1 SPORT Multichannel Receive Selection SPORT_MRCSn Registers on page 19 67 0xFFC0 0958 SPORT1_MRCS2 SPORT Multichannel Receive Selection SPORT_MRCSn Registers on page 19 67 0xFFC0 095C SPORT1_MRCS3 SPORT Multichannel Receive Selection SPORT_MRCSn Registers on page 19 67 Table A 19 UART0 Controller Registers Mem...

Page 1230: ...BR Registers on page 15 38 Table A 20 UART1 Controller Registers Memory Mapped Address Register Name For individual bits see this diagram 0XFFC0 2000 UART1_DLL UARTx_DLL and UARTx_DLH Registers on page 15 43 0XFFC0 2004 UART1_DLH UARTx_DLL and UARTx_DLH Registers on page 15 43 0XFFC0 2008 UART1_GCTL UARTx_GCTL Registers on page 15 45 0XFFC0 200C UART1_LCR UARTx_LCR Registers on page 15 28 0XFFC0 2...

Page 1231: ...age 16 26 0xFFC0 1404 TWI_CONTROL TWI CONTROL Register TWI_CON TROL on page 16 25 0xFFC0 1408 TWI_SLAVE_CTL TWI Slave Mode Control Register TWI_ SLAVE_CTL on page 16 27 0xFFC0 140C TWI_SLAVE_STAT TWI Slave Mode Status Register TWI_ SLAVE_STAT on page 16 29 0xFFC0 1410 TWI_SLAVE_ADDR TWI Slave Mode Address Register TWI_ SLAVE_ADDR on page 16 29 0xFFC0 1414 TWI_MASTER_CTL TWI Master Mode Control Reg...

Page 1232: ...0 0xFFC0 1480 TWI_XMT_DATA8 TWI FIFO Transmit Data Single Byte Regis ter TWI_XMT_DATA8 on page 16 46 0xFFC0 1484 TWI_XMT_DATA16 TWI FIFO Transmit Data Double Byte Regis ter TWI_XMT_DATA16 on page 16 47 0xFFC0 1488 TWI_RCV_DATA8 TWI FIFO Receive Data Single Byte Register TWI_RCV_DATA8 on page 16 48 0xFFC0 148C TWI_RCV_DATA16 TWI FIFO Receive Data Double Byte Register TWI_RCV_DATA16 on page 16 48 Ta...

Page 1233: ...Remote Frame Handling reg 1 0XFFC0 2A30 CAN_OPSS1 Overwrite Protection Single Shot Xmission reg 1 Table A 23 CAN Mailbox Configuration 2 Registers For Mailboxes 16 31 Memory Mapped Address Register Name For individual bits see this diagram 0XFFC0 2A40 CAN_MC2 Mailbox config reg 2 0XFFC0 2A44 CAN_MD2 Mailbox direction reg 2 0XFFC0 2A48 CAN_TRS2 Transmit Request Set reg 2 0XFFC0 2A4C CAN_TRR2 Transm...

Page 1234: ...ter 0XFFC0 2A90 CAN_CEC Error Counter Register 0XFFC0 2A94 CAN_GIS Global Interrupt Status Register 0XFFC0 2A98 CAN_GIM Global Interrupt Mask Register 0XFFC0 2A9C CAN_GIF Global Interrupt Flag Register 0XFFC0 2AA0 CAN_CONTROL Master Control Register 0XFFC0 2AA4 CAN_INTR Interrupt Pending Register 0XFFC0 2AAC CAN_MBTD Mailbox Temporary Disable Feature 0XFFC0 2AB0 CAN_EWR Programmable Warning Level ...

Page 1235: ...ceptance Mask 0XFFC0 2B24 CAN_AM04H Mailbox 4 High Acceptance Mask 0XFFC0 2B28 CAN_AM05L Mailbox 5 Low Acceptance Mask 0XFFC0 2B2C CAN_AM05H Mailbox 5 High Acceptance Mask 0XFFC0 2B30 CAN_AM06L Mailbox 6 Low Acceptance Mask 0XFFC0 2B34 CAN_AM06H Mailbox 6 High Acceptance Mask 0XFFC0 2B38 CAN_AM07L Mailbox 7 Low Acceptance Mask 0XFFC0 2B3C CAN_AM07H Mailbox 7 High Acceptance Mask 0XFFC0 2B40 CAN_AM...

Page 1236: ...90 CAN_AM18L Mailbox 18 Low Acceptance Mask 0XFFC0 2B94 CAN_AM18H Mailbox 18 High Acceptance Mask 0XFFC0 2B98 CAN_AM19L Mailbox 19 Low Acceptance Mask 0XFFC0 2B9C CAN_AM19H Mailbox 19 High Acceptance Mask 0XFFC0 2BA0 CAN_AM20L Mailbox 20 Low Acceptance Mask 0XFFC0 2BA4 CAN_AM20H Mailbox 20 High Acceptance Mask 0XFFC0 2BA8 CAN_AM21L Mailbox 21 Low Acceptance Mask 0XFFC0 2BAC CAN_AM21H Mailbox 21 Hi...

Page 1237: ...M30H Mailbox 30 High Acceptance Mask 0XFFC0 2BF8 CAN_AM31L Mailbox 31 Low Acceptance Mask 0XFFC0 2BFC CAN_AM31H Mailbox 31 High Acceptance Mask Table A 25 CAN Mailbox Registers Memory Mapped Address Register Name For individual bits see this diagram 0XFFC0 2C00 CAN_MB00_DATA0 Mailbox 0 Data Word 0 15 0 Register 0XFFC0 2C04 CAN_MB00_DATA1 Mailbox 0 Data Word 1 31 16 Register 0XFFC0 2C08 CAN_MB00_DA...

Page 1238: ...N_MB02_DATA3 Mailbox 2 Data Word 3 63 48 Register 0XFFC0 2C50 CAN_MB02_LENGTH Mailbox 2 Data Length Code Register 0XFFC0 2C54 CAN_MB02_TIMESTAMP Mailbox 2 Time Stamp Value Register 0XFFC0 2C58 CAN_MB02_ID0 Mailbox 2 Identifier Low Register 0XFFC0 2C5C CAN_MB02_ID1 Mailbox 2 Identifier High Register 0XFFC0 2C60 CAN_MB03_DATA0 Mailbox 3 Data Word 0 15 0 Register 0XFFC0 2C64 CAN_MB03_DATA1 Mailbox 3 ...

Page 1239: ...B0 CAN_MB05_LENGTH Mailbox 5 Data Length Code Register 0XFFC0 2CB4 CAN_MB05_TIMESTAMP Mailbox 5 Time Stamp Value Register 0XFFC0 2CB8 CAN_MB05_ID0 Mailbox 5 Identifier Low Register 0XFFC0 2CBC CAN_MB05_ID1 Mailbox 5 Identifier High Register 0XFFC0 2CC0 CAN_MB06_DATA0 Mailbox 6 Data Word 0 15 0 Register 0XFFC0 2CC4 CAN_MB06_DATA1 Mailbox 6 Data Word 1 31 16 Register 0XFFC0 2CC8 CAN_MB06_DATA2 Mailb...

Page 1240: ..._MB08_TIMESTAMP Mailbox 8 Time Stamp Value Register 0XFFC0 2D18 CAN_MB08_ID0 Mailbox 8 Identifier Low Register 0XFFC0 2D1C CAN_MB08_ID1 Mailbox 8 Identifier High Register 0XFFC0 2D20 CAN_MB09_DATA0 Mailbox 9 Data Word 0 15 0 Register 0XFFC0 2D24 CAN_MB09_DATA1 Mailbox 9 Data Word 1 31 16 Register 0XFFC0 2D28 CAN_MB09_DATA2 Mailbox 9 Data Word 2 47 32 Register 0XFFC0 2D2C CAN_MB09_DATA3 Mailbox 9 D...

Page 1241: ...D78 CAN_MB11_ID0 Mailbox 11 Identifier Low Register 0XFFC0 2D7C CAN_MB11_ID1 Mailbox 11 Identifier High Register 0XFFC0 2D80 CAN_MB12_DATA0 Mailbox 12 Data Word 0 15 0 Register 0XFFC0 2D84 CAN_MB12_DATA1 Mailbox 12 Data Word 1 31 16 Register 0XFFC0 2D88 CAN_MB12_DATA2 Mailbox 12 Data Word 2 47 32 Register 0XFFC0 2D8C CAN_MB12_DATA3 Mailbox 12 Data Word 3 63 48 Register 0XFFC0 2D90 CAN_MB12_LENGTH ...

Page 1242: ...B14_ID1 Mailbox 14 Identifier High Register 0XFFC0 2DE0 CAN_MB15_DATA0 Mailbox 15 Data Word 0 15 0 Register 0XFFC0 2DE4 CAN_MB15_DATA1 Mailbox 15 Data Word 1 31 16 Register 0XFFC0 2DE8 CAN_MB15_DATA2 Mailbox 15 Data Word 2 47 32 Register 0XFFC0 2DEC CAN_MB15_DATA3 Mailbox 15 Data Word 3 63 48 Register 0XFFC0 2DF0 CAN_MB15_LENGTH Mailbox 15 Data Length Code Register 0XFFC0 2DF4 CAN_MB15_TIMESTAMP M...

Page 1243: ...18_DATA0 Mailbox 18 Data Word 0 15 0 Register 0XFFC0 2E44 CAN_MB18_DATA1 Mailbox 18 Data Word 1 31 16 Register 0XFFC0 2E48 CAN_MB18_DATA2 Mailbox 18 Data Word 2 47 32 Register 0XFFC0 2E4C CAN_MB18_DATA3 Mailbox 18 Data Word 3 63 48 Register 0XFFC0 2E50 CAN_MB18_LENGTH Mailbox 18 Data Length Code Register 0XFFC0 2E54 CAN_MB18_TIMESTAMP Mailbox 18 Time Stamp Value Register 0XFFC0 2E58 CAN_MB18_ID0 M...

Page 1244: ...TA1 Mailbox 21 Data Word 1 31 16 Register 0XFFC0 2EA8 CAN_MB21_DATA2 Mailbox 21 Data Word 2 47 32 Register 0XFFC0 2EAC CAN_MB21_DATA3 Mailbox 21 Data Word 3 63 48 Register 0XFFC0 2EB0 CAN_MB21_LENGTH Mailbox 21 Data Length Code Register 0XFFC0 2EB4 CAN_MB21_TIMESTAMP Mailbox 21 Time Stamp Value Register 0XFFC0 2EB8 CAN_MB21_ID0 Mailbox 21 Identifier Low Register 0XFFC0 2EBC CAN_MB21_ID1 Mailbox 21...

Page 1245: ...N_MB24_DATA2 Mailbox 24 Data Word 2 47 32 Register 0XFFC0 2F0C CAN_MB24_DATA3 Mailbox 24 Data Word 3 63 48 Register 0XFFC0 2F10 CAN_MB24_LENGTH Mailbox 24 Data Length Code Register 0XFFC0 2F14 CAN_MB24_TIMESTAMP Mailbox 24 Time Stamp Value Register 0XFFC0 2F18 CAN_MB24_ID0 Mailbox 24 Identifier Low Register 0XFFC0 2F1C CAN_MB24_ID1 Mailbox 24 Identifier High Register 0XFFC0 2F20 CAN_MB25_DATA0 Mai...

Page 1246: ...MB27_DATA3 Mailbox 27 Data Word 3 63 48 Register 0XFFC0 2F70 CAN_MB27_LENGTH Mailbox 27 Data Length Code Register 0XFFC0 2F74 CAN_MB27_TIMESTAMP Mailbox 27 Time Stamp Value Register 0XFFC0 2F78 CAN_MB27_ID0 Mailbox 27 Identifier Low Register 0XFFC0 2F7C CAN_MB27_ID1 Mailbox 27 Identifier High Register 0XFFC0 2F80 CAN_MB28_DATA0 Mailbox 28 Data Word 0 15 0 Register 0XFFC0 2F84 CAN_MB28_DATA1 Mailbo...

Page 1247: ... CAN_MB30_DATA3 Mailbox 30 Data Word 3 63 48 Register 0XFFC0 2FD0 CAN_MB30_LENGTH Mailbox 30 Data Length Code Register 0XFFC0 2FD4 CAN_MB30_TIMESTAMP Mailbox 30 Time Stamp Value Register 0XFFC0 2FD8 CAN_MB30_ID0 Mailbox 30 Identifier Low Register 0XFFC0 2FDC CAN_MB30_ID1 Mailbox 30 Identifier High Register 0XFFC0 2FE0 CAN_MB31_DATA0 Mailbox 31 Data Word 0 15 0 Register 0XFFC0 2FE4 CAN_MB31_DATA1 M...

Page 1248: ...XFFC0 3118 ACM_MS ACM Missed Event Status Register 0XFFC0 311C ACM_EMSK ACM Missed Event Interrupt Mask Register 0XFFC0 3120 ACM_ER0 ACM Event 0 Control Register 0XFFC0 3124 ACM_ER1 ACM Event 1 Control Register 0XFFC0 3128 ACM_ER2 ACM Event 2 Control Register 0XFFC0 312C ACM_ER3 ACM Event 3 Control Register 0XFFC0 3130 ACM_ER4 ACM Event 4 Control Register 0XFFC0 3134 ACM_ER5 ACM Event 5 Control Re...

Page 1249: ... Event 5 Time Register 0XFFC0 3198 ACM_ET6 ACM Event 6 Time Register 0XFFC0 319C ACM_ET7 ACM Event 7 Time Register 0XFFC0 31A0 ACM_ET8 ACM Event 8 Time Register 0XFFC0 31A4 ACM_ET9 ACM Event 9 Time Register 0XFFC0 31A8 ACM_ET10 ACM Event 10 Time Register 0XFFC0 31AC ACM_ET11 ACM Event 11 Time Register 0XFFC0 31B0 ACM_ET12 ACM Event 12 Time Register 0XFFC0 31B4 ACM_ET13 ACM Event 13 Time Register 0...

Page 1250: ...C0 370C PWM0_DT PWM0 Dead Time Register 0XFFC0 3710 PWM0_GATE PWM0 Chopping Control 0XFFC0 3714 PWM0_CHA PWM0 Channel A Duty Control 0XFFC0 3718 PWM0_CHB PWM0 Channel B Duty Control 0XFFC0 371C PWM0_CHC PWM0 Channel C Duty Control 0XFFC0 3720 PWM0_SEG PWM0 Crossover and Output Enable 0XFFC0 3724 PWM0_SYNCWT PWM0 Sync pulse width control 0XFFC0 3728 PWM0_CHAL PWM0 Channel AL Duty Control SR mode on...

Page 1251: ...egister 0XFFC0 3010 PWM1_GATE PWM1 Chopping Control 0XFFC0 3014 PWM1_CHA PWM1 Channel A Duty Control 0XFFC0 3018 PWM1_CHB PWM1 Channel B Duty Control 0XFFC0 301C PWM1_CHC PWM1 Channel C Duty Control 0XFFC0 3020 PWM1_SEG PWM1 Crossover and Output Enable 0XFFC0 3024 PWM1_SYNCWT PWM1 Sync pulse width control 0XFFC0 3028 PWM1_CHAL PWM1 Channel AL Duty Control SR mode only 0XFFC0 302C PWM1_CHBL PWM1 Ch...

Page 1252: ...sponse Register 0XFFC0 3818 RSI_RESPONSE1 RSI Response Register 0XFFC0 381C RSI_RESPONSE2 RSI Response Register 0XFFC0 3820 RSI_RESPONSE3 RSI Response Register 0XFFC0 3824 RSI_DATA_TIMER RSI Data Timer Register 0XFFC0 3828 RSI_DATA_LGTH RSI Data Length Register 0XFFC0 382C RSI_DATA_CONTROL RSI Data Control Register 0XFFC0 3830 RSI_DATA_CNT RSI Data Counter Register 0XFFC0 3834 RSI_STATUS RSI Statu...

Page 1253: ...DC Controller Module ACM Registers Memory Mapped Address Register Name For individual bits see this diagram 0XFFC0 3100 ACM_CTL ACM Control Register on page 22 32 0XFFC0 3104 ACM_TC0 ACM Timing Configuration 0 on page 22 39 0XFFC0 3108 ACM_TC1 ACM Timing Configuration1 on page 22 39 0XFFC0 310C ACM_STAT ACM Status Register on page 22 33 0XFFC0 3110 ACM_ES ACM Event Status Register on page 22 34 0X...

Page 1254: ...150 ACM_ER12 ACM Event12 Control Register on page 22 38 0XFFC0 3154 ACM_ER13 ACM Event13 Control Register on page 22 38 0XFFC0 3158 ACM_ER14 ACM Event14 Control Register on page 22 38 0XFFC0 315C ACM_ER15 ACM Event15 Control Register on page 22 38 0XFFC0 3180 ACM_ET0 ACM Event0 Time Register on page 22 39 0XFFC0 3184 ACM_ET1 ACM Event1 Time Register on page 22 39 0XFFC0 3188 ACM_ET2 ACM Event2 Tim...

Page 1255: ... on page 22 39 0XFFC0 31B0 ACM_ET12 ACM Event12 Time Register on page 22 39 0XFFC0 31B4 ACM_ET13 ACM Event13 Time Register on page 22 39 0XFFC0 31B8 ACM_ET14 ACM Event14 Time Register on page 22 39 0XFFC0 31BC ACM_ET15 ACM Event15 Time Register on page 22 39 Table A 30 ADC Controller Module ACM Registers Cont d Memory Mapped Address Register Name For individual bits see this diagram ...

Page 1256: ...ACM Registers A 50 ADSP BF50x Blackfin Processor Hardware Reference ...

Page 1257: ...st data are communicated A set of test features is defined including a boundary scan register such that the component can respond to a mini mum set of instructions designed to help test printed circuit boards The standard defines test logic that can be included in an integrated cir cuit to provide standardized approaches to Testing the interconnections between integrated circuits once they have be...

Page 1258: ...test registers An instruction register IR that interprets 5 bit instruction codes to select the test mode that performs the desired test operation Several data registers defined by the JTAG standard The TAP controller is a synchronous 16 state finite state machine con trolled by the TCK and TMS pins Transitions to the various states in the diagram occur on the rising edge of TCK and are defined by...

Page 1259: ... see the JTAG standard Figure B 1 shows the state diagram for the TAP controller Figure B 1 TAP Controller State Diagram Test Logic_Reset Run Test Idle Select DR Scan Capture DR Shift DR Exit1 DR Pause DR Exit2 DR Update DR Select IR Scan Capture IR Shift IR Exit1 IR Pause IR Exit2 IR Update IR 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ...

Page 1260: ...ter The instruction register is five bits wide and accommodates up to 32 boundary scan instructions The instruction register holds both public and private instructions The JTAG standard requires some of the public instructions other public instructions are optional Private instructions are reserved for the manu facturer s use The binary decode column of Table B 2 lists the decode for the public in...

Page 1261: ...ence B 5 Test Features Figure B 2 shows the instruction bit scan ordering for the paths shown in Table B 2 Figure B 2 Serial Scan Paths TDO TDI N N 1 N 2 2 1 0 0 1 30 31 4 3 2 1 0 1 Bypass Register Boundary Scan Register JTAG Instruction Register ...

Page 1262: ...re that nothing else drives data on the processor s output pins SAMPLE PRELOAD Binary Code 10000 The SAMPLE PRELOAD instruction performs two functions and selects the Boundary Scan register to be connected between TDI and TDO The instruction has no effect on internal logic The SAMPLE part of the instruction allows a snapshot of the inputs and outputs captured on the boundary scan cells Data is sam...

Page 1263: ...Reference B 7 Test Features Boundary Scan Register The boundary scan register is selected by the EXTEST and SAMPLE PRELOAD instructions These instructions allow the pins of the processor to be con trolled and sampled for board level testing ...

Page 1264: ...Boundary Scan Architecture B 8 ADSP BF50x Blackfin Processor Hardware Reference ...

Page 1265: ...ruction address bit 11 bit 2 6 ACKE bit 17 84 ACM 1 22 ACM busy BSY bit 22 33 ACM control ACM_CTL register 22 32 ACM_CTL ACM control register 22 32 ACM_EMSK ACM event missed interrupt mask register 22 37 ACM_ERx ACM event control registers 22 38 ACM_ES ACM event status register 22 34 ACM_ETx ACM event time registers 22 39 ACM event control ACM_ERx registers 22 38 ACM event interrupt mask ACM_IMSK ...

Page 1266: ...t 17 6 17 52 AMIDE bit 17 48 ANAK address not acknowledged bit 16 35 16 37 analog to digital converter See ADC application data loading 24 1 arbitration DAB 3 7 3 8 DCB 3 7 3 8 DEB 3 7 3 8 EAB 3 10 latency 3 10 TWI 16 8 architecture memory 2 1 array access bit 2 6 ARTS bit 15 31 asynchronous memory 5 6 memory bank address range table 14 24 asynchronous Flash memory parameter control EBIU_FCTL 5 12...

Page 1267: ...CT bit 24 13 24 73 BFLAG_INIT bit 24 13 24 73 BFLAG_NEXTDXE bit 24 72 BFLAG_NOAUTO bit 24 72 BFLAG_NONRESTORE bit 24 72 BFLAG_PERIPHERAL bit 24 72 BFLAG_QUICKBOOT bit 24 13 24 73 BFLAG_RESET bit 24 72 BFLAG_RETURN bit 24 72 BFLAG_SAVE bit 24 13 24 73 BFLAG_SLAVE bit 24 72 BFLAG_TYPE bit 24 72 BFLAG_WAKEUP bit 24 72 BI break indicator bit 15 35 BI break interrupt bit 15 34 binary decode B 4 bit 15 ...

Page 1268: ...ick 24 28 ROM functions 24 38 streams multi DXE 24 39 boot code date code BKDATECODE register 24 64 boot code ones BK_ONES register 24 66 boot code revision BKREVISION register 24 63 boot code zero word BK_ZEROS register 24 65 boot host wait HWAIT 24 19 booting 24 1 to 24 89 BFROM_MEMBOOT 24 38 BFROM_SPIBOOT 24 38 boot stream 24 9 host boot scenarios 24 10 indirect 24 29 initialization code execut...

Page 1269: ...errupt 17 25 acknowledge error 17 28 architecture 17 4 CAN continued auto transmit mode 17 15 bit error 17 28 bit timing 17 10 block diagram 17 3 bus interface 17 2 bus off interrupt 17 25 clock 17 10 code examples 17 85 configuration mode 17 9 17 12 CRC error 17 29 data field filtering 17 18 debug and test modes 17 33 enabling mailboxes 17 87 error frames 17 26 17 29 error levels 17 31 errors 17 ...

Page 1270: ...4 universal counter as event counter 17 26 universal counter exceeded interrupt 17 24 valid message 17 27 wakeup from hibernate 17 38 CAN continued wakeup interrupt 17 25 warnings 17 27 watchdog mode 17 19 CAN_AA1 abort acknowledge register 1 17 75 CAN_AA2 abort acknowledge register 2 17 75 CAN_AAx abort acknowledge registers 17 41 CAN_AMxxH acceptance mask register 17 6 17 40 17 48 CAN_AMxxL acce...

Page 1271: ...d 4 register 17 5 17 40 17 58 CAN_MBxx_TIMESTAMP mailbox word 5 register 17 5 17 40 CAN_MC1 mailbox configuration register 1 17 68 CAN_MC2 mailbox configuration register 2 17 68 CAN_MCx mailbox configuration registers 17 41 CAN_MD1 mailbox direction register 1 17 69 CAN_MD2 mailbox direction register 2 17 69 CAN_MDx mailbox direction registers 17 41 CAN_OPSS1 overwrite protection single shot trans...

Page 1272: ... operating mode 8 8 CCLK core processor clock 3 2 CCR bit 17 43 CDE bit 17 33 17 45 CDGINV CDG pin polarity invert bit 13 19 CDG pin polarity invert CDGINV bit 13 19 CDPRIO bit 3 8 5 8 5 10 CEVNT current event bits 22 33 channels defined serial 19 23 serial port TDM 19 23 serial select offset 19 23 CHNL 9 0 field 19 66 19 67 circuit board testing B 1 B 6 circular addressing 7 57 CKDIV clock diviso...

Page 1273: ...supported 19 29 multichannel operations 19 24 configuration CAN 17 12 SPORT 19 11 configuration CNT_CONFIG register 13 18 13 19 congestion on DMA channels 7 46 contention bus avoiding 5 6 continuous transition DMA 7 28 control bit summary general purpose timers 10 46 control byte sequences PPI 20 8 controller area network CAN 17 1 controller area network See CAN control register data memory 2 5 EB...

Page 1274: ... CS width bitfield 22 41 CS width CSW bitfield 22 41 CTS clear to send bit 15 36 CTYPE DMA channel type bit 7 67 CUD and CDZ input disable INPDIS bit 13 19 CUDINV CUD pin polarity invert bit 13 19 CUD pin polarity invert CUDINV bit 13 19 current address field 7 76 current address registers DMAx_CURR_ADDR 7 76 MDMA_yy_CURR_ADDR 7 76 current descriptor pointer DMAx_CURR_DESC_PTR registers 7 82 curre...

Page 1275: ...1 7 0 field 17 59 data field byte 2 7 0 field 17 62 data field byte 3 7 0 field 17 62 data field byte 4 7 0 field 17 64 data field byte 5 7 0 field 17 64 data field byte 6 7 0 field 17 66 data field byte 7 7 0 field 17 66 data field filtering CAN 17 18 data formats SPORT 19 28 data input modes for PPI 20 14 to 20 17 data instruction access bit 2 6 data memory control DMEM_CONTROL register 2 5 data...

Page 1276: ...a independent transmit frame sync select bit 19 37 19 48 19 51 19 62 divisor latch high byte 15 8 field 15 43 divisor latch low byte 7 0 field 15 43 divisor reset UART 15 44 DLC 3 0 field 17 58 DLEN 2 0 field 20 25 20 26 DMA 7 1 to 7 103 1 D interrupt driven 7 54 1 D unsynchronized FIFO 7 56 2 D polled 7 55 2 D array example 7 92 2 D interrupt driven 7 54 autobuffer mode 7 11 7 29 7 69 bandwidth 7...

Page 1277: ...y DMA 1 8 7 6 memory DMA streams 7 7 memory DMA transfers 7 5 memory read 7 26 operation flow 7 17 orphan access 7 29 DMA continued overflow interrupt 7 41 overview 1 8 performance considerations 7 43 peripheral 7 5 peripheral channels priority 7 6 peripheral interrupts 4 6 peripheral priority and default mapping 7 105 pipelining requests 7 38 polling DMA status example 7 95 polling registers 7 52...

Page 1278: ...eld 24 13 24 73 DMA Code field DMACODE 24 13 DMA configuration DMAx_CONFIG registers 7 68 DMA configuration MDMA_yy_CONFIG registers 7 68 DMA controller 7 2 DMA core bus See DCB DMA direction WNR bit 7 68 7 71 DMA_DONE bit 7 10 7 74 DMA_DONE interrupt 7 72 DMAEN bit 7 18 7 62 7 68 7 71 DMA_ERR bit 7 10 7 74 DMA_ERROR interrupt 7 30 DMA error interrupts 7 73 DMA external bus See DEB DMA performance...

Page 1279: ... 6 DRxSEC signal 19 5 DRxSEC SPORT input 19 6 DTEST_COMMAND data test command register 2 6 DTO bit 17 35 17 45 DTxPRI signal 19 5 DTxPRI SPORT output 19 6 DTxSEC signal 19 5 DTxSEC SPORT output 19 6 dynamic power management 1 24 8 1 controller 8 2 E EAB arbitration 3 10 and EBIU 5 4 frequency 3 10 performance 3 10 early frame sync 19 35 EAV signal 20 5 EBC 5 4 EBIU 1 6 5 1 to 5 12 as slave 5 4 blo...

Page 1280: ...18 40 to 18 42 error status register CAN_ESR 17 84 error warning receive interrupt CAN 17 26 error warning transmit interrupt CAN 17 26 ERR_TYP 1 0 field 10 7 10 41 10 42 10 47 ERR_TYP bits 10 29 ESx event x status bits 22 34 ETBEI bit 15 7 15 16 15 39 15 40 15 41 ETIME event time bits 22 39 event controller 4 2 event counter CAN 17 26 event enable ENAEV bit 22 38 event handling 4 2 event paramete...

Page 1281: ...memory controller 1 6 5 4 EBIU block diagram 5 4 Flash pins reset 6 78 FLD field indicator bit 20 30 FLD_SEL active field select bit 20 4 20 26 20 28 flex descriptors 7 3 FLGx slave select value bit 18 38 18 39 FLOW 2 0 field 7 23 7 24 7 56 7 68 7 69 flow charts CAN receive operation 17 17 CAN transmit operation 17 14 DMA 7 19 7 20 general purpose timers interrupt structure 10 6 GPIO 9 22 GPIO int...

Page 1282: ... 30 G GCALL general call bit 16 29 16 30 general call address TWI 16 10 general purpose interrupts 4 2 4 3 general purpose I O overview 1 9 general purpose I O See GPIO general purpose ports 9 1 to 9 42 assigning interrupt channels 9 18 interrupt channels 9 18 interrupt generation flow 9 17 latency 9 12 pin defaults 9 3 pins interrupt 9 16 throughput 9 12 general purpose ports See GPIO general pur...

Page 1283: ...CAN_STATUS 17 44 GM get more data bit 18 21 18 37 GPIO 1 9 9 1 to 9 42 assigned to same interrupt channel 9 21 clearing interrupt conditions 9 18 GPIO continued clear registers 9 15 code examples 9 41 configuration 9 13 data registers 9 13 9 14 9 15 direction registers 9 13 9 18 edge detection 9 17 edge sensitive 9 15 flow chart 9 22 function enable registers 9 12 9 13 9 16 input buffers 9 14 inpu...

Page 1284: ...ndard protocol 19 25 handshake DMA 1 8 handshake MDMA 7 8 interrupts 7 40 handshake MDMA configuration HMDMAx_BCINIT registers 7 37 handshake MDMA control HMDMAx_CONTROL registers 7 83 handshake MDMA control registers 7 85 handshake MDMA current block count HMDMAx_BCOUNT registers 7 38 7 86 handshake MDMA current block count registers HMDMAx_BCOUNT 7 87 handshake MDMA current edge count HMDMAx_ECO...

Page 1285: ...serial devices 19 3 ICIE illegal gray binary code interrupt enable bit 13 20 ICII illegal gray binary code interrupt identifier bit 13 21 IDE bit 17 52 idle state waking from 4 6 IEEE 1149 1 standard See JTAG standard IEx event x status interrupt enable bits 22 35 IMASK interrupt mask register initialization 4 8 information processing time IPT 17 11 INIT bit 24 25 initcall address symbol command 2...

Page 1286: ...determining source 4 5 DMA channels 4 6 DMA_ERROR 7 30 DMA error 7 74 DMA overflow 7 41 DMA queue completion 7 60 enabling 4 5 interrupts continued evaluation of GPIO interrupts 9 21 general purpose 4 2 4 3 general purpose timers 10 4 10 5 10 15 10 29 generated by peripherals 4 8 global 17 23 GPIO 9 16 9 18 9 21 handshake MDMA 7 40 initialization 4 8 inputs and outputs 4 4 mailbox 17 23 mapping 4 ...

Page 1287: ...ly submode 20 9 20 10 and DLEN field 20 25 entire field submode 20 9 frame start detect 20 34 frame synchronization 20 11 output 20 11 SAV codes 20 31 supported 1 15 vertical blanking interval only submode 20 9 20 10 J JTAG B 1 B 3 B 4 L L1 data cache 2 4 data memory 1 6 data memory subbanks 2 3 data SRAM 2 3 instruction memory 1 6 2 2 memory and core 3 4 memory and DMA controller 7 5 scratchpad R...

Page 1288: ...eive interrupt flag registers 17 80 mailbox transmit interrupt flag registers 17 79 mailbox word 0 register CAN_MBxx_DATA0 17 66 mailbox word 1 register CAN_MBxx_DATA1 17 64 mailbox word 2 register CAN_MBxx_DATA2 17 62 mailbox word 3 register CAN_MBxx_DATA3 17 59 mailbox word 4 register CAN_MBxx_LENGTH 17 58 mailbox word 6 register CAN_MBxx_ID0 17 54 17 56 mailbox word 7 register CAN_MBxx_ID1 17 5...

Page 1289: ...DDR start address registers 7 75 MDMA_yy_X_COUNT inner loop count registers 7 76 MDMA_yy_X_MODIFY inner loop address increment registers 7 78 MDMA_yy_Y_COUNT outer loop count registers 7 79 MDMA_yy_Y_MODIFY outer loop address increment registers 7 80 MDn bit 17 69 measurement report general purpose timers 10 25 10 27 10 28 memory 2 1 to 2 6 accesses to internal 2 1 architecture 1 4 2 1 boot ROM 2 ...

Page 1290: ...annel 19 15 serial port 19 11 SPI master 18 15 18 18 SPI slave 18 16 18 20 UART DMA 15 24 UART non DMA 15 22 MODF mode fault error bit 18 40 18 41 MOSI pin 18 5 18 12 18 15 18 16 18 21 moving data serial port 19 38 MPROG master transfer in progress bit 16 35 16 38 MRB bit 17 45 MRTS manual request to send bit 15 31 MSEL 5 0 field 8 4 8 21 MSTR master bit 18 36 18 37 multichannel frame 19 20 multic...

Page 1291: ...OUT_DIS bit 10 41 10 42 10 47 10 59 outer loop address increment registers DMAx_Y_MODIFY 7 80 MDMA_yy_Y_MODIFY 7 80 outer loop count registers DMAx_Y_COUNT 7 79 MDMA_yy_Y_COUNT 7 79 output pad disable timer 10 12 overflow interrupt DMA 7 41 overwrite protection single shot transmission register 1 CAN_OPSS1 17 72 overwrite protection single shot transmission register 2 CAN_OPSS2 17 72 P PAB 3 5 arb...

Page 1292: ... assignment 7 6 switching from DMA to non DMA 7 75 timing 3 4 used to wake from idle 4 6 PF0 pin 9 15 PFx pin 18 7 phase locked loop See PLL pin information 25 1 pins 25 1 GPIO 9 12 multiplexing 9 1 unused 25 10 pin terminations SPORT 19 9 pipeline lengths of 7 52 pipelining DMA requests 7 38 PJSE bit 9 27 9 28 9 29 PLL 8 1 to 8 29 active enabled but bypassed mode 8 9 active mode 8 9 applying powe...

Page 1293: ...ld 20 4 20 26 20 28 port connection SPORT 19 7 PORT_DIR bit 13 25 PORT_DIR direction bit 20 4 20 26 20 28 PORT_EN enable bit 20 26 20 29 port F GPIO 9 13 peripherals 9 1 structure 9 3 PORTF_FER function enable register 9 10 PORTF_HYSTERESIS register 9 24 port G GPIO 9 13 peripherals 9 2 9 5 structure 9 5 PORTG_FER function enable register 9 10 PORTG_HYSTERESIS register 9 25 port H GPIO 9 13 periph...

Page 1294: ...egisters 9 37 PORTxIO_MASKB_TOGGLE GPIO mask interrupt B toggle registers 9 41 PORTxIO_MASKB_TOGGLE registers 9 41 PORTxIO_POLAR GPIO polarity registers 9 33 PORTxIO_POLAR registers 9 33 PORTxIO registers 9 31 PORTxIO_SET GPIO set registers 9 32 PORTxIO_SET registers 9 32 PORTxIO_TOGGLE GPIO toggle registers 9 33 PORTxIO_TOGGLE registers 9 33 PORTx_MUX port multiplexer control register 9 3 9 27 9 ...

Page 1295: ...20 33 number of samples 20 32 operating modes 20 4 20 25 overview 1 14 port width 20 27 preamble 20 7 programming model 20 22 progressive video 20 6 PPI continued submodes for ITU R 656 20 9 and synchronization with DMA 20 13 timer pins 20 21 transfer delay 20 18 TX modes with external frame syncs 20 21 TX modes with internal frame syncs 20 19 valid data detection 20 15 vertical blanking interval ...

Page 1296: ...A 14 37 PWM_CHAL 14 38 PWM chapter 14 1 PWM_CHB 14 37 PWM_CHBL 14 38 PWM_CHC 14 37 PWM_CHCL 14 38 PWM_CLK clock 10 21 PWM_CLK signal 10 21 PWM_CTL 14 37 PWM_DT 14 37 PWM_GATE 14 37 PWM_LSI 14 38 PWM_OUT mode 10 10 to 10 23 10 44 control bit and register usage 10 46 error prevention 10 45 externally clocked 10 21 PULSE_HI toggle mode 10 16 stopping the timer 10 22 PWM_SEG 14 37 PWM_STAT 14 37 PWM_S...

Page 1297: ...ling register 1 CAN_RFH1 17 77 remote frame handling register 2 CAN_RFH2 17 78 Removable Storage Interface chapter 21 1 REP bit 7 39 7 85 request data control command DMA 7 35 request data urgent control command DMA 7 35 reserved external memory 5 3 reset effect on SPI 18 16 reset Flash pins 6 78 RESET_DOUBLE bit 24 60 RESET pin 24 5 resets core and system 24 82 24 83 core double fault 24 4 core o...

Page 1298: ...gnal 15 9 RXSE RxSEC enable bit 19 54 19 56 RXS RX data buffer status bit 18 23 18 40 S SA0 bit 17 84 SADDR 6 0 field 16 29 SAM bit 17 46 SAMPLE PRELOAD instruction B 6 sampling CAN 17 11 sampling edge SPORT 19 33 SAV codes 20 31 SAV signal 20 5 SB set break bit 15 28 scale value 7 0 field 11 6 scaling of core timer 11 7 scan paths B 5 SCCB bit 16 26 scheduling memory DMA 7 47 SCK signal 18 5 18 1...

Page 1299: ...y 25 5 signalling via semaphores 25 2 sine wave input 1 23 single pulse generation timer 10 13 single shot transmission CAN 17 14 SINITM slave transfer initiated interrupt mask bit 16 42 SINIT slave transfer initiated bit 16 43 16 45 size of accesses timer registers 10 36 SIZE size of words bit 18 36 18 37 SJW 1 0 field 17 46 SJW 1 0 synchronization jump width field 17 11 SKIP_EN skip enable bit 2...

Page 1300: ...gnal 18 5 slave boot mode 24 51 slave device 18 5 slave mode 18 16 18 20 slave mode DMA operation 18 27 SPI continued slave select function 18 38 slave transfer preparation 18 22 SPI_FLG mapping to port pins 18 39 starting DMA transfer 18 51 starting transfer 18 46 stopping 18 48 stopping DMA transfers 18 51 switching between transmit and receive 18 23 timing 18 6 transfer formats 18 12 to 18 14 t...

Page 1301: ...9 20 multichannel operation 19 15 to 19 25 multichannel transfer timing 19 17 overview 1 16 packing data multichannel DMA 19 24 SPORT continued peripheral access bus error 19 39 pin line terminations 19 9 port connection 19 7 receive and transmit functions 19 4 receive clock signal 19 30 receive FIFO 19 59 receive word length 19 60 register writes 19 46 RX hold register 19 60 sampling edge 19 33 s...

Page 1302: ...mit data registers 19 19 19 37 19 57 SRAM ADDR 13 12 field 2 6 SRS bit 17 43 SSEL 3 0 field 3 4 8 5 8 20 SSEL bit 25 2 SSEL system select bit 8 20 start address registers DMAx_START_ADDR 7 75 MDMA_yy_START_ADDR 7 75 status CNT_STATUS register 13 18 13 21 STB stop bits bit 15 28 STDVAL slave transmit data valid bit 16 27 16 28 stereo serial data 19 3 device SPORT connection 19 9 frame sync modes 19...

Page 1303: ...o 24 89 SYSTEM_RESET 2 0 field 24 60 system reset configuration register SYSCR 24 61 24 62 system reset configuration SYSCR register 24 61 system select SSEL bit 8 20 system software reset 24 4 SZ send zero bit 18 21 18 37 T TAn bit 17 76 TAP registers boundary scan B 7 BYPASS B 6 instruction B 2 B 4 TAP test access port B 1 B 2 controller B 2 target address 24 17 TAUTORLD bit 11 3 11 5 TCKFE cloc...

Page 1304: ... 10 5 10 36 10 37 timer input select TIN_SEL bit 10 42 10 47 timer interrupt TIMILx bits 10 4 10 40 timer period 15 0 field 10 45 timer period 31 16 field 10 45 timer period TIMERx_PERIOD registers 10 4 10 44 10 45 timers 10 1 to 10 58 core 11 1 to 11 8 EXT_CLK mode 10 33 overview 1 18 watchdog 1 23 12 1 to 12 10 WDTH_CAP mode 15 22 TIMER_STATUS timer status register 10 5 10 39 10 40 timer status ...

Page 1305: ...ledge register 2 CAN_TA2 17 76 transmission error SPI 18 42 transmission request reset register 1 CAN_TRR1 17 74 transmission request reset register 2 CAN_TRR2 17 74 transmission request set register 1 CAN_TRS1 17 73 transmission request set register 2 CAN_TRS2 17 73 transmit clock serial TSCLKx pins 19 30 transmit collision error SPI 18 42 transmit configuration registers SPORTx_TCR1 and SPORTx_T...

Page 1306: ...trol register 16 27 TWI_SLAVE_STAT TWI slave mode status register 16 30 two dimensional DMA 7 11 two wire interface See TWI TXCOL flag 18 42 TXCOL transmit collision error bit 18 40 TXECNT 7 0 field 17 84 TXE transmission error bit 18 40 18 42 19 58 19 63 TXF transmit FIFO full status bit 19 62 TX hold register 19 57 TXHRE transmit hold register empty bit 19 63 TXREQ signal 15 7 TXSE TxSEC enable ...

Page 1307: ...t UARTx_IER_SET registers 15 39 UART interrupt enable UARTx_IER registers 15 39 UART line control registers UARTx_LCR 15 28 UART line control UARTx_LCR registers 15 28 UART line status registers UARTx_LSR 15 33 UART line status UARTx_LSR registers 15 34 UART modem control UARTx_MCR registers 15 31 UART modem status UARTx_MSR registers 15 36 UART ports overview 1 19 UART receive buffer registers UA...

Page 1308: ... 17 82 UCCNT 15 0 field 17 83 UCCT bit 17 82 UCE bit 17 82 UCEIF bit 17 24 17 48 UCEIM bit 17 24 17 47 UCEIS bit 17 24 17 47 UCEN bit 15 8 15 18 15 45 15 46 UCIE up count interrupt enable bit 13 20 UCII up count interrupt identifier bit 13 21 UCRC 15 0 field 17 83 UCRC bit 17 82 UIAIF bit 17 25 17 48 UIAIM bit 17 25 17 47 UIAIS bit 17 25 17 47 UNDR FIFO underrun bit 20 30 20 31 unframed framed ser...

Page 1309: ... value 12 5 features 12 2 internal interface 12 3 overview 1 23 registers 12 5 reset 12 5 24 4 24 5 starting 12 4 waveform generation pulse width modulation 10 14 WBA bit 17 43 WDEN 7 0 field 12 7 WDEV 1 0 field 12 4 12 7 WDOG_CNT watchdog count register 12 5 12 6 WDOG_CTL watchdog control register 12 7 12 8 WDOG_STAT watchdog status register 12 3 12 4 12 6 12 7 WDRESET bit 24 61 WDSIZE 1 0 field ...

Page 1310: ...MTFLUSH transmit buffer flush bit 16 38 16 40 XMTINTLEN transmit buffer interrupt length bit 16 38 16 39 XMTSERVM transmit FIFO service interrupt mask bit 16 42 XMTSERV transmit FIFO service bit 16 43 16 44 XMTSTAT 1 0 field 16 40 16 41 XOFF transmitter off bit 15 31 Y YCbCr format 20 27 Y_COUNT 15 0 field 7 79 Y_MODIFY 15 0 field 7 81 Z ZC zero cycle bitfield 22 41 zero cycle ZC bitfield 22 41 ZM...

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