Analog Devices EZ-KIT Lite ADSP-BF506F, Hardware Reference Manual

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ADSP-BF50x Blackfin Processor Hardware Reference 8-13
Dynamic Power Management
In addition to the mode transitions shown in Figure 8-2 , the PLL can be
modified while in active operating mode. Changes to the PLL do not take
effect immediately. As with operating mode transitions, the PLL program-
ming sequence must be executed for these changes to take effect (see
“Programming Operating Mode Transitions” on page 8-14 ).
• PLL disabled: In addition to being bypassed in the active mode, the
PLL can be disabled.
When the PLL is disabled, additional power savings are achieved
although they are relatively small. To disable the PLL, set the
PLL_OFF
bit in the
PLL_CTL
register, and then execute the PLL pro-
gramming sequence.
• PLL enabled: When the PLL is disabled, it can be re-enabled later
when additional performance is required.
The PLL must be re-enabled before transitioning to the full-on or
sleep operating modes. To re-enable the PLL, clear the
PLL_OFF
bit
in the
PLL_CTL
register, and then execute the PLL programming
sequence.
• New multiplier ratio: The multiplier ratio can also be changed
while in full-on mode.
The PLL state automatically transitions to active mode while the
PLL is locking. After locking, the PLL returns to full-on mode. To
program a new
CLKIN
to VCO multiplier, write the new
MSEL[5:0]
and/or
DF
values to the
PLL_CTL
register; then execute the PLL pro-
gramming sequence ( on page 8-14 ).
Table 8-6 summarizes the allowed operating mode transitions.