Analog Devices EZ-KIT Lite ADSP-BF506F, Hardware Reference Manual

Page: 346 / 1310

Phase Locked Loop and Clock Control
8-4 ADSP-BF50x Blackfin Processor Hardware Reference
intermediate clock from which the core clock (
CCLK
) and system clock
(
SCLK
) are derived.
PLL Clock Multiplier Ratios
The PLL control register (
PLL_CTL
) governs the operation of the PLL. For
details about the
PLL_CTL
register, see “PLL_CTL Register” on page 8-21 .
The divide frequency (
DF
) bit and multiplier select (
MSEL[5:0]
) field con-
figure the various PLL clock dividers:
•
DF
enables the input divider
•
MSEL[5:0]
controls the feedback dividers
The reset value of
MSEL
is 0x6. This value can be reprogrammed at startup
in the boot code.
Table 8-1 illustrates the VCO multiplication factors for the various
MSEL
and
DF
settings.
As shown in the table, different combinations of MSEL[5:0] and DF can
generate the same VCO frequencies. For a given application, one combi-
nation may provide lower power or satisfy the VCO maximum frequency.
Under normal conditions, setting DF to 1 typically results in lower power
dissipation. See the processor data sheet for maximum and minimum fre-
quencies for CLKIN, CCLK, and VCO.
Table 8-1. MSEL Encodings
Signal name VCO Frequency
MSEL[5:0] DF = 0 DF = 1
5 5x 1.5x
6 6x 3x
N = 7–62 Nx 0.5Nx