Programming Examples
10-56
ADSP-BF50x Blackfin Processor Hardware Reference
r7 = [p5 + TIMER5_PERIOD - TIMER_ENABLE];
r6 = [p5 + TIMER5_WIDTH - TIMER_ENABLE];
r5 = r7 - r6;
[p5 + TIMER5_WIDTH - TIMER_ENABLE] = r5;
r5 = [p5 + TIMER4_WIDTH - TIMER_ENABLE];
r7 = r7 - r5;
CC = r7 < 0;
if CC r7 = r6;
[p5 + TIMER4_WIDTH - TIMER_ENABLE] = r7;
/* disable after a certain number of periods */
r0+= -1;
CC = r0 == 0;
r5.l = 0;
r7.l = TIMDIS5 | TIMDIS4;
if !CC r7 = r5;
w[p5 + TIMER_DISABLE - TIMER_ENABLE] = r7;
(r7:5, p5:5) = [sp++];
astat = [sp++];
rti;
isr_timer5.end:
Listing 10-5
generates N pulses on both timer output pins. Disabling the
timers does not corrupt the generated pulse pattern anyhow.
Listing 10-6
configures timer 5 in
WDTH_CAP
mode. If looped back exter-
nally, this code might be used to receive N PWM patterns generated by
one of the other timers. Ensure that the PWM generator and consumer
both use the same
PERIOD_CNT
and
PULSE_HI
settings.
Listing 10-6. Timer Configured in WDTH_CAP Mode
.section L1_data_a;
.align 4;
#define N 1024
.var buffReceive[N*2];
Summary of Contents for EZ-KIT Lite ADSP-BF506F
Page 50: ...Contents l ADSP BF50x Blackfin Processor Hardware Reference ...
Page 92: ...Development Tools 1 30 ADSP BF50x Blackfin Processor Hardware Reference ...
Page 110: ...Interface Overview 3 12 ADSP BF50x Blackfin Processor Hardware Reference ...
Page 236: ...Internal Flash Memory Control Registers 6 92 ADSP BF50x Blackfin Processor Hardware Reference ...
Page 650: ...Programming Examples 15 56 ADSP BF50x Blackfin Processor Hardware Reference ...
Page 804: ...Programming Examples 17 92 ADSP BF50x Blackfin Processor Hardware Reference ...
Page 1194: ...Programming Examples 24 90 ADSP BF50x Blackfin Processor Hardware Reference ...
Page 1256: ...ACM Registers A 50 ADSP BF50x Blackfin Processor Hardware Reference ...
Page 1264: ...Boundary Scan Architecture B 8 ADSP BF50x Blackfin Processor Hardware Reference ...