Architecture
843
SPRUH82C – April 2013 – Revised September 2016
Copyright © 2013–2016, Texas Instruments Incorporated
External Memory Interface A (EMIFA)
Table 19-11. SDRAM LOAD MODE REGISTER Command
EMA_A[9:7]
EMA_A[6:4]
EMA_A[3]
EMA_A[2:0]
0 (Write bursts are of
the programmed burst
length in EMA_A[2:0])
These bits control the CAS latency of the
SDRAM and are set according to CL field in
the SDRAM configuration register (SDCR)
as follows:
• If CL = 2, EMA_A[6:4] = 2h
(CAS latency = 2)
• If CL = 3, EMA_A[6:4] = 3h
(CAS latency = 3)
0 (Sequential Burst
Type. Interleaved
Burst Type not
supported)
These bits control the burst length of the
SDRAM and are set according to the NM
field in the SDRAM configuration register
(SDCR) as follows:
• If NM = 0, EMA_A[2:0] = 2h
(Burst Length = 4)
• If NM = 1, EMA_A[2:0] = 3h
(Burst Length = 8)
19.2.4.5 SDRAM Configuration Procedure
There are two different SDRAM configuration procedures. Although EMIFA automatically performs the
SDRAM initialization sequence described in
when coming out of reset, it is recommended
to follow one of the procedures listed below before performing any EMIFA memory requests. Procedure A
should be followed if it is determined that the SDRAM Power-up constraint was not violated during the
SDRAM Auto-Initialization Sequence detailed in
on coming out of Reset. The SDRAM
Power-up constraint specifies that 200
μ
s (sometimes 100
μ
s) should exits between receiving stable Vdd
and CLK and the issuing of a PRE command. Procedure B should be followed if the SDRAM Power-up
constraint was violated. The 200
μ
s (100
μ
s) SDRAM Power-up constraint will be violated if the frequency
of EMA_CLK is greater than 50 MHz (100 MHz for 100
μ
s SDRAM power-up constraint) during SDRAM
Auto-Initialization Sequence. Procedure B should be followed if there is any doubt that the Power-up
constraint was met.
Procedure A
— Following is the procedure to be followed if the SDRAM Power-up constraint was NOT
violated:
1. Place the SDRAM into Self-Refresh Mode by setting the SR bit of SDCR to 1. A byte-write to the upper
byte of SDCR should be used to avoid restarting the SDRAM Auto-Initialization Sequence described in
. The SDRAM should be placed into Self-Refresh mode when changing the frequency
of EMA_CLK to avoid incurring the 200
μ
s Power-up constraint again.
2. Program the CPU's PLL Controller to provide the desired EMA_CLK clock frequency. Refer to the
device Data Manual for details on programming the PLL Controller. The frequency of the memory clock
must meet the timing requirements in the SDRAM manufacturer's documentation and the timing
limitations shown in the electrical specifications of the device Data Manual.
3. Remove the SDRAM from Self-Refresh Mode by clearing the SR bit of SDCR to 0. A byte-write to the
upper byte of SDCR should be used to avoid restarting the SDRAM Auto-Initialization Sequence
described in
4. Program SDTIMR and SDSRETR to satisfy the timing requirements for the attached SDRAM device.
The timing parameters should be taken from the SDRAM datasheet.
5. Program the RR field of SDRCR to match that of the attached device's refresh interval. See
details on determining the appropriate value.
6. Program SDCR to match the characteristics of the attached SDRAM device. This will cause the auto-
initialization sequence in
to be re-run. This second initialization generally takes much
less time due to the increased frequency of EMA_CLK.
Procedure B
— Following is the procedure to be followed if the SDRAM Power-up constraint was
violated:
1. Program the CPU's PLL Controller to provide the desired EMA_CLK clock frequency. Refer to the
device Data Manual for details on programming the PLL Controller. The frequency of the memory clock
must meet the timing requirements in the SDRAM manufacturer's documentation and the timing
limitations shown in the electrical specifications of the device Data Manual.
2. Program SDTIMR and SDSRETR to satisfy the timing requirements for the attached SDRAM device.
The timing parameters should be taken from the SDRAM datasheet.
