Samsung S5PC100, Руководство пользователя

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IRDA S5PC100 USER’S MANUAL (REV1.0)
8.4-14
6.5 IRDA INTERUPT IDENTIFICATION REGISTER(IRDA_IIR, R, ADDRESS = 0XEC60_0010)
IrDA _IIR Bit Description Initial State
Last Byte to Rx
FIFO [7] Last byte write to RX FIFO interrupt pending. If the last payload
byte of the frame is loaded into the RX FIFO, bit 7 is set to '1'. Bit
7 is set prior to bit 2. Bit 7 is cleared if it is read. 0
Error Indication [6] Receiver line error Indication. Bit 6 is set to a '1' if one of three
possible errors occurs in the RX process. With the corresponding
interrupt enable bit active, one of PHY, CRC and Frame length
errors let this bit go active. Bit 6 is cleared if the source of the error
is cleared. 0
Tx Underrun [5] Transmit under-run interrupt pending. If corresponding interrupt
enable bit is active, bit 5 is set to '1' if an under-run occurs in TX
FIFO. Bit 5 is cleared by serving the under-run. 0
Last Byte Detect [4] Detects last byte of a frame interrupt pending. If the corresponding
interrupt enable bit is active, bit 4 is set to '1' if the demodulation
block detects the last byte of a received frame and the CRC
decoding is finished. Bit 4 is cleared if it is read. 0
Rx Overrun [3] RX FIFO over-run interrupt. If corresponding interrupt enable bit is
set, bit 3 is active, bit 3 is set to '1' if an overrun occurs in the RX
FIFO. Bit 3 is cleared by serving the over-run. 0
Last Byte Read
from Rx FIFO [2] RX FIFO last byte read interrupt. If corresponding interrupt enable
bit is active, it is set to '1' if the CPU reads the last byte of a frame
from the RX FIFO. It is cleared if it is read. 0
Tx FIFO Below
Threshold [1] TX FIFO below threshold interrupt pending. Bit 1 is set to '1' if the
transmitter FIFO level is below its threshold level. 0
Rx FIFO Over
Threshold [0] RX FIFO over threshold interrupt pending. Bit 0 is set to '1' if the
receiver FIFO level is equal to or above its threshold level. 0