Samsung S5PC100, Руководство пользователя

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I2S CONTROLLER(5.1CH) S5PC100 USER’S MANUAL (REV1.0)
10.2-12
RX CHANNEL
The I2S RX channel provides a single stereo compliant output. The receive channel operates in master or slave
mode. Data is received from the input line and transferred into the RX FIFO. Then processor reads this data via
an APB read or a DMA access.
RX Channel has 64 X 32-bit wide RX FIFO where the processor or DMA is read up to 16 left/ right data samples
after enabling the channel for reception.
For Example:
Ensure the PCLK and CODCLKI are coming correctly to the I2S controller. FLUSH the RX FIFO using the
RFLUSH bit in the I2SFIC Register (I2S FIFO Control Register). The I2S controller is configured in any of the
following modes
•
Receive only.
•
Receive/ Transmit simultaneous mode
This is done by Programming the TXR bit in the I2SMOD Register (I2S Mode Register)
1. Then Program the following parameters according to the need
♦
IMS
♦
SDF
♦
BFS
♦
BLC
♦
LRP
For Programming, the above mentioned fields please refer to I2SMOD Register (I2S Mode Register)
2. After ensuring that the input clocks for I2S controller are up and running and step 1 and 2 have been
completed, you must put the I2SACTIVE high to enable any reception of data, the I2S Controller
receives data on the LRCLK change.
The Data must be read from the RX FIFO using the I2SRXD Register (I2S RX FIFO Register) only after looking
at the RX FIFO count in the I2SFIC Register (I2S FIFO Control Register). The count would only increment
once the complete left channel and right have been received.